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[SUCCESS] Gigabyte Designare Z390 (Thunderbolt 3) + i7-9700K + AMD RX 580

nels1 said:
Thank you for your answer, I still have the CLOVER/drivers64UEFI present, so I will delete it, but before, here's a screenshot of what I've got now. Do I need to move HFSPlus-64.efi & VirtualSmc.efi to CLOVER/drivers/UEFI ?
And what about this nvram.plist ! I don't even know what is it and if I need it.
Thanks
Click to expand...
Please do the following:
  • drivers/UEFI folder:
    • Delete OsxAptioFix3Drv.efi
  • Then copy only these files from drivers64UEFI to drivers/UEFI:
    • HFSPlus-64.efi
    • OsxAptioFix2Drv-free2000.efi
    • VirtualSmc.efi
  • Now delete the entire drivers64UEFI folder and empty the trash.
  • The file nvram.plist is okay -- it stores NVRAM data when native NVRAM support has not been enabled.
 
CaseySJ said:
@Elias64Fr,

Okay, after connecting the Apple Thunderbolt-to-Gigabit Ethernet via Apple TB3-to-TB2 adapter, look what we get!!

View attachment 451852View attachment 451853View attachment 451854View attachment 451855View attachment 451856View attachment 451857View attachment 451858View attachment 451859View attachment 451860
Above results obtained with:
  • Thunderbolt Boot Support disabled
  • GPIO3 Force Power disabled
Click to expand...
@CaseySJ , GREAT !

I haven't tried any TBT1 devices (don't have) but it's a good news that it's now detected.

About Link speed, the only property which could change 20Gbps x2 to 40Gbps 1x is linkDetailsb ... but its might be normal when self detecting speed link (to verify it you should boot without any device connected)

About ASPM, I dont know if it is required to change current value but if we want to be closest as possible off all rMacs, I have found new methodology to configure different parameters (Cache Line Size for Legacy devices, ASPM, Extended Tag, ClockPM and Common Clk) of each devices by adding some news data on CNHI method (currently renamed as CONF () ).
I have also modified MMBA method to have a standard final SSDT file.
Method (CONF, 0, Serialized)
{
DBG1 ("Configure Thunderbolt ...")
Local0 = 0x0A
While (Local0)
{
RP0C = 0x40 / Cache Line Size stetted to 256 bytes
RP20 = R020
RP24 = R024
RP28 = R028
RP2C = R02C
RPRL = One / Retrain Link (probably not required!)
RPAS = Zero / ASPM configuration, set to Zero (disabled)
RPCC = One / Common Clock enabled
RPLB = Zero /Link Bandwidth Management Interrupt Enable
RPPD = Zero / Device Power state (Probably not required! but) setted to D0 (active state)
RPNR = One / No Soft Reset (PM for transition from D3 to D0, depending on initial state of LSPCI results)
RP04 = 0x07
If ((R020 == RP20))
{
Break
}

Sleep (One)
Local0--
}

If ((R020 != RP20))
{
DBG1 ("Configure Root Port failed!")
Return (Zero)
}
Else
{
DBG1 ("Configure Root Port done")
}

Local0 = 0x0A
While (Local0)
{
UP0C = 0x40
UP18 = R118 /* \_SB_.PCI0.RP05.R118 */
UP19 = R119 /* \_SB_.PCI0.RP05.R119 */
UP1A = R11A /* \_SB_.PCI0.RP05.R11A */
UP1C = R11C /* \_SB_.PCI0.RP05.R11C */
UP20 = R120 /* \_SB_.PCI0.RP05.R120 */
UP24 = R124 /* \_SB_.PCI0.RP05.R124 */
UP28 = R128 /* \_SB_.PCI0.RP05.R128 */
UP2C = R12C /* \_SB_.PCI0.RP05.R12C */
UPET = One / Extended tag (Probably not required but different from rMacs)
UPAS = Zero
UPCC = One
UPCP = Zero
UP04 = 0x07
If ((R119 == UP19))
{
Break
}

Sleep (One)
Local0--
}

If ((R119 != UP19))
{
DBG1 ("Configure UpStreamBridge failed!")
Return (Zero)
}
Else
{
DBG1 ("Configure UpStreamBridge done")
}

If ((WTLT () == One)){}
Else
{
Return (Zero)
}

Local0 = 0x0A
While (Local0)
{
DP0C = 0x40
DP18 = R218 /* \_SB_.PCI0.RP05.R218 */
DP19 = R219 /* \_SB_.PCI0.RP05.R219 */
DP1A = R21A /* \_SB_.PCI0.RP05.R21A */
DP1C = R21C /* \_SB_.PCI0.RP05.R21C */
DP20 = R220 /* \_SB_.PCI0.RP05.R220 */
DP24 = R224 /* \_SB_.PCI0.RP05.R224 */
DP28 = R228 /* \_SB_.PCI0.RP05.R228 */
DP2C = R22C /* \_SB_.PCI0.RP05.R22C */
DPET = One
DPRL = One
DPAS = Zero
DPCC = One
DPLB = Zero
DP04 = 0x07
DBG1 ("Configure DownStreamBridge0 done")
D30C = 0x40
D318 = R318 /* \_SB_.PCI0.RP05.R318 */
D319 = R319 /* \_SB_.PCI0.RP05.R319 */
D31A = R31A /* \_SB_.PCI0.RP05.R31A */
D31C = R31C /* \_SB_.PCI0.RP05.R31C */
D320 = R320 /* \_SB_.PCI0.RP05.R320 */
D324 = R324 /* \_SB_.PCI0.RP05.R324 */
D328 = R328 /* \_SB_.PCI0.RP05.R328 */
D32C = R32C /* \_SB_.PCI0.RP05.R32C */
D3ET = One
D3AS = Zero
D304 = 0x07
DBG1 ("Configure DownStreamBridge1 done")
D40C = 0x40
D418 = R418 /* \_SB_.PCI0.RP05.R418 */
D419 = R419 /* \_SB_.PCI0.RP05.R419 */
D41A = R41A /* \_SB_.PCI0.RP05.R41A */
D41C = R41C /* \_SB_.PCI0.RP05.R41C */
D420 = R420 /* \_SB_.PCI0.RP05.R420 */
D424 = R424 /* \_SB_.PCI0.RP05.R424 */
D428 = R428 /* \_SB_.PCI0.RP05.R428 */
D42C = R42C /* \_SB_.PCI0.RP05.R42C */
D4ET = One
D4RL = One
D4AS = Zero
D4CC = One
D4LB = Zero
DVES = RVES /* \_SB_.PCI0.RP05.RVES */
D404 = 0x07
DBG1 ("Configure DownStreamBridge2 done")
D50C = 0x40
D518 = R518 /* \_SB_.PCI0.RP05.R518 */
D519 = R519 /* \_SB_.PCI0.RP05.R519 */
D51A = R51A /* \_SB_.PCI0.RP05.R51A */
D51C = R51C /* \_SB_.PCI0.RP05.R51C */
D520 = R520 /* \_SB_.PCI0.RP05.R520 */
D524 = R524 /* \_SB_.PCI0.RP05.R524 */
D528 = R528 /* \_SB_.PCI0.RP05.R528 */
D52C = R52C /* \_SB_.PCI0.RP05.R52C */
D5ET = One
D5AS = Zero
D504 = 0x07
DBG1 ("Configure DownStreamBridge4 done")
If ((R219 == DP19))
{
Break
}

Sleep (One)
Local0--
}

If ((R219 != DP19))
{
DBG1 ("Configure DownStreamBridges failed!")
Return (Zero)
}

If ((WTDL () == One))
{
DBG1 ("Configure DownStreamBridges done")
}
Else
{
Return (Zero)
}

Local0 = 0x64
While (Local0)
{
NH0C = 0x40
NH10 = RH10 /* \_SB_.PCI0.RP05.RH10 */
NH14 = RH14 /* \_SB_.PCI0.RP05.RH14 */
NHET = One
NHAS = Zero
NHCC = One
NHCP = Zero
NHPS = Zero
NH04 = 0x07
If ((RH10 == NH10))
{
Break
}
Else
{
}

Sleep (One)
Local0--
}

If ((RH10 != NH10))
{
DBG1 ("Configure NHI0 failed!")
Return (Zero)
}

If ((WTDL () == One))
{
DBG1 ("Configure NHI0 done")
}
Else
{
Return (Zero)
}

Local0 = 0x64
While (Local0)
{
XH0C = 0x40
XHET = One
XHAS = Zero
XHCC = One
XHCP = Zero
XHPS = Zero
XH04 = 0x07
If ((XH0C == 0x40))
{
Break
}
Else
{
}

Sleep (One)
Local0--
}

If ((XH0C != 0x40))
{
DBG1 ("Configure XHC2 failed!")
Return (Zero)
}

If ((WTDL () == One))
{
DBG1 ("Configure XHC2 done")
}
Else
{
Return (Zero)
}

DBG1 ("Configure Thunderbolt finished")
Return (One)
}
OperationRegion (RPSM, SystemMemory, MMBA (One), 0xA8)
Field (RPSM, DWordAcc, NoLock, Preserve)
{
RPVD, 32,
RP04, 8,
Offset (0x0C),
RP0C, 8,
Offset (0x18),
RP18, 8,
RP19, 8,
RP1A, 8,
Offset (0x1C),
RP1C, 16,
Offset (0x20),
RP20, 32,
RP24, 32,
RP28, 32,
RP2C, 32,
Offset (0x3E),
, 6,
RRST, 1,
Offset (0x50),
RPAS, 2,
, 3,
RPRL, 1,
RPCC, 1,
, 3,
RPLB, 1,
Offset (0x52),
, 11,
RPLT, 1,
Offset (0x58),
, 3,
RPPD, 1,
Offset (0xA0),
Offset (0xA1),
Offset (0xA2),
Offset (0xA4),
, 3,
RPNR, 1,
Offset (0xA8)
}

OperationRegion (RPSB, SystemMemory, MMBA (One), 0x5C)
Field (RPSB, DWordAcc, NoLock, Preserve)
{
Offset (0x18),
RB18, 32,
Offset (0x44),
RB44, 32,
RB48, 16,
RB4A, 16,
RB4C, 32,
RB50, 16,
RB52, 16,
RB54, 32,
RB58, 16,
RB5A, 16
}

OperationRegion (UPSM, SystemMemory, MMBA (0x02), 0x0550)
Field (UPSM, DWordAcc, NoLock, Preserve)
{
UPVD, 32,
UP04, 8,
Offset (0x08),
CLRD, 32,
UP0C, 8,
Offset (0x18),
UP18, 8,
UP19, 8,
UP1A, 8,
Offset (0x1C),
UP1C, 16,
Offset (0x20),
UP20, 32,
UP24, 32,
UP28, 32,
UP2C, 32,
Offset (0xC9),
UPET, 1,
Offset (0xD0),
UPAS, 2,
, 4,
UPCC, 1,
Offset (0xD1),
UPCP, 1,
Offset (0xD2),
, 11,
UPLT, 1,
Offset (0xD4),
Offset (0x544),
UPMB, 1,
Offset (0x548),
T2PR, 32,
P2TR, 32
}

OperationRegion (DNSM, SystemMemory, MMBA (0x03), 0xD4)
Field (DNSM, DWordAcc, NoLock, Preserve)
{
DPVD, 32,
DP04, 8,
Offset (0x0C),
DP0C, 8,
Offset (0x18),
DP18, 8,
DP19, 8,
DP1A, 8,
Offset (0x1C),
DP1C, 16,
Offset (0x20),
DP20, 32,
DP24, 32,
DP28, 32,
DP2C, 32,
Offset (0xC9),
DPET, 1,
Offset (0xD0),
DPAS, 2,
, 3,
DPRL, 1,
DPCC, 1,
, 3,
DPLB, 1,
Offset (0xD2),
, 11,
DPLT, 1,
Offset (0xD4)
}

OperationRegion (DS3M, SystemMemory, MMBA (0x04), 0xD4)
Field (DS3M, DWordAcc, NoLock, Preserve)
{
D3VD, 32,
D304, 8,
Offset (0x0C),
D30C, 8,
Offset (0x18),
D318, 8,
D319, 8,
D31A, 8,
Offset (0x1C),
D31C, 16,
Offset (0x20),
D320, 32,
D324, 32,
D328, 32,
D32C, 32,
Offset (0xC9),
D3ET, 1,
Offset (0xD0),
D3AS, 2,
Offset (0xD4)
}

OperationRegion (DS4M, SystemMemory, MMBA (0x05), 0x0568)
Field (DS4M, DWordAcc, NoLock, Preserve)
{
D4VD, 32,
D404, 8,
Offset (0x0C),
D40C, 8,
Offset (0x18),
D418, 8,
D419, 8,
D41A, 8,
Offset (0x1C),
D41C, 16,
Offset (0x20),
D420, 32,
D424, 32,
D428, 32,
D42C, 32,
Offset (0xC9),
D4ET, 1,
Offset (0xD0),
D4AS, 2,
, 3,
D4RL, 1,
D4CC, 1,
, 3,
D4LB, 1,
Offset (0x564),
DVES, 32
}

OperationRegion (DS5M, SystemMemory, MMBA (0x06), 0xD4)
Field (DS5M, DWordAcc, NoLock, Preserve)
{
D5VD, 32,
D504, 8,
Offset (0x0C),
D50C, 8,
Offset (0x18),
D518, 8,
D519, 8,
D51A, 8,
Offset (0x1C),
D51C, 16,
Offset (0x20),
D520, 32,
D524, 32,
D528, 32,
D52C, 32,
Offset (0xC9),
D5ET, 1,
Offset (0xD0),
D5AS, 2,
Offset (0xD4)
}

OperationRegion (NHIM, SystemMemory, MMBA (0x07), 0xD4)
Field (NHIM, DWordAcc, NoLock, Preserve)
{
NH00, 32,
NH04, 8,
Offset (0x0C),
NH0C, 8,
Offset (0x10),
NH10, 32,
NH14, 32,
Offset (0x80),
Offset (0x81),
Offset (0x82),
Offset (0x84),
NHPS, 2,
Offset (0xC9),
NHET, 1,
Offset (0xD0),
NHAS, 2,
, 4,
NHCC, 1,
Offset (0xD1),
NHCP, 1,
Offset (0xD4)
}

OperationRegion (XHCM, SystemMemory, MMBA (0x09), 0xD4)
Field (XHCM, DWordAcc, NoLock, Preserve)
{
XH00, 32,
XH04, 8,
Offset (0x0C),
XH0C, 8,
Offset (0x10),
XH10, 32,
XH14, 32,
Offset (0x80),
Offset (0x81),
Offset (0x82),
Offset (0x84),
XHPS, 2,
Offset (0xC9),
XHET, 1,
Offset (0xD0),
XHAS, 2,
, 4,
XHCC, 1,
Offset (0xD1),
XHCP, 1,
Offset (0xD4)
}
And new MMBA (0x09) for XHC2 configuration
Local0 = \_SB.PCI0.GPCB ()
Local1 = ((\_SB.PCI0.GPCB () + ((\_SB.PCI0.RP05._ADR & 0x00FF0000) >> One)) +
((\_SB.PCI0.RP05._ADR & 0xFF) << 0x0C))
OperationRegion (MMMM, SystemMemory, Local1, 0x24)
Field (MMMM, DWordAcc, NoLock, Preserve)
{
Offset (0x19),
SB19, 8,
SB1A, 8,
Offset (0x20),
SB20, 32
}
...

Case (0x09)
{
Local2 = (Local0 + ((((((SB1A - SB19) -
0x02) >> One) + SB19) + 0x02) << 0x14))
}
The following method modifications allow Thunderbolt device model detection for using related CRMW data (AR different from TR). Like that, we can have a standard file for all thunderbolt 3 devices ;)
Method (UPCK, 0, Serialized)
{
If ((UPVD == 0x15788086))
{
TBID = One
Return (One)
}
ElseIf ((UPVD == 0x15C08086))
{
TBID = 0x02
Return (One)
}
ElseIf ((UPVD == 0x15D38086))
{
TBID = 0x03
Return (One)
}
ElseIf ((UPVD == 0x15EA8086))
{
TBID = 0x04
Return (One)
}
Else
{
Return (Zero)
}
}

...
If ((LWRT >= LPMN))
{
LRRT += One
DBG1 ("UPSB PCED - Retrying link. POC Reset NEEDED")
}

If ((Local4 != Zero))
{
LRRT += One
If ((TBID == 0x04))
{
\_SB.PCI0.RP05.UPSB.CRMW (0x0771, Zero, 0x02, 0x0200, 0xFFFFFFFF)
}
}
...
Method (_PS0, 0, Serialized) // _PS0: Power State 0
{
DBG1 ("UPSB _PS0")
PCED ()
If ((TBID <= 0x03))
{
\_SB.PCI0.RP05.UPSB.CRMW (0x013E, Zero, 0x02, 0x0200, 0x0200)
\_SB.PCI0.RP05.UPSB.CRMW (0x023E, Zero, 0x02, 0x0200, 0x0200)
}
ElseIf ((TBID == 0x04))
{
\_SB.PCI0.RP05.UPSB.CRMW (0x0150, Zero, 0x02, 0x04000000, 0x04000000)
\_SB.PCI0.RP05.UPSB.CRMW (0x0250, Zero, 0x02, 0x04000000, 0x04000000)
}
}
 
Last edited:
CaseySJ said:
Reply posted!
Click to expand...

Thank you for your posting.
I tested it, but Graphics doesn't work correctly.

Graphics/Displays Kernel Extension Info: No Kext Loaded.

How can I solve it?
 
jiny505 said:
Thank you for your posting.
I tested it, but Graphics doesn't work correctly.

Graphics/Displays Kernel Extension Info: No Kext Loaded.

How can I solve it?
Click to expand...
I’ll reply in about 2 hours. Lifting weights at the gym right now. :)
 
Elias64Fr said:
@CaseySJ , GREAT !

I haven't tried any TBT1 devices (don't have) but it's a good news that it's now detected.

About Link speed, the only property which could change 20Gbps x2 to 40Gbps 1x is linkDetailsb ... but its might be normal when self detecting speed link (to verify it you should boot without any device connected)

About ASPM, I dont know if it is required to change current value but if we want to be closest as possible off all rMacs, I have found new methodology to configure different parameters (Cache Line Size for Legacy devices, ASPM, Extended Tag, ClockPM and Common Clk) of each devices by adding some news data on CNHI method (currently renamed as CONF () ).
I have also modified MMBA method to have a standard final SSDT file.
Method (CONF, 0, Serialized)
{
DBG1 ("Configure Thunderbolt ...")
Local0 = 0x0A
While (Local0)
{
RP0C = 0x40 / Cache Line Size stetted to 256 bytes
RP20 = R020
RP24 = R024
RP28 = R028
RP2C = R02C
RPRL = One / Retrain Link (probably not required!)
RPAS = Zero / ASPM configuration, set to Zero (disabled)
RPCC = One / Common Clock enabled
RPLB = Zero /Link Bandwidth Management Interrupt Enable
RPPD = Zero / Device Power state (Probably not required! but) setted to D0 (active state)
RPNR = One / No Soft Reset (PM for transition from D3 to D0, depending on initial state of LSPCI results)
RP04 = 0x07
If ((R020 == RP20))
{
Break
}

Sleep (One)
Local0--
}

If ((R020 != RP20))
{
DBG1 ("Configure Root Port failed!")
Return (Zero)
}
Else
{
DBG1 ("Configure Root Port done")
}

Local0 = 0x0A
While (Local0)
{
UP0C = 0x40
UP18 = R118 /* \_SB_.PCI0.RP05.R118 */
UP19 = R119 /* \_SB_.PCI0.RP05.R119 */
UP1A = R11A /* \_SB_.PCI0.RP05.R11A */
UP1C = R11C /* \_SB_.PCI0.RP05.R11C */
UP20 = R120 /* \_SB_.PCI0.RP05.R120 */
UP24 = R124 /* \_SB_.PCI0.RP05.R124 */
UP28 = R128 /* \_SB_.PCI0.RP05.R128 */
UP2C = R12C /* \_SB_.PCI0.RP05.R12C */
UPET = One / Extended tag (Probably not required but different from rMacs)
UPAS = Zero
UPCC = One
UPCP = Zero
UP04 = 0x07
If ((R119 == UP19))
{
Break
}

Sleep (One)
Local0--
}

If ((R119 != UP19))
{
DBG1 ("Configure UpStreamBridge failed!")
Return (Zero)
}
Else
{
DBG1 ("Configure UpStreamBridge done")
}

If ((WTLT () == One)){}
Else
{
Return (Zero)
}

Local0 = 0x0A
While (Local0)
{
DP0C = 0x40
DP18 = R218 /* \_SB_.PCI0.RP05.R218 */
DP19 = R219 /* \_SB_.PCI0.RP05.R219 */
DP1A = R21A /* \_SB_.PCI0.RP05.R21A */
DP1C = R21C /* \_SB_.PCI0.RP05.R21C */
DP20 = R220 /* \_SB_.PCI0.RP05.R220 */
DP24 = R224 /* \_SB_.PCI0.RP05.R224 */
DP28 = R228 /* \_SB_.PCI0.RP05.R228 */
DP2C = R22C /* \_SB_.PCI0.RP05.R22C */
DPET = One
DPRL = One
DPAS = Zero
DPCC = One
DPLB = Zero
DP04 = 0x07
DBG1 ("Configure DownStreamBridge0 done")
D30C = 0x40
D318 = R318 /* \_SB_.PCI0.RP05.R318 */
D319 = R319 /* \_SB_.PCI0.RP05.R319 */
D31A = R31A /* \_SB_.PCI0.RP05.R31A */
D31C = R31C /* \_SB_.PCI0.RP05.R31C */
D320 = R320 /* \_SB_.PCI0.RP05.R320 */
D324 = R324 /* \_SB_.PCI0.RP05.R324 */
D328 = R328 /* \_SB_.PCI0.RP05.R328 */
D32C = R32C /* \_SB_.PCI0.RP05.R32C */
D3ET = One
D3AS = Zero
D304 = 0x07
DBG1 ("Configure DownStreamBridge1 done")
D40C = 0x40
D418 = R418 /* \_SB_.PCI0.RP05.R418 */
D419 = R419 /* \_SB_.PCI0.RP05.R419 */
D41A = R41A /* \_SB_.PCI0.RP05.R41A */
D41C = R41C /* \_SB_.PCI0.RP05.R41C */
D420 = R420 /* \_SB_.PCI0.RP05.R420 */
D424 = R424 /* \_SB_.PCI0.RP05.R424 */
D428 = R428 /* \_SB_.PCI0.RP05.R428 */
D42C = R42C /* \_SB_.PCI0.RP05.R42C */
D4ET = One
D4RL = One
D4AS = Zero
D4CC = One
D4LB = Zero
DVES = RVES /* \_SB_.PCI0.RP05.RVES */
D404 = 0x07
DBG1 ("Configure DownStreamBridge2 done")
D50C = 0x40
D518 = R518 /* \_SB_.PCI0.RP05.R518 */
D519 = R519 /* \_SB_.PCI0.RP05.R519 */
D51A = R51A /* \_SB_.PCI0.RP05.R51A */
D51C = R51C /* \_SB_.PCI0.RP05.R51C */
D520 = R520 /* \_SB_.PCI0.RP05.R520 */
D524 = R524 /* \_SB_.PCI0.RP05.R524 */
D528 = R528 /* \_SB_.PCI0.RP05.R528 */
D52C = R52C /* \_SB_.PCI0.RP05.R52C */
D5ET = One
D5AS = Zero
D504 = 0x07
DBG1 ("Configure DownStreamBridge4 done")
If ((R219 == DP19))
{
Break
}

Sleep (One)
Local0--
}

If ((R219 != DP19))
{
DBG1 ("Configure DownStreamBridges failed!")
Return (Zero)
}

If ((WTDL () == One))
{
DBG1 ("Configure DownStreamBridges done")
}
Else
{
Return (Zero)
}

Local0 = 0x64
While (Local0)
{
NH0C = 0x40
NH10 = RH10 /* \_SB_.PCI0.RP05.RH10 */
NH14 = RH14 /* \_SB_.PCI0.RP05.RH14 */
NHET = One
NHAS = Zero
NHCC = One
NHCP = Zero
NHPS = Zero
NH04 = 0x07
If ((RH10 == NH10))
{
Break
}
Else
{
}

Sleep (One)
Local0--
}

If ((RH10 != NH10))
{
DBG1 ("Configure NHI0 failed!")
Return (Zero)
}

If ((WTDL () == One))
{
DBG1 ("Configure NHI0 done")
}
Else
{
Return (Zero)
}

Local0 = 0x64
While (Local0)
{
XH0C = 0x40
XHET = One
XHAS = Zero
XHCC = One
XHCP = Zero
XHPS = Zero
XH04 = 0x07
If ((XH0C == 0x40))
{
Break
}
Else
{
}

Sleep (One)
Local0--
}

If ((XH0C != 0x40))
{
DBG1 ("Configure XHC2 failed!")
Return (Zero)
}

If ((WTDL () == One))
{
DBG1 ("Configure XHC2 done")
}
Else
{
Return (Zero)
}

DBG1 ("Configure Thunderbolt finished")
Return (One)
}
OperationRegion (RPSM, SystemMemory, MMBA (One), 0xA8)
Field (RPSM, DWordAcc, NoLock, Preserve)
{
RPVD, 32,
RP04, 8,
Offset (0x0C),
RP0C, 8,
Offset (0x18),
RP18, 8,
RP19, 8,
RP1A, 8,
Offset (0x1C),
RP1C, 16,
Offset (0x20),
RP20, 32,
RP24, 32,
RP28, 32,
RP2C, 32,
Offset (0x3E),
, 6,
RRST, 1,
Offset (0x50),
RPAS, 2,
, 3,
RPRL, 1,
RPCC, 1,
, 3,
RPLB, 1,
Offset (0x52),
, 11,
RPLT, 1,
Offset (0x58),
, 3,
RPPD, 1,
Offset (0xA0),
Offset (0xA1),
Offset (0xA2),
Offset (0xA4),
, 3,
RPNR, 1,
Offset (0xA8)
}

OperationRegion (RPSB, SystemMemory, MMBA (One), 0x5C)
Field (RPSB, DWordAcc, NoLock, Preserve)
{
Offset (0x18),
RB18, 32,
Offset (0x44),
RB44, 32,
RB48, 16,
RB4A, 16,
RB4C, 32,
RB50, 16,
RB52, 16,
RB54, 32,
RB58, 16,
RB5A, 16
}

OperationRegion (UPSM, SystemMemory, MMBA (0x02), 0x0550)
Field (UPSM, DWordAcc, NoLock, Preserve)
{
UPVD, 32,
UP04, 8,
Offset (0x08),
CLRD, 32,
UP0C, 8,
Offset (0x18),
UP18, 8,
UP19, 8,
UP1A, 8,
Offset (0x1C),
UP1C, 16,
Offset (0x20),
UP20, 32,
UP24, 32,
UP28, 32,
UP2C, 32,
Offset (0xC9),
UPET, 1,
Offset (0xD0),
UPAS, 2,
, 4,
UPCC, 1,
Offset (0xD1),
UPCP, 1,
Offset (0xD2),
, 11,
UPLT, 1,
Offset (0xD4),
Offset (0x544),
UPMB, 1,
Offset (0x548),
T2PR, 32,
P2TR, 32
}

OperationRegion (DNSM, SystemMemory, MMBA (0x03), 0xD4)
Field (DNSM, DWordAcc, NoLock, Preserve)
{
DPVD, 32,
DP04, 8,
Offset (0x0C),
DP0C, 8,
Offset (0x18),
DP18, 8,
DP19, 8,
DP1A, 8,
Offset (0x1C),
DP1C, 16,
Offset (0x20),
DP20, 32,
DP24, 32,
DP28, 32,
DP2C, 32,
Offset (0xC9),
DPET, 1,
Offset (0xD0),
DPAS, 2,
, 3,
DPRL, 1,
DPCC, 1,
, 3,
DPLB, 1,
Offset (0xD2),
, 11,
DPLT, 1,
Offset (0xD4)
}

OperationRegion (DS3M, SystemMemory, MMBA (0x04), 0xD4)
Field (DS3M, DWordAcc, NoLock, Preserve)
{
D3VD, 32,
D304, 8,
Offset (0x0C),
D30C, 8,
Offset (0x18),
D318, 8,
D319, 8,
D31A, 8,
Offset (0x1C),
D31C, 16,
Offset (0x20),
D320, 32,
D324, 32,
D328, 32,
D32C, 32,
Offset (0xC9),
D3ET, 1,
Offset (0xD0),
D3AS, 2,
Offset (0xD4)
}

OperationRegion (DS4M, SystemMemory, MMBA (0x05), 0x0568)
Field (DS4M, DWordAcc, NoLock, Preserve)
{
D4VD, 32,
D404, 8,
Offset (0x0C),
D40C, 8,
Offset (0x18),
D418, 8,
D419, 8,
D41A, 8,
Offset (0x1C),
D41C, 16,
Offset (0x20),
D420, 32,
D424, 32,
D428, 32,
D42C, 32,
Offset (0xC9),
D4ET, 1,
Offset (0xD0),
D4AS, 2,
, 3,
D4RL, 1,
D4CC, 1,
, 3,
D4LB, 1,
Offset (0x564),
DVES, 32
}

OperationRegion (DS5M, SystemMemory, MMBA (0x06), 0xD4)
Field (DS5M, DWordAcc, NoLock, Preserve)
{
D5VD, 32,
D504, 8,
Offset (0x0C),
D50C, 8,
Offset (0x18),
D518, 8,
D519, 8,
D51A, 8,
Offset (0x1C),
D51C, 16,
Offset (0x20),
D520, 32,
D524, 32,
D528, 32,
D52C, 32,
Offset (0xC9),
D5ET, 1,
Offset (0xD0),
D5AS, 2,
Offset (0xD4)
}

OperationRegion (NHIM, SystemMemory, MMBA (0x07), 0xD4)
Field (NHIM, DWordAcc, NoLock, Preserve)
{
NH00, 32,
NH04, 8,
Offset (0x0C),
NH0C, 8,
Offset (0x10),
NH10, 32,
NH14, 32,
Offset (0x80),
Offset (0x81),
Offset (0x82),
Offset (0x84),
NHPS, 2,
Offset (0xC9),
NHET, 1,
Offset (0xD0),
NHAS, 2,
, 4,
NHCC, 1,
Offset (0xD1),
NHCP, 1,
Offset (0xD4)
}

OperationRegion (XHCM, SystemMemory, MMBA (0x09), 0xD4)
Field (XHCM, DWordAcc, NoLock, Preserve)
{
XH00, 32,
XH04, 8,
Offset (0x0C),
XH0C, 8,
Offset (0x10),
XH10, 32,
XH14, 32,
Offset (0x80),
Offset (0x81),
Offset (0x82),
Offset (0x84),
XHPS, 2,
Offset (0xC9),
XHET, 1,
Offset (0xD0),
XHAS, 2,
, 4,
XHCC, 1,
Offset (0xD1),
XHCP, 1,
Offset (0xD4)
}
And new MMBA (0x09) for XHC2 configuration
Local0 = \_SB.PCI0.GPCB ()
Local1 = ((\_SB.PCI0.GPCB () + ((\_SB.PCI0.RP05._ADR & 0x00FF0000) >> One)) +
((\_SB.PCI0.RP05._ADR & 0xFF) << 0x0C))
OperationRegion (MMMM, SystemMemory, Local1, 0x24)
Field (MMMM, DWordAcc, NoLock, Preserve)
{
Offset (0x19),
SB19, 8,
SB1A, 8,
Offset (0x20),
SB20, 32
}
...

Case (0x09)
{
Local2 = (Local0 + ((((((SB1A - SB19) -
0x02) >> One) + SB19) + 0x02) << 0x14))
}
The following method modifications allow Thunderbolt device model detection for using related CRMW data (AR different from TR). Like that, we can have a standard file for all thunderbolt 3 devices ;)
Method (UPCK, 0, Serialized)
{
If ((UPVD == 0x15788086))
{
TBID = One
Return (One)
}
ElseIf ((UPVD == 0x15C08086))
{
TBID = 0x02
Return (One)
}
ElseIf ((UPVD == 0x15D38086))
{
TBID = 0x03
Return (One)
}
ElseIf ((UPVD == 0x15EA8086))
{
TBID = 0x04
Return (One)
}
Else
{
Return (Zero)
}
}

...
If ((LWRT >= LPMN))
{
LRRT += One
DBG1 ("UPSB PCED - Retrying link. POC Reset NEEDED")
}

If ((Local4 != Zero))
{
LRRT += One
If ((TBID == 0x04))
{
\_SB.PCI0.RP05.UPSB.CRMW (0x0771, Zero, 0x02, 0x0200, 0xFFFFFFFF)
}
}
...
Method (_PS0, 0, Serialized) // _PS0: Power State 0
{
DBG1 ("UPSB _PS0")
PCED ()
If ((TBID <= 0x03))
{
\_SB.PCI0.RP05.UPSB.CRMW (0x013E, Zero, 0x02, 0x0200, 0x0200)
\_SB.PCI0.RP05.UPSB.CRMW (0x023E, Zero, 0x02, 0x0200, 0x0200)
}
ElseIf ((TBID == 0x04))
{
\_SB.PCI0.RP05.UPSB.CRMW (0x0150, Zero, 0x02, 0x04000000, 0x04000000)
\_SB.PCI0.RP05.UPSB.CRMW (0x0250, Zero, 0x02, 0x04000000, 0x04000000)
}
}
Click to expand...
WOW!!! This is brilliant...

Will incorporate all of these changes this evening and try the following devices:
  1. Apple Thunderbolt Gigabit Ethernet with Apple TB3-to-TB2 adapter
  2. PowerColor Gaming Station X eGPU with Radeon RX 580 installed inside
  3. Belkin Thunderbolt 3 Dock Pro
Last night only item 1 generated a device tree under DSB1/DSB4.

Regarding TBID, I'll add this: Name (TBID, 0x04).
Regarding LPMN (in UPSB.PCED), where is this defined?
 
Last edited:
CaseySJ said:
Ah, it specifically says not compatible with 30-inch Apple Cinema Display!
Click to expand...
yes! i have the 20-inch monitors but I think it's the same. However I'm going to buy 2 new monitor hdmi and I think also 2 new usb-c to hdmi adapters no (or maybe to DP port)... any advice for the adapters?
 
Vorshim92 said:
yes! i have the 20-inch monitors but I think it's the same. However I'm going to buy 2 new monitor hdmi and I think also 2 new usb-c to hdmi adapters no (or maybe to DP port)... any advice for the adapters?
Click to expand...
If you are going to buy new monitors (which is a good idea), please buy something that has both HDMI 1.4+ and DisplayPort 1.2+ connectors. I would recommend USB-C to DisplayPort cables only -- such as this one.

If you're buying 4K monitors, they should support HDMI 2.0+ and DisplayPort 1.2+.
 
I've successfully updated the BIOS to F9b and native NVRAM few days ago.
I can't say if it was right after that, but the EFIClone-v4.sh script has stopped working for me. I noticed the destination EFI partition mounted and not the boot one so I stopped the backup in CCC. I've reinstalled the script, leaving it in test mode and let run to see what's going on.

From the attached log looks like the boot partition is not recognised and then I can see all files from my boot drive listed.
What could have happened and how could I fix this? At the moment backing up the EFI folder manually but would be great to have it back in automatic mode!
 

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