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[SUCCESS] Gigabyte Designare Z390 (Thunderbolt 3) + i7-9700K + AMD RX 580
- Thread starter CaseySJ
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-
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- gigabyte thunderbolt 3
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For some reason my UAD stuff hotswaps fine on this build. In fact, it is the first time ever that I’m able to do so. I’m on Catalina.
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Hi @CaseySJ, I'm back and happy to continue this adventure
Nice ! With theses informations, we should have this following code under RHUB :
Code:
Device (RHUB)
{
Name (_ADR, Zero) // _ADR: Address
Device (SSP1)
{
Name (_ADR, 0x03) // _ADR: Address
Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
{
0xFF,
0x09,
Zero,
Zero
})
Name (_PLD, Package (0x01) // _PLD: Physical Location of Device
{
ToPLD (
PLD_Revision = 0x1,
PLD_IgnoreColor = 0x1,
PLD_Red = 0x0,
PLD_Green = 0x0,
PLD_Blue = 0x0,
PLD_Width = 0x0,
PLD_Height = 0x0,
PLD_UserVisible = 0x1,
PLD_Dock = 0x0,
PLD_Lid = 0x0,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "UPPER",
PLD_HorizontalPosition = "LEFT",
PLD_Shape = "UNKNOWN",
PLD_GroupOrientation = 0x0,
PLD_GroupToken = 0x0,
PLD_GroupPosition = 0x0,
PLD_Bay = 0x0,
PLD_Ejectable = 0x0,
PLD_EjectRequired = 0x0,
PLD_CabinetNumber = 0x0,
PLD_CardCageNumber = 0x0,
PLD_Reference = 0x0,
PLD_Rotation = 0x0,
PLD_Order = 0x0,
PLD_VerticalOffset = 0x0,
PLD_HorizontalOffset = 0x0)
})
Name (FS, Package (0x02)
{
"XHC",
0x08
})
Name (LS, Package (0x02)
{
"XHC",
0x08
})
Name (HS, Package (0x02)
{
"XHC",
0x08
})
Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
{
Local0 = Package (0x06)
{
"kUSBWakePortCurrentLimit",
0x0BB8,
"kUSBSleepPortCurrentLimit",
0x0BB8,
"UsbCompanionPortPresent",
One
}
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}
}
Device (SSP2)
{
Name (_ADR, 0x04) // _ADR: Address
Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
{
0xFF,
0x09,
Zero,
Zero
})
Name (_PLD, Package (0x01) // _PLD: Physical Location of Device
{
ToPLD (
PLD_Revision = 0x1,
PLD_IgnoreColor = 0x1,
PLD_Red = 0x0,
PLD_Green = 0x0,
PLD_Blue = 0x0,
PLD_Width = 0x0,
PLD_Height = 0x0,
PLD_UserVisible = 0x1,
PLD_Dock = 0x0,
PLD_Lid = 0x0,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "UPPER",
PLD_HorizontalPosition = "LEFT",
PLD_Shape = "UNKNOWN",
PLD_GroupOrientation = 0x0,
PLD_GroupToken = 0x0,
PLD_GroupPosition = 0x0,
PLD_Bay = 0x0,
PLD_Ejectable = 0x0,
PLD_EjectRequired = 0x0,
PLD_CabinetNumber = 0x0,
PLD_CardCageNumber = 0x0,
PLD_Reference = 0x0,
PLD_Rotation = 0x0,
PLD_Order = 0x0,
PLD_VerticalOffset = 0x0,
PLD_HorizontalOffset = 0x0)
})
Name (FS, Package (0x02)
{
"XHC",
0x0D
})
Name (LS, Package (0x02)
{
"XHC",
0x0D
})
Name (HS, Package (0x02)
{
"XHC",
0x0D
})
Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
{
Local0 = Package (0x06)
{
"kUSBWakePortCurrentLimit",
0x0BB8,
"kUSBSleepPortCurrentLimit",
0x0BB8,
"UsbCompanionPortPresent",
One
}
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}
}
}To be sure ! when you say on pics "UPPER", this is not from your motherboard back side pics ? Because upper on this pics, is the USB Type A in red ! We should test only USB-C connectors !
CaseySJ
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Hello @Elias64Fr. Hope you had a good weekend! I certainly enjoyed mine.Hi @CaseySJ, I'm back and happy to continue this adventure
I had reached the same conclusion and was about to post this...
I've made these changes and will test them later this evening!
Correct -- only the USB-C connectors. Because my system is oriented vertically, the two Thunderbolt ports are not side-by-side, but one atop the other.
Additional Observations:
I received a complete set of real iMac 19,1 ACPI tables from a family member, and have been comparing our version with Apple's original.
Interesting: This is why Device ID 0x15EA is okay for UPSB!
CTBT method uses different technique for powering on the TB3 controller. Whereas Apple's version (on left side) seems to power on TBT and USB separately using two fields/methods, we seem to have only one field/method.
Not sure if TGPE and UTLK are needed...
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I have updated the firmware on the EVO 970 Plus to the latest firmware as per @CaseySJ 's instruction and that seems to have enabled the progress bar under the Apple logo to go slightly further this time (one third of the way before it gets stuck).
I've updated the bios parameters as per Post #01 with the exception of choosing slot 01 for the graphics card whilst it is actually installed in slots 6-7.
I've also noticed a few times that after either switching the machine ON or rebooting the system, it switches itself off and back on again a couple of times before showing the motherboard screen.
I'm not sure what causes Catalina installation to get stuck or if it has anything to do with the sudden resetting that I've explained above.
Any advice would be much appreciated.
I've updated the bios parameters as per Post #01 with the exception of choosing slot 01 for the graphics card whilst it is actually installed in slots 6-7.
I've also noticed a few times that after either switching the machine ON or rebooting the system, it switches itself off and back on again a couple of times before showing the motherboard screen.
I'm not sure what causes Catalina installation to get stuck or if it has anything to do with the sudden resetting that I've explained above.
Any advice would be much appreciated.
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Hi
Without the graphic card?
Clear CMOS?
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Native NVRAM also working on Gigabyte Z390 Aorus Pro firmware F12d using the same CFG Lock parameter 0x5C1 
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Comments/Questions :
- ThunderboltConfig
- If you see the screenshots of successful TNODE/TBUS activations, you'll find that they all use a ThunderboltConfig setting that was taken from an older MacBook Pro (w/Titan Ridge), namely:
- 0002FFFF 04000301 01000400 05010200 03000301 01000000 03010200 02000100
- All attempts to change this to a newer setting from iMac19,1 (below) failed to activate TNODE/TBUS.
- 00021C00 02000503 01000400 05030200 03000503 01000000 03030200 01000200
- Additionally, all TNODE/TBUS activations were done with Draft07.
- Questions:
- Do we know how to interpret these bytes?
- TLN/TB seems to be dependent in part on this.
- If you see the screenshots of successful TNODE/TBUS activations, you'll find that they all use a ThunderboltConfig setting that was taken from an older MacBook Pro (w/Titan Ridge), namely:
Titan Ridge with similar values seem to be MBP15,1 with two controllers and "ThunderboltConfig" parameters are the following (with bolded diff):
Controller1:
<00 02 ff ff 02 00 05 03 01 00 04 00 05 03 02 00 03 00 05 03 01 00 00 00 03 03 02 00 02 00 01 00>
Controller2:
<01 02 ff ff 02 00 05 03 01 00 04 00 05 03 02 00 03 00 05 03 01 00 01 00 03 03 02 00 04 00 03 00>
Two first bolded seem to be the controller number and last two, the port number.
Another Titan Ridge with similar values is iMac19,1 with one controller and ThunderboltConfig is the following (with bolded diff):
Controller1:
<00 02 1c 00 02 00 05 03 01 00 04 00 05 03 02 00 03 00 05 03 01 00 00 00 03 03 02 00 01 00 02 00>
We can see that the last port number are inverted from MBP15,1, like your ThunderboltConfig ! It will be interesting to test with MBP15,1 first controller parameter (closest to TR config than yours).
About all Thunderbolt parameters, I had tested with/without, this is the first following results :
- All parameters aren't required to have full thunderbolt tree.
- Without LinkDetails, thunderbolt speed that appear on System informations/Thunderbolt displays "up to 20Gb/s x2" instead of "up to 40Gb/s x1", don't know if it's only a visual information or if that really limit bus speed ! I should test with EGPU if performances decrease without this parameter. Under IOThunderboltport@1 to @4, this parameter change value of "Supported Link Width" from 0x1 to 0x3.
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About first picture :
We don't have correct Bus speed (0Gb/s instead of 40Gb/s), "Current Link Width" is empty AND another missed line in French text :
"Version du programme interne du contrôleur de liaison : 0.16.0" for Asus Maximus IX
with IOReg value appearing on "IOThunderboltPort@x / Micro Version" property
Could you send me IOReg properties screen-shot of each part of IOThunderboltSwitchType3 except DPIN and DPOUT (without port@5, @6, @A and @B) ?
Attachments
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