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iMac Pro X299 - Live the Future now with macOS 10.14 Mojave [Successful Build/Extended Guide]

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nmano said:
I try like this
Code: 
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180427 (64-bit version)(RM)
* Copyright (c) 2000 - 2018 Intel Corporation
*
* Disassembling to non-symbolic legacy ASL operators
*
* Disassembly of iASLCWVu49.aml, Fri Feb 15 20:15:32 2019
*
* Original Table Header:
*     Signature        "SSDT"
*     Length           0x0000025D (605)
*     Revision         0x01
*     Checksum         0xE1
*     OEM ID           "KGP"
*     OEM Table ID     "X299SL01"
*     OEM Revision     0x00000000 (0)
*     Compiler ID      "INTL"
*     Compiler Version 0x20180427 (538444839)
*/
DefinitionBlock ("", "SSDT", 1, "KGP", "X299SL01", 0x00000000)
{
    External (_SB_.PC01.BR1A, DeviceObj)    // (from opcode)
    External (_SB_.PC01.BR1A.PEGP, DeviceObj)    // (from opcode)
    External (_SB_.PC01.BR1A.SL01, DeviceObj)    // (from opcode)
    External (DTGP, MethodObj)    // 5 Arguments (from opcode)

    Scope (\_SB.PC01.BR1A)
    {
        Scope (SL01)
        {
            Name (_STA, Zero)  // _STA: Status
        }

        Scope (PEGP)
        {
            Device (EGP5)
            {
                Name (_ADR, 0x00080000)  // _ADR: Address
                Device (XHC2)
                {
                    Name (_ADR, Zero)  // _ADR: Address
                    Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                    {
                        If (LEqual (Arg2, Zero))
                        {
                            Return (Buffer (One)
                            {
                                 0x03                                       
                            })
                        }

                        Store (Package ()
                            {
                                "AAPL,slot-name",
                                Buffer ()
                                {
                                    "Slot-5"
                                },

                                "built-in",
                                Buffer ()
                                {
                                     0x00                                       
                                },

                                "name",
                                Buffer ()
                                {
                                    "Intel XHC Controller"
                                },

                                "model",
                                Buffer ()
                                {
                                    "USB xHC Host Controller"
                                },

                                "device_type",
                                Buffer ()
                                {
                                    "USB eXtensible Host Controller"
                                },

                          

                                "device-id",
                                Buffer ()
                                {
                                     0x42, 0x11, 0x00, 0x00                     
                                },

                                "subsystem-id",
                                Buffer ()
                                {
                                     0x42, 0x11, 0x00, 0x00                     
                                },

                                "subsystem-vendor-id",
                                Buffer ()
                                {
                                     0x21, 0x1B, 0x00, 0x00                     
                                }

                            
                            }, Local0)
                        DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                        Return (Local0)
                    }
                }
            }
        }
    }
}
Click to expand...

But if you use both firewire and USB controllers, you cannot implement separate SSDTs for each controller as both share SL01 on two different bridges.

After nulling SL01, both bridges and their children must be redefined in the same SSDT. Thus the SSDT must contain both EGP3 and EGP5 device definitions. That's why SSDT-X299-SL01-FRWR-XHC2.aml and not SSDT-X299-SL01-FRWR.aml and SSDT-X299-SL01-XHC2.aml.

Just check if "fwhub" definition in DSM of EGP3 and "reg-ltrovr"and "AAPL" definitions of EGP5 are really adequate. There is nothing else in SSDT-X299-SL01-FRWR-XHC2.aml that could prevent sleep/wake.

You did not answer if system sleep/wake works after removing firewire and USB controllers and SSDT-X299-SL01-FRWR-XHC2.aml, or if firewire and USB controllers are implemented but SSDT-X299-SL01-FRWR-XHC2.aml is removed.

Well.. I will be now on my way to Frankfurt.

Good luck,

KGP
 
Last edited:
kgp said:
But if you use both firewire and USB controllers, you cannot implement separate SSDTs for each controller as both share SL01 on two different bridges.

After nulling SL01, both bridges and their children must be redefined in the same SSDT. Thus the SSDT must contain both EGP3 and EGP5 device definitions. That's why SSDT-X299-SL01-FRWR-XHC2.aml and not SSDT-X299-SL01-FRWR.aml and SSDT-X299-SL01-XHC2.aml.

Just check if "fwhub" definition in DSM of EGP3 and "reg-ltrovr"and "AAPL" definitions of EGP5 are really adequate. There is nothing else in SSDT-X299-SL01-FRWR-XHC2.aml that could prevent sleep/wake.

You did not answer if system sleep/wake works after removing firewire and USB controllers and SSDT-X299-SL01-FRWR-XHC2.aml, or if firewire and USB controllers are implemented but SSDT-X299-SL01-FRWR-XHC2.aml is removed.

Well.. I will be now on my way to Frankfurt.

Good luck,

KGP
Click to expand...
Hi KGP
I am work at the moment back to home I will check.
Happy Holiday.:)
I removed FRWR-card and I have USB card in there.
 
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nmano said:
Hi KGP
I am work at the moment back to home I will check.
Happy Holiday.:)
I removed FRWR-card and I have USB card in there.
Click to expand...

And sleep/wake works such? If not, also remove USB card and entire SSDT-X299-SL01-FRWR-XHC2.aml for testing purposes.

Good luck,

KGP
 
@nmano, something else comes to my mind. I do not remember which Vega64 GPU you are exactly using. Please verify that with the current SL05 SSDT-implementation, all DP and HDMI ports of your VEGA are poperly implemented and fully work as expected, including display hotplug and multi-monitor support. If the latter is not the case, we would have to modify the SL05-SSDT by Tuesday, as else also sleep/wake will never work such.

Not all Vegas are compatible with my custom Vega64 SSDT inplementation, e.g Frontier and some other reference Vega64 GPUs might require a PCI implementation similar to the one considered in SSDT-X299-Frontier.aml instead.
 
@ izo1: Thanks for posting the AQC111 factory firmware at
https://www.tonymacx86.com/threads/...sful-build-extended-guide.255082/post-1909271
Some users were successful in re-flashing (& unbricking) their AQC111 firmware:
www.station-drivers.com

Aquantia AQC107, AQC108, Firmware Version 3.1.56

Aquantia AQC107, AQC108 Firmware Version 3.1.56 Nouveau firmware pour les chipsets réseaux Aquantia AQC107, AQC108 Version 3.1.56 AVANT APRES Release...
www.station-drivers.com www.station-drivers.com
Quote: "I still don't understand why ASUS would not put a 10GbE port instead on a $500 motherboard. It costs them pennies for these chips".
That's probably inaccurate, since there's a $100 price difference on the 2018 Mac Mini between the base 1Gbit vs. optional 10Gbit LAN port versions being offered by Apple. If the cost to Apple was truly "pennies", then they'd include the 10Gbit version in all Mac Mini 2018 models.
If anyone has access to either the iMacPro or to the 2018 Mac Mini (with the 10Gbit LAN port), please consider making Aquantia factory firmware backups, and posting them somewhere publicly accessible. The "diag" flash tool is included in the 3.1.56 firmware at https://www.station-drivers.com/ind...topic&catid=19&id=156&Itemid=858&lang=en#1185
Thanks.
 
Last edited:
rugula said:
@ izo1: Thanks for posting the AQC111 factory firmware at
https://www.tonymacx86.com/threads/...sful-build-extended-guide.255082/post-1909271
Quote: "I still don't understand why ASUS would not put a 10GbE port instead on a $500 motherboard. It costs them pennies for these chips".
That's probably inaccurate, since there's a significant price difference on the 2018 Mac Mini between the base 1Gbit vs. optional 10Gbit LAN port versions being offered by Apple. If the cost to Apple was truly "pennies", then they'd include the 10Gbit version in all Mac Mini 2018 models.
If anyone has access to either the iMacPro or to the 2018 Mac Mini (with the 10Gbit LAN port), please consider making Aquantia factory firmware backups, and posting them somewhere publicly accessible. The "diag" flash tool is included in the 3.1.56 firmware at https://www.station-drivers.com/ind...topic&catid=19&id=156&Itemid=858&lang=en#1185
Thanks.
Click to expand...

The 5GB onboard NIC was just one of my reasons not to opt for this motherboard. And it is definitely not the only flaw, ASUS committed when designing the Deluxe II. There are several severe flaws that I outlined from the very beginning along my threads. The 5GB NIC now even turned out to be fully incompatible with macOS, whereas the ASUS Aquantia 10GB PCIe NIC perfectly works with macOS. The more than buggy macOS ASUS TTR firmware implementation on the Deluxe II in line with the missing THB_C header finally also disqualifies the primer justification for its implementation in state-of-art Hackintosh systems.

The combination of ASUS X299 Sage 10GB + GC Titan Ridge PCIe adapter is by far the better and even fully working solution in terms of both 10GB LAN and TTR TB connectivity under macOS.

The seven X16 PCIe slots of the ASUS X299 Sage 10GB moreover make the reduced just threefold X16 PCIe slot inplementation on the Deluxe II appear more redicules than it is already by definition.

Deluxe II, definitely not my decision.
 
Last edited:
kgp said:
@nmano, something else comes to my mind. I do not remember which Vega64 GPU you are exactly using. Please verify that with the current SL05 SSDT-implementation, all DP and HDMI ports of your VEGA are poperly implemented and fully work as expected, including display hotplug and multi-monitor support. If the latter is not the case, we would have to modify the SL05-SSDT by Tuesday, as else also sleep/wake will never work such.

Not all Vegas are compatible with my custom Vega64 SSDT inplementation, e.g Frontier and some other reference Vega64 GPUs might require a PCI implementation similar to the one considered in SSDT-X299-Frontier.aml instead.
Click to expand...
Thanks man I will wait until Tuesday.You're right Its graphics issue.
 
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nmano said:
Thanks man I will wait until Tuesday.You're right Its graphics issue.
Click to expand...

No worries, I know the solution :)

Just wait until I return on Thuesday and we will rock it together :)
 
applemacosxGOD said:
ASUS remove Deluxe II bios 0404 from their website...not sure why....
Click to expand...

Just noticed that also BIOS version 1603 for the original Deluxe board is gone from the website.
 
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