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A Beginner's Guide to Creating a Custom USB SSDT

Joined
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Thank you @UtterDisbelief this finally worked for me after using other guides / SSDT templates / kexts / DSDT fixes / etc. all of them had various drawbacks or bugs or system instabilities but this one is rock solid after a week of testing.:clap:
 
Joined
Jan 9, 2014
Messages
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Motherboard
Gigabyte X99-UD4
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i7-5820K
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RX 580
Hey,

Despite this great guide and all my tries, can't seems to work for me.
I think I might have a problem in the first place:

My config:
  • Mojave 10.14.5 with latest USB patches
  • Gigabyte X99-UD4
  • USB 2 + USB 3 speeds are fine, but I do want to create a custom USB SSDT
Gigabyte x99-UD4 USB ports come in 2 parts:
Code:
Chipset:
    4 x USB 3.0/2.0 ports (2 ports on the back panel, 2 ports available through the internal USB header)
    8 x USB 2.0/1.1 ports (4 ports on the back panel, 4 ports available through the internal USB headers)
Chipset + Renesas® uPD720210 USB 3.0 Hub:
    4 x USB 3.0/2.0 ports on the back panel
The Chipset + Renesas® uPD720210 USB 3.0 Hub, in IOReg, appears very strangely, all the ports comes in a single line: HS09 SS05.
When I plug/unplug devices, it only moves inside the HS09 or SS05 zone, in the AppleUSBHub lines.

Screenshot 2019-06-02 at 15.38.38.png


I really don't know how I should handle those ports? How to include them in the 15 ports? Should I count them for 2 ports (1 USB2 + 1 USB3), as if it's a hub?

Another strange things, in system info, my usb 2 devices appears on a USB 3 hub. But they are plugged in USB 2 ports.

Screenshot 2019-06-02 at 15.39.16.png


Thanks a lot for your feedback about what to do with those ports.
 

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UtterDisbelief

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Hey,

Despite this great guide and all my tries, can't seems to work for me.
I think I might have a problem in the first place:

My config:
  • Mojave 10.14.5 with latest USB patches
  • Gigabyte X99-UD4
  • USB 2 + USB 3 speeds are fine, but I do want to create a custom USB SSDT
Gigabyte x99-UD4 USB ports come in 2 parts:
Code:
Chipset:
    4 x USB 3.0/2.0 ports (2 ports on the back panel, 2 ports available through the internal USB header)
    8 x USB 2.0/1.1 ports (4 ports on the back panel, 4 ports available through the internal USB headers)
Chipset + Renesas® uPD720210 USB 3.0 Hub:
    4 x USB 3.0/2.0 ports on the back panel
The Chipset + Renesas® uPD720210 USB 3.0 Hub, in IOReg, appears very strangely, all the ports comes in a single line: HS09 SS05.
When I plug/unplug devices, it only moves inside the HS09 or SS05 zone, in the AppleUSBHub lines.

View attachment 409420

I really don't know how I should handle those ports? How to include them in the 15 ports? Should I count them for 2 ports (1 USB2 + 1 USB3), as if it's a hub?

Another strange things, in system info, my usb 2 devices appears on a USB 3 hub. But they are plugged in USB 2 ports.

View attachment 409421

Thanks a lot for your feedback about what to do with those ports.
Hi there.

I'll double-check when I'm back at my desk BUT ...

The USB Hubs will probably be the Renesas controlled ports. They are not included in the 15 limit so you do not need to configure them separately.

It is possible you might see a different result in IOReg if you use GenericUSBXHC.Kext as that should affect the Renesas controller. However ensure you back-up if you decide to experiment, otherwise everything looks good :thumbup:

:)
 
Joined
Jan 9, 2014
Messages
49
Motherboard
Gigabyte X99-UD4
CPU
i7-5820K
Graphics
RX 580
Thanks for the quick feedback!

The USB Hubs will probably be the Renesas controlled ports.
Yep that's it, it's HS09 SS05

They are not included in the 15 limit so you do not need to configure them separately.
Does it mean that I should act like they are not here?
Or should I include them in the SSDT?

It is possible you might see a different result in IOReg if you use GenericUSBXHC.Kext
I'll try that ASAP.

:thumbup:
 

UtterDisbelief

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Thanks for the quick feedback!


Yep that's it, it's HS09 SS05


Does it mean that I should act like they are not here?
Or should I include them in the SSDT?


I'll try that ASAP.

:thumbup:
Thanks for the quick feedback!


Yep that's it, it's HS09 SS05


Does it mean that I should act like they are not here?
Or should I include them in the SSDT?


I'll try that ASAP.

:thumbup:
That's correct. You do not need to configure the Renesas ports.

1) The Renesas ports do not count in the 15 limit. This is because the 15-limit only applies to main Intel chipset controlled ports - so in your case the X99. For this older motherboard the EHCI controller is also useful and I see you have renamed it appropriately in your config.plist.

2) As you point out the Renesas chip controls 4 of the back-panel ports. All rest are controlled by the main X99.

3) To double check your controllers when creating an SSDT you should use the 8086_8d31 XHC controller. You can double-check this in System Report. :thumbup: I think, from looking at your IOReg output, that you have already done this. The EHCI controllers are 8086_8d26 (#1) and 8086_8d2d (#2).

Incidentally, because you have the EHC controllers enabled you might want to try the FakePCIID_XHCIMux.kext too (along with FakePCIID.kext) as this puts all the USB2.0 ports on the EHCI part of the tree, freeing up the XHC for more USB3.0 ports. However, again, treat this as "experimental" and back-up everything first!

As you already have your main ports configured as you want them, you might not wish to change this:thumbup:

:)
 
Joined
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Thanks for this intel! NOW I understand a little bit more what's going on.

3) To double check your controllers when creating an SSDT you should use the 8086_8d31 XHC controller.
That was my mistake at my first try. Would never have resolve it alone thanks!

Incidentally, because you have the EHC controllers enabled you might want to try the FakePCIID_XHCIMux.kext too (along with FakePCIID.kext)
Result: no discovery possible in IOREG exept for the EHCI ports.

It is possible you might see a different result in IOReg if you use GenericUSBXHC.Kext
Result: no discovery possible in IOREG for any ports.

The only thing working for me to be able to discover peripherals in IOReg is XHCI-unsupported.kext.

But my Bios config is
Code:
EHCI hand off = ENABLE
XHCI hand off = ENABLE
Hope I'm correct with that.

Last questions about the SSDT file:
  • For USB 3 internal connector, should we name them 3 or 255?
  • For setting the port address, is this correct: <0e 00 00 00> = "port", Buffer() { 0x0e, 0, 0, 0 },?
:thumbup:
 
Joined
Jan 9, 2014
Messages
49
Motherboard
Gigabyte X99-UD4
CPU
i7-5820K
Graphics
RX 580
Incidentally, because you have the EHC controllers enabled you might want to try the FakePCIID_XHCIMux.kext too (along with FakePCIID.kext)
Result: no discovery possible in IOREG exept for the EHCI ports.
Answering myself: Off course no discovery because the HSXX ports are not under XHC anymore with FakePCIID_XHCIMux.kext. Forget it.
 
Joined
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Messages
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Motherboard
Gigabyte X99-UD4
CPU
i7-5820K
Graphics
RX 580
Update:

I successfully created a SSDT_USB.aml, and everything looks good on IOReg.
But I should've did something wrong because it's worst than ever :angel:

> with SSDT_USB.aml + USBInjectAll.kext + XHCI-unsupported.kext + no Patches:

  • All my EHCI ports are disable, meaning my 4 usb3 ports, witch I need.
  • My XHC SS04 USB3 port don't work anymore with USB3 devices (ok with USB2 device). For some reason?
  • So only 1 USB3 port working! haha.
Now I'm pretty lost. But it's always darker before the dawn I hope!
 

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UtterDisbelief

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Update:

I successfully created a SSDT_USB.aml, and everything looks good on IOReg.
But I should've did something wrong because it's worst than ever :angel:

> with SSDT_USB.aml + USBInjectAll.kext + XHCI-unsupported.kext + no Patches:
  • All my EHCI ports are disable, meaning my 4 usb3 ports, witch I need.
  • My XHC SS04 USB3 port don't work anymore with USB3 devices (ok with USB2 device). For some reason?
  • So only 1 USB3 port working! haha.
Now I'm pretty lost. But it's always darker before the dawn I hope!
Hello there.

Good work so far :thumbup:

Okay, I think you should double-check your SSDT template.

I do not have access to an X99 motherboard here BUT I would expect the SS01 port to be address "0x11" SS02 to be "0x12" etc up the scale. If so then SS04 would be "0x14" - AND so would your "port-count".

I might be wrong, as I say, because I cannot check from here, but use IORegistryEplorer to double-check your addresses. :thumbup:

If they are wrong, this would explain why the USB2.0 config works but not the USB3.0.

If your addresses are correct then export your IORegistryExplorer output and post it here so we can take a look:thumbup:

As for your other question - use "255" for internal ports to prevent wake from sleep happening with a bluetooth connection. "3" will work but cause port 'polling'. It's okay if you plug-in an extra back-plate port for example.

:)
 
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