Z690 Chipset Motherboards and Alder Lake CPU

[Elias64Fr]

Thanks.
View attachment 533984

@CaseySJ

Do we need USR1 and USR2 ? As shown on Intel 600 series specification theses ports aren't used :

Another existential question, How can we have all USB 3.2 gen 2 (20Gbps) ports full operating with all USB 3.2 gen 1 (10Gbps) ports ?!?

 

[CaseySJ]

@CaseySJ

Do we need USR1 and USR2 ? As shown on Intel 600 series specification theses ports aren't used :

When we do port mapping, we'll only include HS and SS.

Another existential question, How can we have all USB 3.2 gen 2 (20Gbps) ports full operating with all USB 3.2 gen 1 (10Gbps) ports ?!?

This is why you're here! I might also try a GC-Maple Ridge card and see if we can get Thunderbolt Bus and hot-plug via SSDT...

 

[etorix]

I cannot elevate my own build to golden status! That's for the sys admins to decide.

But history suggests you have the Midas touch and your builds turn into gold…

Another existential question, How can we have all USB 3.2 gen 2 (20Gbps) ports full operating with all USB 3.2 gen 1 (10Gbps) ports ?!?

2x2 is using both sets of connectors at the same time, so it is no more demanding (but also no less) than fully mapping a non-switched USB-C port (type 10). The question is: Does OS X supports the Gen 2x2 mode of engaging both sets at the same time.
It only takes a USB 3.2 Gen 2x2 device to test.

 

[CaseySJ]

Great work everyone.

@CaseySJ , how do you feel about the chances of having a fully functional Alder-Lake Hack? (including E-Cores)

We are already able to boot with both P-cores and E-cores enabled, but we have to disable Hyper-threading on the P-cores. macOS cannot schedule tasks properly between the two core types, but neither can Windows 10, and there hasn't been too much of an issue there.

• Unless someone finds a way to tap into Intel Thread Director and build a kext for macOS that can help it schedule tasks between P- and E-cores (which does not seem very likely at this time), we can just treat all cores the same and live with that.
• We can also disable some or all E-cores so that statistically most tasks will be performed on P-cores.

We have to wait and see what the Hackintosh community can cook up!

 

[ori69]

** Little Announcement **​

I decided to assemble an Alder Lake system after all. The plan is to start with a reasonably priced Z690 DDR4 board. This means no on-board Thunderbolt.

Components ordered yesterday:

• Gigabyte Z690 Aero G (DDR4 version)
• Intel i5-12600K
• EVGA SuperNova G5 850W PSU

Components already on hand:

• OLoY 8GB x 2 for total of 16GB DDR4 3200 MHz DRAM
• Gigabyte Radeon RX 6800 XT Gaming Trio
• Flashed GC-Titan Ridge Thunderbolt 3 add-in-card
• Raijintek 280mm AIO -- but may not fit
• NZXT H510i Case with front-panel USB-C

ETA for all parts:

• Tomorrow (Friday the 12th)

P.S. I have no need for this system; this is pro bono (for the public good).

Insert GC-Titan Ridge 2 for this port,

you will add SSDT-TB3HP_RP05.AML file from my EFI folder you will have a fully operating Thunderbolt 3 with a hot-plug.

 

[AndyKramer]

When we do port mapping, we'll only include HS and SS.


This is why you're here! I might also try a GC-Maple Ridge card and see if we can get Thunderbolt Bus and hot-plug via SSDT...

let us know please how it goes with the Ridge card. I am just on the right moment to buy a new build after my x mother board passed away.

 

[Elias64Fr]

When we do port mapping, we'll only include HS and SS.


This is why you're here! I might also try a GC-Maple Ridge card and see if we can get Thunderbolt Bus and hot-plug via SSDT...

All right !

Work is in progress , you should see my last post

 

[AndyKramer]

Insert GC-Titan Ridge 2 for this port,

View attachment 533991

you will add SSDT-TB3HP_RP05.AML file from my EFI folder you will have a fully operating Thunderbolt 3 with a hot-plug.

What about the Thunderbolt header ? Should he connected somewhere on the motherboard? Let me know please where it should be connected. Thanks ++

 

[etorix]

Here you are

Thanks! PowerManagement is loaded. IntelPowerGadget should allow to test how effective it is.

I see some intriguing jumps in addresses… and an easy way to tell cores apart through frequency.
This was with 8 P-cores and hyperthreading, right?
Whenever you reboot with 8 P-cores + 8 E-cores and no hyperthreading, can you take another IOReg to compare with this one?

 

[CaseySJ]

... you should see my last post

Oh, you are a bad influence!