[SUCCESS] Gigabyte Designare Z390 (Thunderbolt 3) + i7-9700K + AMD RX 580

CaseySJ · Jul 18, 2020

roastable said:
Changing PCI0 to PCI1 made for what seems to be some un-ideal results, but the ports still work.
View attachment 480878

Great! So I'll continue forward with the setup I have as you've outlined (original SSDT for the Designare and HackinDROM SSDT for the AIC with a modification to accommodate for RP21).

I'll be sure to report back with any kernel panics. Related to the four receptacles, I've also been wondering about the Speed; how does 20Gb/s x2 differ from 40Gb/s x1 as seen in some other configurations? And is the 40Gb/s x0 for the four receptacle layout just a cosmetic issue? Is one of these more desirable or does it not matter?

As I was trying to figure out what I might try and change "PC0" to, I found this in Windows. I'm sure it's been mentioned before, but HWinfo was able to display what looks to be the correct install location for each controller (Port #21 for the AIC and Port #5 for the Designare).
View attachment 480888
View attachment 480889

Thank you very much to the both of you for your help and research.

Do not change it to PCI1. It must be PCI0.

TheWiggler · Jul 18, 2020

CaseySJ said:
The modified version was added to the Repository earlier this morning along with the DROM Micro-Guide. Please give it a try with the understanding that these modified firmwares are not perfect. It may be necessary to hot-plug devices or to warm-boot the system. And modified firmware may not play well with Windows (it may be necessary to boot macOS first and warm-boot into Windows).

Thank you, CaseySJ. I'll give it a shot and report back.

Inqnuam · Jul 18, 2020

CaseySJ said:
** Solution for Removing Duplicate Thunderbolt Port Entries **

@roastable @Inqnuam

Finally we have a solution to the problem of duplicate Port entries in System Information --> Thunderbolt.

Background:
On a system with multiple Thunderbolt controllers, we assign a unique Thunderbolt Bus ID to each one. This is done by changing the first byte of UID (in DROM) to BusID and optionally changing the first byte of ThunderboltConfig to BusID. Unfortunately, this results in duplicate ports as shown below for Bus ID 2:
...

Oh hell!
I'll update HackinDROM, thank you 2 @joevt @CaseySJ.

We need this only for AIC I guess?

Inqnuam · Jul 18, 2020

@roastable
I've updated HackinDROM as Casey explained. Please try again and let me know!
For the moment only GC Titan Ridge v1 and v2 are supported,. I'm waiting for your confirmation to apply this to Alpine Ridge too.

Thank you, guys.

djlild7hina · Jul 18, 2020

Hi @Inqnuam,

I'm trying your HackinDROM for the GC Titan Ridge and it's throwing errors when trying to save in MaciASL.

I'm seeing some spaces or invalid bytes.

Code:

"ThunderboltDROM",
                                Buffer (0x76)
                                {
0xAF, 0x00x80, 0x52, 0x67, 0x79, 0x16, 0x00, 0x00, 0x93, 0x71, 0xE7, 0xEF, 0x01, 0x6e, 0x00, 0x01, 0x00, 0x0D, 0x00, 0x01, 0x00, 0x08, 0x81, 0x8 0, 0x02, 0x8 0, 0x00, 0x00, 0x00, 0x08, 0x82, 0x9 0, 0x01, 0x8 0, 0x00, 0x00, 0x00, 0x08, 0x83, 0x8 0, 0x04, 0x8 0, 0x01, 0x00, 0x00, 0x08, 0x84, 0x9 0, 0x03, 0x8 0, 0x01, 0x00, 0x00, 0x05, 0x85, 0x50, 0x00, 0x00, 0x05, 0x86, 0x50, 0x00, 0x00, 0x02, 0x87, 0x0B, 0x88, 0x20, 0x01, 0x00, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x89, 0x80, 0x05, 0x8A, 0x50, 0x40, 0x00, 0x05, 0x8B, 0x50, 0x40, 0x00, 0xb, 0x01, 0x47, 0x49, 0x47, 0x41, 0x42, 0x59, 0x54, 0x45, 0x00, 0x16, 0x02, 0x5a, 0x33, 0x39, 0x30, 0x20, 0x47, 0x43, 0x2d, 0x54, 0x69, 0x74, 0x61, 0x6e, 0x20, 0x52, 0x69, 0x64, 0x67, 0x65, 0x00                              
                                },

For example 0x00x80, or 0x8 0, or 0x9 0

Same with thunderboltconfig

Code:

"ThunderboltConfig",
                                Buffer (0x20)
                                {
                                    /* 0000 */ 0x 0, 0x02, 0x1C, 0x00, 0x02, 0x00, 0x05, 0x03,  // ........
                                    /* 0008 */  0x01, 0x00, 0x04, 0x00, 0x05, 0x03, 0x02, 0x00,  // ........
                                    /* 0010 */  0x03, 0x00, 0x05, 0x03, 0x01, 0x00, 0x00, 0x00,  // ........
                                    /* 0018 */  0x03, 0x03, 0x02, 0x00, 0x01, 0x00, 0x02, 0x00   // ........
                                },

Inqnuam · Jul 18, 2020

djlild7hina said:

Hi @Inqnuam,

I'm trying your HackinDROM for the GC Titan Ridge and it's throwing errors when trying to save in MaciASL.

I'm seeing some spaces or invalid bytes.

Code:

"ThunderboltDROM",
                                Buffer (0x76)
                                {
0xAF, 0x00x80, 0x52, 0x67, 0x79, 0x16, 0x00, 0x00, 0x93, 0x71, 0xE7, 0xEF, 0x01, 0x6e, 0x00, 0x01, 0x00, 0x0D, 0x00, 0x01, 0x00, 0x08, 0x81, 0x8 0, 0x02, 0x8 0, 0x00, 0x00, 0x00, 0x08, 0x82, 0x9 0, 0x01, 0x8 0, 0x00, 0x00, 0x00, 0x08, 0x83, 0x8 0, 0x04, 0x8 0, 0x01, 0x00, 0x00, 0x08, 0x84, 0x9 0, 0x03, 0x8 0, 0x01, 0x00, 0x00, 0x05, 0x85, 0x50, 0x00, 0x00, 0x05, 0x86, 0x50, 0x00, 0x00, 0x02, 0x87, 0x0B, 0x88, 0x20, 0x01, 0x00, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x89, 0x80, 0x05, 0x8A, 0x50, 0x40, 0x00, 0x05, 0x8B, 0x50, 0x40, 0x00, 0xb, 0x01, 0x47, 0x49, 0x47, 0x41, 0x42, 0x59, 0x54, 0x45, 0x00, 0x16, 0x02, 0x5a, 0x33, 0x39, 0x30, 0x20, 0x47, 0x43, 0x2d, 0x54, 0x69, 0x74, 0x61, 0x6e, 0x20, 0x52, 0x69, 0x64, 0x67, 0x65, 0x00                            
                                },

For example 0x00x80, or 0x8 0, or 0x9 0

Same with thunderboltconfig

Code:

"ThunderboltConfig",
                                Buffer (0x20)
                                {
                                    /* 0000 */ 0x 0, 0x02, 0x1C, 0x00, 0x02, 0x00, 0x05, 0x03,  // ........
                                    /* 0008 */  0x01, 0x00, 0x04, 0x00, 0x05, 0x03, 0x02, 0x00,  // ........
                                    /* 0010 */  0x03, 0x00, 0x05, 0x03, 0x01, 0x00, 0x00, 0x00,  // ........
                                    /* 0018 */  0x03, 0x03, 0x02, 0x00, 0x01, 0x00, 0x02, 0x00   // ........
                                },

Yes. sir. I'm fixing this, a minor bug.

yapiyapo · Jul 18, 2020

Hello¡¡ @CaseySJ, today I want to test the new driver for Bluetooth natively https://github.com/OpenIntelWireless/IntelBluetoothFirmware/releases/tag/1.1.1 (release 1.1.1)...but in about this Mac the Bluetooth driver is empty... I put the new driver in EFI and same problem its not enable...
Any solution?
THX¡¡

Inqnuam · Jul 18, 2020

@djlild7hina @roastable Try again please

HackinDROM

I've already changed RP05 to RP21 for this AIC

roastable · Jul 18, 2020

Inqnuam said:
@roastable
I've updated HackinDROM as Casey explained. Please try again and let me know!
For the moment only GC Titan Ridge v1 and v2 are supported,. I'm waiting for your confirmation to apply this to Alpine Ridge too.

Thank you, guys.

You and @CaseySJ are absolute madlads for updating and fixing problems so quickly. Can confirm that the current version of HackinDROM is able to generate an SSDT that does not show duplicate ports and uses the chosen bus id. I should also mention that I manually edited the SSDT to change RP05->RP21 in addition to the modified bus id so that the controllers don't conflict. This allowed for the correct bus id to be shown. If you're able to @Inqnuam, perhaps this might be a nice function to add for people who have more than one Thunderbolt controller?

I also used ThunderboltUtil to update the current DROM myself and can confirm that the results seem to be the same.

Thanks again to the both of you and @joevt for ThunderboltUtil

EDIT: To avoid confusion, the screenshot labeled "RP05" is an example of the AIC incorrectly being assigned RP05 instead of RP21 as is shown in the other screenshot.

Inqnuam · Jul 18, 2020

roastable said:
You and @CaseySJ are absolute madlads for updating and fixing problems so quickly. Can confirm that the current version of HackinDROM is able to generate an SSDT that does not show duplicate ports and uses the chosen bus id. I should also mention that I manually edited the SSDT to change RP05->RP21 in addition to the modified bus id so that the controllers don't conflict. This allowed for the correct bus id to be shown. If you're able to @Inqnuam, perhaps this might be a nice function to add for people who have more than one Thunderbolt controller?

I also used ThunderboltUtil to update the current DROM myself and can confirm that the results seem to be the same.

Thanks again to the both of you and @joevt for ThunderboltUtil

1 min ago updated RP05 to RP21
Congratulations Sir!

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[SUCCESS] Gigabyte Designare Z390 (Thunderbolt 3) + i7-9700K + AMD RX 580

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