[Guide] Creating a Custom SSDT for USBInjectAll.kext

[RehabMan]

I´m not able to fill in the code for "find" and "replace".
I tried with Xcode and Plist Edit Pro, but both programs says that hex code is wrong.
For " find" I should fill in "g710////EA==" this and for "replace" this "g710////Gw==" right?

Use copy/paste from config_patches.plist provided in the USBInjectAll repo.

 

[HackToshNoob]

At a glance, it looks ok.

Success!!!! I now have only the USB ports I need showing and working. Thanks for the great guide that even a noob can fumble through! One thing I have left is to remove the port limit patch but I cannot seem to find the instructions on how to do this? Can someone point me to those instructions as I have read through this tutorial again without luck.

 

[RehabMan]

One thing I have left is to remove the port limit patch but I cannot seem to find the instructions on how to do this? Can someone point me to those instructions as I have read through this tutorial again without luck.

You should find it in your config.plist somewhere in KernelAndKextPatches/KextsToPatch.

 

[HackToshNoob]

You should find it in your config.plist somewhere in KernelAndKextPatches/KextsToPatch.

Found it! Thanks for the fast reply. It is removed.

 

[r2tincan]

Hi there. Thanks so much for the guide. The port limit patch and XCH renames weren't enough to get USB3 working on my board, I had to use all of your patches mentioned to even get testing working.

I followed your guide very closely to map out my ports. I am confused, however, on the reported mapping. The way that it looks like the ports are mapped on my board are completely insane. The first FOUR ports share one "port" and all the others have independent ports. Did I do something wrong or could this be correct?

Questions:
1. Does it make sense that one "port" could be controlling 4 USB ports and then one controller each for the remaining intel ports?
a. If it doesn't make sense, how can I trouble shoot this?
2. The GenericXCH USB got the ASMedia ports working for USB 3 (but not USB 2. obviously. but what kext do I use for USB 2?)
3. None of the templates match my device ID <31 8d 00 00> so do I just create a whole new entry for that?
4. For the sake of my sanity, would the syntax for the AML be something like:

"8086_318d", Package()
            {
                "port-count", Buffer() { 26, 0, 0, 0 },
                "ports", Package()
                {
                    "HS01", Package()
                    {
                        "UsbConnector", 3,
                        "port", Buffer() { 1, 0, 0, 0 },
                    },
                    "SSP1", Package()
                    {
                        "UsbConnector", 3,
                        "port", Buffer() { 2, 0, 0, 0 },
                    },
}

etc, etc?

I am confused what number to put inside the array. Does the array number match the physical port number or the logical one?
5. For my board, would SSP5 and HS09 have the same array numbers even though there are 4 physical ports?
6. Would SSP1 and HS01 have the same array numbers or different? Sorry I'm very not clear on syntax here.
7. I use *many* USB devices and hubs at any given moment. What do I have to do to make sure hubs work? This will change on a daily basis because of how many USB devices I'm connecting and disconnecting. I am extremely confused about what to do with external hubs and I don't know how to to map them or treat them in the aml.
8. Do I need to do anything to manage USB hubs connected via Thunderbolt or will they just work?
9. I wasn't clear on the usage of FakePCIID_XHCIMux.kext and FakePCIID kext. I installed these and the system would boot but not allow me any control of any USB device. I had a never ending spinwheel on boot and couldn't even log in, deleted the kexts. Do I need these orrrr... ?

I should mention that this board has zero USB2 ports except for in the internal headers.

Thanks so much for your time!

 

[RehabMan]

I followed your guide very closely to map out my ports. I am confused, however, on the reported mapping. The way that it looks like the ports are mapped on my board are completely insane. The first FOUR ports share one "port" and all the others have independent ports. Did I do something wrong or could this be correct?

Sounds like a hub. Nothing unusual or unexpected about internal hubs...
Port injection as described here is only for the ports on the controller. Ports on attached hubs are a separate matter.

 

[HackToshNoob]

Don't want to hijack this thread RehabMan but do you know where I can find a guide that can tell me how to get my USB-C ports working on my Designaire board? I didn't have any luck searching.

 

[RehabMan]

Don't want to hijack this thread RehabMan but do you know where I can find a guide that can tell me how to get my USB-C ports working on my Designaire board? I didn't have any luck searching.

Depends on which device the USB-c ports are connected to. If they are connected to your Intel XHCI controller, you should follow this guide. Make sure you set UsbConnector correctly based on the ACPI 6.1 spec.

 

[HackToshNoob]

Depends on which device the USB-c ports are connected to. If they are connected to your Intel XHCI controller, you should follow this guide. Make sure you set UsbConnector correctly based on the ACPI 6.1 spec.

I have the Gigabyte Z170X Designaire board. I'm not sure what a XHCI controller is but would you know the answer to that question knowing that I have the Designaire? Not sure why I assumed that USB-C ports were different than all other USB's. I didn't even test them when I did my custom SSDT. Ugh....

 

[RehabMan]

I have the Gigabyte Z170X Designaire board. I'm not sure what a XHCI controller is but would you know the answer to that question knowing that I have the Designaire? Not sure why I assumed that USB-C ports were different than all other USB's. I didn't even test them when I did my custom SSDT. Ugh....

The Intel XHCI controller is the USB3 controller provided by Intel.
Special requirements with USB-C as the cable can be turned upside down, and it is handled in different ways depending on hardware (some details in the ACPI spec).