Z690 Chipset Motherboards and Alder Lake CPU

[Elias64Fr]

Here is a Hex fiend view with header removed, we can easily see which Local APIC Id is assigned to Processor Id :
View attachment 534647

UPDATE:
Question: As we have error message during boot with x86_validate_tolopogy () 12 threads but 20 registered from MADT, why can't we see E-core threads ? We only have 4 cores.

UPDATE 2:
It seem that there is not Hyper-threading feature for E-cores

@CaseySJ

What about faking 4 more "thread" for E-Core to meet 20 registered cores on MADT ?!

Here is 2 APIC with faked 4 more threads on E-core (ordered same as P-Core and another ordered after all E-Cores)

Edit: On my laptop with 6cores/12threads, I have modified my APIC table by changing order (alternate Core/Threads to Cores then Threads) .. then verified on ACPI loaded files on MacIASL .. It boot without any problems

 

[CaseySJ]

@CaseySJ

What about faking 4 more "thread" for E-Core to meet 20 registered cores on MADT ?!

View attachment 534661

Here is 2 APIC with faked 4 more threads on E-core (ordered same as P-Core and another ordered after all E-Cores)

Alas we cannot drop and replace APIC table! Verbose output shows boot hang right at the beginning:

[EB|#LOG:EXITBS:START]

I'll switch to debug version can gather log again...

Update: User error! I used the wrong .aml file name!

 

[Elias64Fr]

Alas we cannot drop and replace APIC table! Verbose output shows boot hang right at the beginning:

[EB|#LOG:EXITBS:START]

I'll switch to debug version can gather log again...

You should see my Edit text on my previous post..

Modifications has to be done on MacIASL then recompile to correct Checksum

 

[CaseySJ]

You should see my Edit text on my previous post..

Modifications has to be done on MacIASL then recompile to correct Checksum

Are you first dropping table APIC and then adding your own SSDT-APIC?

My first test was done with one of the three original APIC files from the motherboard with no changes made by me.

I’m about to repeat the test with your “fake” versions…

 

[CaseySJ]

You should see my Edit text on my previous post..

Modifications has to be done on MacIASL then recompile to correct Checksum

Result: Unfortunately not successful (yet)!

Details:

Test 1:

• BIOS configured as follows:
  • P-cores = 6
  • E-cores = 4
  • HT = disabled
  • 10 threads

Result 1:

• APIC-1-P-E-HT-fake1.aml
  • x86_validate_topology() 10 threads but 20 registered from MADT
• APIC-1-P-E-HT-fake2.aml
  • x86_validate_topology() 10 threads but 20 registered from MADT

With HT = enabled, macOS still reports exactly the same as above (same 10 threads instead of 16).

---

Test 2:

• BIOS configured as follows:
  • P-cores = 6
  • E-cores = 0
  • HT = enabled
  • 12 threads

Result 2:

• APIC-1-P-E-HT-fake1.aml
  • x86_validate_topology() 12 threads but 20 registered from MADT
• APIC-1-P-E-HT-fake2.aml
  • x86_validate_topology() 12 threads but 20 registered from MADT

---

macOS is still getting actual thread count from somewhere and comparing it against MADT (Multiple APIC Description Table).

• When E-cores are disabled:
  • macOS computes P-cores and Hyper-Threads correctly.
  • 12 cores with HT enabled
  • 6 cores with HT disabled
  • So macOS recognizes symmetric hyper-threading
• When E-cores are enabled:
  • macOS no longer sees hyper threads
  • Only counts total number of E-cores and P-cores

 

[Elias64Fr]

Result: Unfortunately not successful (yet)!

Details:

Test 1:

• BIOS configured as follows:
  • P-cores = 6
  • E-cores = 4
  • HT = disabled
  • 10 threads

Result 1:

• APIC-1-P-E-HT-fake1.aml
  • x86_validate_topology() 10 threads but 20 registered from MADT
• APIC-1-P-E-HT-fake2.aml
  • x86_validate_topology() 10 threads but 20 registered from MADT

---

Test 2:

• BIOS configured as follows:
  • P-cores = 6
  • E-cores = 0
  • HT = enabled
  • 12 threads

Result 2:

• APIC-1-P-E-HT-fake1.aml
  • x86_validate_topology() 12 threads but 20 registered from MADT
• APIC-1-P-E-HT-fake2.aml
  • x86_validate_topology() 12 threads but 20 registered from MADT

---

macOS is still getting actual thread count from somewhere and comparing it against MADT (Multiple APIC Description Table)

I thought about the only interesting configuration with P-cores and E-cores enabled with hyper-threading enabled too.

 

[CaseySJ]

I thought about the only interesting configuration with P-cores and E-cores enabled with hyper-threading enabled too.

Please see my updated previous post (just refresh the page)!

 

[Elias64Fr]

Result: Unfortunately not successful (yet)!

Details:

Test 1:

• BIOS configured as follows:
  • P-cores = 6
  • E-cores = 4
  • HT = disabled
  • 10 threads

Result 1:

• APIC-1-P-E-HT-fake1.aml
  • x86_validate_topology() 10 threads but 20 registered from MADT
• APIC-1-P-E-HT-fake2.aml
  • x86_validate_topology() 10 threads but 20 registered from MADT

With HT = enabled, macOS still reports exactly the same as above (same 10 threads instead of 16).

---

Test 2:

• BIOS configured as follows:
  • P-cores = 6
  • E-cores = 0
  • HT = enabled
  • 12 threads

Result 2:

• APIC-1-P-E-HT-fake1.aml
  • x86_validate_topology() 12 threads but 20 registered from MADT
• APIC-1-P-E-HT-fake2.aml
  • x86_validate_topology() 12 threads but 20 registered from MADT

---

macOS is still getting actual thread count from somewhere and comparing it against MADT (Multiple APIC Description Table).

• When E-cores are disabled:
  • macOS computes P-cores and Hyper-Threads correctly.
  • 12 cores with HT enabled
  • 6 cores with HT disabled
  • So macOS recognizes symmetric hyper-threading
• When E-cores are enabled:
  • macOS no longer sees hyper threads
  • Only counts total number of E-cores and P-cores

And if we modify SSDT-CPUR-Z690 to redirect faked core on related real core (for exemple Proc Id 0x0D to 0x0C, 0x0F to 0x0E, …). I mean two CPxx have same PRxx

 

[CaseySJ]

And if we modify SSDT-CPUR-Z690 to redirect faked core on related real core (for exemple Proc Id 0x0D to 0x0C, 0x0F to 0x0E, …). I mean two CPxx have same PRxx

I'm not exactly sure what you mean, but I'm happy to attach the file for your magic hands!

I can use either of the two files attached, whichever is easier.

 

[dehjomz]

It would be good to dump x86_validate_tolopogy() to see how macOS probes the cpuid or logical/physical processors... to devise a workaround. And even if we workaround it, it's not clear how the thread scheduler will schedule threads on the Golden Cove cores vs the Gracemont cores.

One step at a time!