/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20161210-64(RM)
* Copyright (c) 2000 - 2016 Intel Corporation
*
* Disassembling to non-symbolic legacy ASL operators
*
* Disassembly of iASL8yKhjT.aml, Thu Jun 1 04:59:28 2017
*
* Original Table Header:
* Signature "SSDT"
* Length 0x0000074C (1868)
* Revision 0x01
* Checksum 0xB1
* OEM ID "APPLE "
* OEM Table ID "CpuPm"
* OEM Revision 0x00021500 (136448)
* Compiler ID "INTL"
* Compiler Version 0x20161210 (538317328)
*/
DefinitionBlock ("", "SSDT", 1, "APPLE ", "CpuPm", 0x00021500)
{
External (_PR_.CPU0, DeviceObj) // (from opcode)
External (_PR_.CPU1, DeviceObj) // (from opcode)
External (_PR_.CPU2, DeviceObj) // (from opcode)
External (_PR_.CPU3, DeviceObj) // (from opcode)
Scope (\_PR.CPU0)
{
Method (_INI, 0, NotSerialized) // _INI: Initialize
{
Store ("ssdtPRGen version.....: 21.5 / Mac OS X 10.12.5 (16F73)", Debug)
Store ("custom mode...........: 0", Debug)
Store ("host processor........: Intel(R) Core(TM) i7-3667U CPU @ 2.00GHz", Debug)
Store ("target processor......: i7-3667U", Debug)
Store ("number of processors..: 1", Debug)
Store ("baseFrequency.........: 800", Debug)
Store ("frequency.............: 2000", Debug)
Store ("busFrequency..........: 100", Debug)
Store ("logicalCPUs...........: 4", Debug)
Store ("maximum TDP...........: 17", Debug)
Store ("packageLength.........: 25", Debug)
Store ("turboStates...........: 12", Debug)
Store ("maxTurboFrequency.....: 3200", Debug)
Store ("CPU Workarounds.......: 3", Debug)
Store ("machdep.xcpm.mode.....: 0", Debug)
}
Name (APLF, One)
Name (APSN, 0x0D)
Name (APSS, Package (0x1B)
{
Package (0x06)
{
0x0C81,
0x4268,
0x0A,
0x0A,
0x2100,
0x2100
},
Package (0x06)
{
0x0C80,
0x4268,
0x0A,
0x0A,
0x2000,
0x2000
},
Package (0x06)
{
0x0C1C,
0x4268,
0x0A,
0x0A,
0x1F00,
0x1F00
},
Package (0x06)
{
0x0BB8,
0x4268,
0x0A,
0x0A,
0x1E00,
0x1E00
},
Package (0x06)
{
0x0B54,
0x4268,
0x0A,
0x0A,
0x1D00,
0x1D00
},
Package (0x06)
{
0x0AF0,
0x4268,
0x0A,
0x0A,
0x1C00,
0x1C00
},
Package (0x06)
{
0x0A8C,
0x4268,
0x0A,
0x0A,
0x1B00,
0x1B00
},
Package (0x06)
{
0x0A28,
0x4268,
0x0A,
0x0A,
0x1A00,
0x1A00
},
Package (0x06)
{
0x09C4,
0x4268,
0x0A,
0x0A,
0x1900,
0x1900
},
Package (0x06)
{
0x0960,
0x4268,
0x0A,
0x0A,
0x1800,
0x1800
},
Package (0x06)
{
0x08FC,
0x4268,
0x0A,
0x0A,
0x1700,
0x1700
},
Package (0x06)
{
0x0898,
0x4268,
0x0A,
0x0A,
0x1600,
0x1600
},
Package (0x06)
{
0x0834,
0x4268,
0x0A,
0x0A,
0x1500,
0x1500
},
Package (0x06)
{
0x07D0,
0x4268,
0x0A,
0x0A,
0x1400,
0x1400
},
Package (0x06)
{
0x076C,
0x3E5E,
0x0A,
0x0A,
0x1300,
0x1300
},
Package (0x06)
{
0x0708,
0x3A6A,
0x0A,
0x0A,
0x1200,
0x1200
},
Package (0x06)
{
0x06A4,
0x3689,
0x0A,
0x0A,
0x1100,
0x1100
},
Package (0x06)
{
0x0640,
0x32BC,
0x0A,
0x0A,
0x1000,
0x1000
},
Package (0x06)
{
0x05DC,
0x2F03,
0x0A,
0x0A,
0x0F00,
0x0F00
},
Package (0x06)
{
0x0578,
0x2B5E,
0x0A,
0x0A,
0x0E00,
0x0E00
},
Package (0x06)
{
0x0514,
0x27CC,
0x0A,
0x0A,
0x0D00,
0x0D00
},
Package (0x06)
{
0x04B0,
0x244D,
0x0A,
0x0A,
0x0C00,
0x0C00
},
Package (0x06)
{
0x044C,
0x20E2,
0x0A,
0x0A,
0x0B00,
0x0B00
},
Package (0x06)
{
0x03E8,
0x1D89,
0x0A,
0x0A,
0x0A00,
0x0A00
},
Package (0x06)
{
0x0384,
0x1A43,
0x0A,
0x0A,
0x0900,
0x0900
},
Package (0x06)
{
0x0320,
0x1710,
0x0A,
0x0A,
0x0800,
0x0800
},
Package (0x06)
{
0x02BC,
Zero,
0x0A,
0x0A,
0x0700,
0x0700
}
})
Method (ACST, 0, NotSerialized)
{
Store ("Method _PR_.CPU0.ACST Called", Debug)
Store ("CPU0 C-States : 29", Debug)
Return (Package (0x06)
{
One,
0x04,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
One,
Zero,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x03, // Access Size
)
},
0x03,
0xCD,
0x01F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000020, // Address
0x03, // Access Size
)
},
0x06,
0xF5,
0x015E
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000030, // Address
0x03, // Access Size
)
},
0x07,
0xF5,
0xC8
}
})
}
Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
{
Store ("Method _PR_.CPU0._DSM Called", Debug)
If (LEqual (Arg2, Zero))
{
Return (Buffer (One)
{
0x03
})
}
Return (Package (0x02)
{
"plugin-type",
One
})
}
}
Scope (\_PR.CPU1)
{
Method (APSS, 0, NotSerialized)
{
Store ("Method _PR_.CPU1.APSS Called", Debug)
Return (\_PR.CPU0.APSS)
}
Method (ACST, 0, NotSerialized)
{
Store ("Method _PR_.CPU1.ACST Called", Debug)
Store ("CPU1 C-States : 7", Debug)
Return (Package (0x05)
{
One,
0x03,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
One,
0x03E8,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x03, // Access Size
)
},
0x02,
0x94,
0x01F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000030, // Address
0x03, // Access Size
)
},
0x03,
0xC6,
0xC8
}
})
}
}
Scope (\_PR.CPU2)
{
Method (APSS, 0, NotSerialized)
{
Store ("Method _PR_.CPU2.APSS Called", Debug)
Return (\_PR.CPU0.APSS)
}
Method (ACST, 0, NotSerialized)
{
Return (\_PR.CPU1.ACST ())
}
}
Scope (\_PR.CPU3)
{
Method (APSS, 0, NotSerialized)
{
Store ("Method _PR_.CPU3.APSS Called", Debug)
Return (\_PR.CPU0.APSS)
}
Method (ACST, 0, NotSerialized)
{
Return (\_PR.CPU1.ACST ())
}
}
}