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X299 Big Sur Support

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Last edited:
Joined
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I thougt you updated your Bios recently, so if no improuvment the previous version .
Thanks for the clarification -- I did recently update my BIOS to 3203 recently, but my problems were worse on 3101 (I updated with the hopes of maybe fixing my bugs). The recent improvement in stability (and TB3 drives at boot) has been on BIOS 3203 after I turned off XMP and dropped the RAM speed from 3466MHz down to a MacOS reported 2133MHz. I do not know if the increased stability would have also been seen on BIOS 3101 with the RAM speed decreased, as I never tried it. Does any of that give any clues about the original problems I had when the RAM was running at XMP speed of 3466MHz? Any clues about how to get the current stability with my RAM running at the rated speed (3466MHz)? Thanks!
 

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Joined
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Thanks for the clarification -- I did recently update my BIOS to 3203 recently, but my problems were worse on 3101 (I updated with the hopes of maybe fixing my bugs). The recent improvement in stability (and TB3 drives at boot) has been on BIOS 3203 after I turned off XMP and dropped the RAM speed from 3466MHz down to a MacOS reported 2133MHz. I do not know if the increased stability would have also been seen on BIOS 3101 with the RAM speed decreased, as I never tried it. Does any of that give any clues about the original problems I had when the RAM was running at XMP speed of 3466MHz? Any clues about how to get the current stability with my RAM running at the rated speed (3466MHz)? Thanks!
It is not perfect though, just a little more stable. I just crashed when I was rendering a video in FCPX. I attached the crash report text in case someone can read it. Looks the same as all of the rest in the past: "panic(cpu 2 caller 0xffffff7f937c2ad5): userspace watchdog timeout: no successful checkins from com.apple.WindowServer in 120 seconds"
 

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Joined
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It is not perfect though, just a little more stable. I just crashed when I was rendering a video in FCPX. I attached the crash report text in case someone can read it. Looks the same as all of the rest in the past: "panic(cpu 2 caller 0xffffff7f937c2ad5): userspace watchdog timeout: no successful checkins from com.apple.WindowServer in 120 seconds"
I did some research about your problem.

This should explain that your problem is complex related to hardware, applications and MacOs: so not easy to solve but maybe you can find out more with that :

- There are specific problems about rendering a video in FCPX see here Apple discussions or here bcp.co forum

- There are problems reported Kernel Panics – userspace from com.apple.WindowServer on Catalina even on MacPro 7,1 in a dedicated thread macrumors thread

I'm not expert with FXP rendering : but for exemple if you use attached Thunderbolt devices to export your FXP rendering file.

Another way : your Thunderbolt raid storage devices combined with Catalina.

But my two points linked below converge on the Thunderbolt Titan Ridge : I can not find for now a solution to resolve your problem : because I know that RAID storage devices are important for your build and use.

Maybe another experienced owner will give you feedback or an improvement to fix this.
 
Last edited:
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@Loloflatsix

For my RP05 and RP07 PXSX the IOAPCIPlane shows as PC00 so do I change this in the SSDT XHC to PC00?

Also for the device ID to be complete do I add the vendor ID where it has 0x00 and 0x00 see below:

Code:
                        "device-id",
                        Buffer (0x04)
                        {
                             0x42, 0x21, 0x00, 0x00                           // B!..
                        },

Should that not be:

Code:
                        "device-id",
                        Buffer (0x04)
                        {
                             0x42, 0x21, 0x21, 0x1b                           // B!..
                        },



Since it says Device ID I will assume only the device ID goes in not the vendor. SO I have loaded DTGP XHC and XHCI SSDTs can you see if they look correct so far with 2nd Ioreg posted.

I have not loaded the modified USBport.kext yet with adding the power properties still in the USBX SSDT with first Ioreg attached, but if we load the properties into the kext then the kUSB needs to be removed from EC-USBX correct? So first Ioreg shows what it will look like without the modified USBPort.kext, the port names HS and SS don't show up :)

Attached Ioreg's without modified kext and Removed Kusb power properties from EC-USBX and named it just SSDT-EC, with Modified USBPort.kext.

How does it look so far? Need help with the external USB 3 card kinda lost on how to configure this both SSDT and Kext.

Actually for cosmetic purposes I should rename those PXSX controllers in SSDT as USB 3.2 Gen2.

I think I am missing something you mentioned to me XHC2? I am using all ports internally the 20pin USB3 internal and Gen2 type C think it’s 8 pin internal so I need XHC2,3 and 4? XHC5 would be for PCIe inatech usb3 card has 20pin and two usb3 A type.

Sorry edited again I think I’ll enable usbinjectall again remove SSDT and usb kext to make sure I have all ports. I think I’m getting more confused on what is on XHCI maybe the internal 20 pin is part of that? Only the usb c internal small gen2 connector and on external plate usb c and a green usb A which is usb 3 are pxsx? The order of XHC2,3,4 how do you get order from ioreg top to bottom entry?

Sorry Edited Again:

So I confirmed that only one internal USB 3 20 pin connector inside the board near the SATA connectors on SAGE II is in the XHCI group don't need to separate that? The internal small Gen2 connector on the board is RP07 has USB3 SS01/2 USB2 HS01/2. I named this XHC2 should that be XHC3?


The external plate USB C and Type A looks blue/green is on RP05. That should have 4 ports correct with USBinjectall I see only SS01/2 and HS01 no HS02. Would this be XHC3 or XHC4? What would be XHC2? maybe you have a second USB3 20 pin?

Since the Inatech USB 3 PCIe card is at the end of the of the ioreg I have to assume you number the XHC last.

So is it correct for me to have XHC2,3 and 4, XHC4 for the PCIe card? XHC2 RP05 and XHC3 RP07 and XHC4 will be the PCIe Inateck USB 3 card which has internal 20 pin USB3 and two external type A USB3, one of which seems to load on 2.0 instead of 3.0 as I mentioned before maybe it sharing some port?

Edited One more Time clear some more things:

In the Bios I have 3 individual connectors all Gen 2 I can enable/disable which I did to figure out which connector goes where.

U32G2_E1 = Internal USB 3.2 Gen 2 small connector like 8 pin cable to case USB C.
U32G2_E2 = External Plate USB 3.2 Gen 2 Type A
U32G2_EC1 = External Plate USB 3.2 Gen 2 USB C

So would these each be the XHC2,3,4 because the U32G2_E2 and U32G2_EC1 are both on RP05, do I separate them and if not that leaves me with only two XHC's right and use XHC2 and XHC3? USBG2_E1 is on RP07.

Also please verify PC00 for XHC2, XHC3 and XHCI and PC01 for PCIe card if I have this correct in SSDT?
 

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  • osxfr33k’s iMac Pro_With_XHC_XHCI_Mod_USBPort.ioreg.zip
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  • SSDT-X299-XHC.aml.zip
    1.3 KB · Views: 17
  • SSDT-X299-XHCI.aml.zip
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  • USBPorts.kext_With_kUSB_And_XHC_Mod.zip
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Last edited:
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hello i have asus x299 tuf mark 2 moterboard and bios 3105 i can not flash back the bios version and not install macos please help me
 
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Question regarding the Airport SSDT doesn't seem to be loading it in Ioreg or System Information under PCI, its under PCI but not as it is in SSDT as far as the name so I am figuring its not loading correctly?

Snapshot of SSDT which I modified according to my original Ioreg such as PC and BR and SL.

Code:
DefinitionBlock ("", "SSDT", 1, "LOLO", "X299ARPT", 0x00000000)
{
    External (_SB_.PC01.BR1A, DeviceObj)
    External (_SB_.PC01.BR1A.PEGP, DeviceObj)
    External (_SB_.PC01.BR1A.SL01, DeviceObj)
    External (DTGP, MethodObj)    // 5 Arguments

    Scope (_SB.PC01.BR1A)
    {
        Scope (SL01)
        {
            Name (_STA, Zero)  // _STA: Status
        }

        Scope (PEGP)
        {
            Name (_STA, Zero)  // _STA: Status
        }

        Device (ARPT)
        {
            Name (_ADR, Zero)  // _ADR: Address
            Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
            {
                Local0 = Package (0x0E)
                    {
                        "built-in",
                        Buffer (One)
                        {
                             0x00                                             // .
                        },

                        "device-id",
                        Buffer (0x04)
                        {
                             0xA0, 0x43, 0x00, 0x00                           // .C..
                        },

                        "AAPL,slot-name",
                        Buffer (0x07)
                        {
                            "Slot-6"
                        },

                        "device_type",
                        Buffer (0x13)
                        {
                            "AirPort Controller"
                        },

                        "model",
                        Buffer (0x4A)
                        {
                            "OSX WIFI Broadcom BCM94360CD 802.11 a/b/g/n/ac + Bluetooth 4.0 Controller"
                        },

                        "compatible",
                        Buffer (0x0D)
                        {
                            "pci14e4,43a0"
                        },

                        "name",
                        Buffer (0x10)
                        {
                            "AirPort Extreme"
                        }
                    }
                DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                Return (Local0)
            }
        }
    }
}

Pictures of Ioreg and PCI information from System Information:

Screen Shot 2020-09-27 at 5.31.04 PM.png


Says Other Network Card?


Screen Shot 2020-09-27 at 5.32.02 PM.png
 

Ellybz

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GUIDE TO CREATE EDIT MODIFY YOUR OWN USB.kext FOR YOUR X299 MOTHERBOARD
---------
Enjoy :thumbup:

First and foremost, thanks for the heads up, details & directions for this new USB.Kext expansion. You Sir rock :headbang:
I did a few modifications to your guide as I did not want to use any SSDTs for XHCs or TB.( Only device properties )
I was able to rename the ports within the kext itself using the IONameMatch ( see screenshot below ).

I have now the properties from the SSDT-USBX attached to ALL my USB ports, without the SSDT. I also got rid of the SSDT-plug as I have native XCPM from my Bios. Native XCPM gives me 10 speed steps from 1.12Ghz to 5Ghz ;Idle @1.12 ( tested for over 2 weeks ).

Now, I can boot & run successfully Big Sur, Catalina & Mojave:

-SSDT-USBX is gone!!!
-SSDT-PLUG is gone !!!!
(Gigabyte x299 does not need SSDT for EC or RTC, XOSI or SBUS); so my ACPI Folder is now empty :headbang::clap::)

My custom USB kext is fully loaded with all my ports. ( Note that my XHCI has now 22 ports fully functional )

Sleep & Wake functions are still working perfectly.

Kudos to @Loloflatsix

PS: I still need to rename the ports on my Inateck Pcie Card..Will do it shortly.

TB01/02/03/04 are the ports I renamed for the Alpine ridge TB3

And to top off my Sunday..New High Score on CINEBENCH R20: above 10400 :lol:

Thanks again for all your contributions :wave:

EDIT: I will make sure to report back on this post if any bug or unstable behavior occurs.

Screen Shot 2020-09-27 at 21.25.05.png


Screen Shot 2020-09-27 at 21.18.47.png


Screen Shot 2020-09-27 at 22.40.03.png


Screen Shot 2020-09-27 at 16.53.06.png




Screen Shot 2020-09-26 at 10.40.15.png
 
Last edited:
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As this thread is oriented to all x299 motherboard models, I will propose to put together all the know how related to the alternative SSDT/device properties/USB, trying to expand the PDF guide already posted by @Loloflatsix, to let all us capable to better self configure the EFIs ...
 
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@Loloflatsix

For my RP05 and RP07 PXSX the IOAPCIPlane shows as PC00 so do I change this in the SSDT XHC to PC00?

Also for the device ID to be complete do I add the vendor ID where it has 0x00 and 0x00 see below:

Code:
                        "device-id",
                        Buffer (0x04)
                        {
                             0x42, 0x21, 0x00, 0x00                           // B!..
                        },

Should that not be:

Code:
                        "device-id",
                        Buffer (0x04)
                        {
                             0x42, 0x21, 0x21, 0x1b                           // B!..
                        },



Since it says Device ID I will assume only the device ID goes in not the vendor. SO I have loaded DTGP XHC and XHCI SSDTs can you see if they look correct so far with 2nd Ioreg posted.

I have not loaded the modified USBport.kext yet with adding the power properties still in the USBX SSDT with first Ioreg attached, but if we load the properties into the kext then the kUSB needs to be removed from EC-USBX correct? So first Ioreg shows what it will look like without the modified USBPort.kext, the port names HS and SS don't show up :)

Attached Ioreg's without modified kext and Removed Kusb power properties from EC-USBX and named it just SSDT-EC, with Modified USBPort.kext.

How does it look so far? Need help with the external USB 3 card kinda lost on how to configure this both SSDT and Kext.

Actually for cosmetic purposes I should rename those PXSX controllers in SSDT as USB 3.2 Gen2.

I think I am missing something you mentioned to me XHC2? I am using all ports internally the 20pin USB3 internal and Gen2 type C think it’s 8 pin internal so I need XHC2,3 and 4? XHC5 would be for PCIe inatech usb3 card has 20pin and two usb3 A type.

Sorry edited again I think I’ll enable usbinjectall again remove SSDT and usb kext to make sure I have all ports. I think I’m getting more confused on what is on XHCI maybe the internal 20 pin is part of that? Only the usb c internal small gen2 connector and on external plate usb c and a green usb A which is usb 3 are pxsx? The order of XHC2,3,4 how do you get order from ioreg top to bottom entry?

Sorry Edited Again:

So I confirmed that only one internal USB 3 20 pin connector inside the board near the SATA connectors on SAGE II is in the XHCI group don't need to separate that? The internal small Gen2 connector on the board is RP07 has USB3 SS01/2 USB2 HS01/2. I named this XHC2 should that be XHC3?


The external plate USB C and Type A looks blue/green is on RP05. That should have 4 ports correct with USBinjectall I see only SS01/2 and HS01 no HS02. Would this be XHC3 or XHC4? What would be XHC2? maybe you have a second USB3 20 pin?

Since the Inatech USB 3 PCIe card is at the end of the of the ioreg I have to assume you number the XHC last.

So is it correct for me to have XHC2,3 and 4, XHC4 for the PCIe card? XHC2 RP05 and XHC3 RP07 and XHC4 will be the PCIe Inateck USB 3 card which has internal 20 pin USB3 and two external type A USB3, one of which seems to load on 2.0 instead of 3.0 as I mentioned before maybe it sharing some port?

Edited One more Time clear some more things:

In the Bios I have 3 individual connectors all Gen 2 I can enable/disable which I did to figure out which connector goes where.

U32G2_E1 = Internal USB 3.2 Gen 2 small connector like 8 pin cable to case USB C.
U32G2_E2 = External Plate USB 3.2 Gen 2 Type A
U32G2_EC1 = External Plate USB 3.2 Gen 2 USB C

So would these each be the XHC2,3,4 because the U32G2_E2 and U32G2_EC1 are both on RP05, do I separate them and if not that leaves me with only two XHC's right and use XHC2 and XHC3? USBG2_E1 is on RP07.

Also please verify PC00 for XHC2, XHC3 and XHCI and PC01 for PCIe card if I have this correct in SSDT?
Your IOReg looks good :
All the ports under XHC2 , XHC3 and XHCI are loaded on the right side.

Just some improvements :
- On SSDT-X299-XHC :
1/ XHC2 : 2 ports USB 3.2 Gen1 Type-A External (N° 6 : USB 3.2 Gen 1 ports 7 and 8 on rear IO)
2/ XHC3 : 1x USB 3.2 Type-A / ASM1543 1x USB 3.2 Type-C External (gen 2) - ( N°9 USB 3.2 Gen 2 Type-C® port EC1 and N°5 USB 3.2 Gen 2 port E2 on rear IO)

- On USB.kext :
1/ XHC2 : HS01 and HS02 : usb-connector : 2 (never 255 on external) -SS01 and SS02 : usb-connector : 3 OK (N° 6 : USB 3.2 Gen 1 ports 7 and 8 on rear IO)
2/ XHC3 : HS01 and SS01 : usb-connector : 9 (10 works also) and HS02 and SS02 : usb-connector : 3 (never 255 on external) ( N°9 USB 3.2 Gen 2 Type-C® port EC1 and N°5 USB 3.2 Gen 2 port E2 on rear IO)

Only for cosmetic but SSDT--X299-XHCI no more needed and we can achieve that by adding PciRoot device properties on OC config.plist

I don't think your internal USB C header is plugged actually.

Note : usb-connector : 255 only for USB Wifi header if plugged in.
 

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  • SSDT-X299-XHC.aml
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  • USBPorts-V2.kext.zip
    2.9 KB · Views: 23
Last edited:
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