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SSDT GPU (Graphics Card) Injection

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Thanks for being helpful. I know. SUN is a automatic function but it gives different naming based on system definition.
No problem, does it matter in terms of functionality or is it mostly aesthetics? I also patched the port types after making sure that the addresses were right figuring 0 goes unused, thinking ports could be zero indexed. They weren't, which is easy to figure out by plugging in displays and checking ioreg.

Also, technical question, if I left in SUN, and added the slot patch below, SUN took precedence, is that because it comes above, or is that a function of the method?
 
No problem, does it matter in terms of functionality or is it mostly aesthetics? I also patched the port types after making sure that the addresses were right figuring 0 goes unused, thinking ports could be zero indexed. They weren't, which is easy to figure out by plugging in displays and checking ioreg.

Also, technical question, if I left in SUN, and added the slot patch below, SUN took precedence, is that because it comes above, or is that a function of the method?
SUN always overrides aapl,slot-name. It's not because of it's location. It's mostly esthetic regardless of which one you use.
 
Hi "Shilohh"
I'm gonna follow your instructions. I'm getting at step 1. There is no any NPE or PEG in my IORegistry and DSDT at all. Then I don't know how to move further. Please advise. I uploaded my IORegistry and DSDT for your analysis and advice. Secondly. I have the FakeID key per your instructions, should I remove those keys in config.plst? Thanks.


My build is :
I7 6800K
Asrock Taichi X99
Asus ROG Strix GTX1060 6GB.
MacOS Sierra 10.12.4
RAM Corsair Vegeneance LED 3200 32GB
 

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Thanks a lot. Then I must start from step 3b, correct?
Correct, look for these patches - Disable PCI0.BR3A.D076.txt, Disable PCI0.BR3A.H000 & H001.txt
 
Correct, look for these patches - Disable PCI0.BR3A.D076.txt, Disable PCI0.BR3A.H000 & H001.txt
My address in DSDT is BR3A.
I'm following the instruction 3b by using SSDT-1 file from the given SSDTFiles.zip.

The original address in SSDT-1 is _SB.PCI0.NPE3.GFX1 and _SB.PCI0.NPE3.HDAU

after applying the patch from the Disable file.
The patch added 2 lines :
Name (_SB.PCI0.BR3A.H000._STA, Zero)
Name (_SB.PCI0.BR3A.H001._STA, Zero)

I found that the address of device in the upper part is still NPE3. It is not changed to BR3A. Is this correct? The contents in the SSDT-1 after applying the patch is as below. Please advise if this is correct. Thanks, sir.
Remark : If the address after applying the patch should be BR3A (but the PATCH didn't change accordingly), should I change it manually?

/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20161210-64(RM)
* Copyright (c) 2000 - 2016 Intel Corporation
*
* Disassembling to non-symbolic legacy ASL operators
*
* Disassembly of iASLVWeEs6.aml, Tue May 9 07:24:45 2017
*
* Original Table Header:
* Signature "SSDT"
* Length 0x000000BA (186)
* Revision 0x01
* Checksum 0x54
* OEM ID "shiloh"
* OEM Table ID "GFX1"
* OEM Revision 0x00001000 (4096)
* Compiler ID "INTL"
* Compiler Version 0x20100331 (537920305)
*/
DefinitionBlock ("", "SSDT", 1, "shiloh", "GFX1", 0x00001000)
{
Device (_SB.PCI0.NPE3.GFX1)
{
Name (_ADR, Zero) // _ADR: Address
Name (_SUN, One) // _SUN: Slot User Number
Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
{
If (LEqual (Arg2, Zero))
{
Return (Buffer (One)
{
0x03
})
}

Return (Package (0x02)
{
"hda-gfx",
Buffer (0x0A)
{
"onboard-1"
}
})
}
}

Device (_SB.PCI0.NPE3.HDAU)
{
Name (_ADR, One) // _ADR: Address
Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
{
If (LEqual (Arg2, Zero))
{
Return (Buffer (One)
{
0x03
})
}

Return (Package (0x02)
{
"hda-gfx",
Buffer (0x0A)
{
"onboard-1"
}
})
}
}
Name (_SB.PCI0.BR3A.H000._STA, Zero)
Name (_SB.PCI0.BR3A.H001._STA, Zero)
}
 
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Sorry for a few more questions. The next instruction as shown in the uploaded snapshot. What should I do to align with my question 1 above.

The last question : suppose I follow everything correctly, Do I have to do step 3c (my card is GTX1060 PASCAL, I didn't find a patch file for my PASCAL card for step 3c)?

Thanks, sir.
 

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If the address after applying the patch should be BR3A (but the PATCH didn't change accordingly), should I change it manually?
Yes, change NPE3 to BR3A. You also need to apply Disable PCI0.BR3A.D076.txt patch.
 
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