(Edited to correct and expand)
USB 3 and USB 2 (+USB 1) are separate circuits in the same socket and appear as distinct "ports" for mapping, each counting against the 15 max per root hub controller. When mapping, these are sometimes referred to as companions because they share a socket. You can enable either companion or both.
For example, 7 back-panel sockets with 2 & 3 enabled are 14. But there are also internal ports on the same root hub, like BT, LED, plus typically 2 ports (USB 2 & 3) that connect to an another onboard hub that fans out to the front-panel.
So you'll have to make some compromises about which of these to enable to get a fit. For example maybe only enable USB 2 on a couple of sockets.
USB via Thunderbolt is on its own root, so these don't count. Ports on add in cards don't count. I think gen 2x2 is usually front-panel which is sourced by the internal hub hanging off the back-panel root.
So the only challenge is getting the backpanel plus internal that hang off the backpanel root to fit into 15. This will become clear with via toolbox.
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As an aside..
All devices on a root controller share the PCIe lanes for that controller. So the total amount of USB port bandwidth presented at sockets tends to exceed the PCIe bandwidth for the root controller.
This matters for some use cases.
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Further aside...
USB2 was a CPU-polled I/O not DMA, so it's relatively compute expensive to run at high load.
USB 3 greatly improved bus dynamics with DMA and events to get a 10x bandwidth gain (450M to 5G) while not growing CPU workload.
3.1 gen 1 doubled USB 3 signaling to 10G.
USB 3.2 gen 2x2 is two 3.1 gen 1 ports married into a type-C socket to get 20G.
Apple wisely punted this gen2x2 nonsense and went to Thunderbolt which is actually scalable.
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Heading out to orbit...
Above USB, chipset topology and bandwidth sharing plays out again at PCIe bus as devices are ganged onto lanes and share those lanes' bandwidth.
In a modern desktop board, there are typically 28 lanes (at whatever generation mix) where 20 are direct CPU lanes (what used to be called northbridge) for traditional first-class PCI, including GPU and add-in cards, and 8 more CPU lanes feed the "chipset" via DMI (what used to be called southbridge) that fan out into many 20 logical lanes, allowing more slots, and devices.
If you carefully read the mainboard documentation, the topology details are spelled out by a bunch of feature conditions.
For the z590 ROG Hero I use, the docs reads as follows:
- M.2_1 - CPU, PCIe 4.0, disabled except for 11th Gen
- M.2_2 - CPU, PCIe 4.0 or PCIe 3.0 (when in use, PCIEX16_1 @ x8 and PCIEX16_2 @ x4)
- M.2_3 - Chipset, PCIe 3.0 or SATA
- M.2_4 - Chipset, PCIe 3.0 or SATA (when in use, SATA6G_56 disabled)
- PCIe x16_3 [chipset implied] - when @ x2 SATA6G_34 is disabled, when @ x4 SATA6G_12 & SATA6G_34 is disabled
When you read between the lines these conditions say that with 10th gen, only one m.2 slot gets first class x4 connection to CPU and this prevents a x16 GPU because otherwise there are not enough lanes to serve all the slots.
Note that when the third PCI3 x16 slot is populated at x4, all onboard SATA are disabled.
The generational advance for 11th gen was that PCIe 4.0 signaling doubled over 10th gen so 11th gen x8 GPU has same bus performance as 10th gen x16. When you carefully read the board specs, the proper generational charges become evident, including important details left out of the marketing hype.
The fanout for lanes and bandwidth is well thought out in the mainboard topology, and to be sure there's not as much bandwidth as slots.
These are factors to be aware of if you are building high-end AV kit. Topology limits may lead to problems for certain workflows where nerds overload their kit not understanding the internals, especially for DAW where "artists" keep piling on until camel's back breaks..
Lanes and allocations are one of the primary distinctions between "desktop", "high-end desktop" and "server". The other is ECC RAM which is critical for engineering and high value media.
In Intel parlance, desktop (Z) is about peak gaming and user media experience
High-end desktop (X) adds more ports via DMI lanes via chipset, and tradeoff to peak gaming.
Workstation is a variety of Xeon with more CPU lanes and ECC.
Server is another kind of Xeon for racks.
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Deep space...
The OSX USB 15 port limit represents a historical feature of Apple's system software awareness of chipset topology.
But the bigger picture is Apple is always re-designing its kit with all these tradeoffs in mind.
Plus, Intel started building a licensing model into Xeon sub units, which Apple looked at, along with many other architecture aspects, and said "No."
For hackers, Apple can now evolve the entire architecture faster at a price-point than value-oriented nerds can keep up with the details in the mainboard manuals.
Such are these times.
