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[Guide] Creating a Custom SSDT for USBInjectAll.kext

deeveedee said:
Thank you. It is attached to a real port; however, I would love to learn more. What would I inspect in a PR dump to determine whether a port is "real" or internal.
Click to expand...

Ports connected to internal devices are relatively obvious, as the port shows as attached to a device upon booting, but without plugging anything in.
 
iancarleton said:
Hello Rehabman,

Thank you for the clear instructions and all the hard work that you have put into this site.
This is my first time reaching out for support, please advise if I am missing information.

I've had success limiting ports, but get the following error when trying to eliminate EHCI. (I do not believe I need to keep EHCI)

"143, 6126, syntax error, unexpected PARSEOP_EXTERNAL, expecting $end and premature End-Of-File"

Can you advise how to get past this error?

Thank you in advance,
Ian


Here's my SSDT, other information attached.

Code: 
/*
 * Intel ACPI Component Architecture
 * AML/ASL+ Disassembler version 20180427 (64-bit version)(RM)
 * Copyright (c) 2000 - 2018 Intel Corporation
 *
 * Disassembling to non-symbolic legacy ASL operators
 *
 * Disassembly of iASLVW4Upv.aml, Fri Dec  7 14:44:23 2018
 *
 * Original Table Header:
 *     Signature        "SSDT"
 *     Length           0x000001AA (426)
 *     Revision         0x02
 *     Checksum         0xFF
 *     OEM ID           "hack"
 *     OEM Table ID     "_UIAC"
 *     OEM Revision     0x00000000 (0)
 *     Compiler ID      "INTL"
 *     Compiler Version 0x20180427 (538444839)
 */
DefinitionBlock ("", "SSDT", 2, "hack", "_UIAC", 0x00000000)
{
    Device (UIAC)
    {
        Name (_HID, "UIA00000")  // _HID: Hardware ID
        Name (RMCF, Package (0x02)
        {
            "8086_8xxx",
            Package (0x04)
            {
                "port-count",
                Buffer (0x04)
                {
                     0x15, 0x00, 0x00, 0x00                       
                },

                "ports",
                Package (0x10)
                {
                    "HS01",
                    Package (0x04)
                    {
                        "UsbConnector",
                        0x03,
                        "port",
                        Buffer (0x04)
                        {
                             0x01, 0x00, 0x00, 0x00                       
                        }
                    },

                    "HS02",
                    Package (0x04)
                    {
                        "UsbConnector",
                        0x03,
                        "port",
                        Buffer (0x04)
                        {
                             0x02, 0x00, 0x00, 0x00                       
                        }
                    },

                    "HS09",
                    Package (0x04)
                    {
                        "UsbConnector",
                        0x03,
                        "port",
                        Buffer (0x04)
                        {
                             0x09, 0x00, 0x00, 0x00                       
                        }
                    },

                    "HS10",
                    Package (0x04)
                    {
                        "UsbConnector",
                        0x03,
                        "port",
                        Buffer (0x04)
                        {
                             0x0A, 0x00, 0x00, 0x00                       
                        }
                    },

                    "SS01",
                    Package (0x04)
                    {
                        "UsbConnector",
                        0x03,
                        "port",
                        Buffer (0x04)
                        {
                             0x10, 0x00, 0x00, 0x00                       
                        }
                    },

                    "SS02",
                    Package (0x04)
                    {
                        "UsbConnector",
                        0x03,
                        "port",
                        Buffer (0x04)
                        {
                             0x11, 0x00, 0x00, 0x00                       
                        }
                    },

                    "SS05",
                    Package (0x04)
                    {
                        "UsbConnector",
                        0x03,
                        "port",
                        Buffer (0x04)
                        {
                             0x14, 0x00, 0x00, 0x00                       
                        }
                    },

                    "SS06",
                    Package (0x04)
                    {
                        "UsbConnector",
                        0x03,
                        "port",
                        Buffer (0x04)
                        {
                             0x15, 0x00, 0x00, 0x00                       
                        }
                    }
                }
            }
        })
    }
}
//
// Disabling EHCI #1
//
    External(_SB.PCI0, DeviceObj)
    External(_SB.PCI0.LPCB, DeviceObj)
    External(_SB.PCI0.EH01, DeviceObj)
    Scope(_SB.PCI0)
    {
        // registers needed for disabling EHC#1
        Scope(EH01)
        {
            OperationRegion(PSTS, PCI_Config, 0x54, 2)
            Field(PSTS, WordAcc, NoLock, Preserve)
            {
                PSTE, 2  // bits 2:0 are power state
            }
        }
        Scope(LPCB)
        {
            OperationRegion(RMLP, PCI_Config, 0xF0, 4)
            Field(RMLP, DWordAcc, NoLock, Preserve)
            {
                RCB1, 32, // Root Complex Base Address
            }
            // address is in bits 31:14
            OperationRegion(FDM1, SystemMemory, Add(And(RCB1,Not(Subtract(ShiftLeft(1,14),1))),0x3418), 4)
            Field(FDM1, DWordAcc, NoLock, Preserve)
            {
                ,15,    // skip first 15 bits
                FDE1,1, // should be bit 15 (0-based) (FD EHCI#1)
            }
        }
        Device(RMD1)
        {
            //Name(_ADR, 0)
            Name(_HID, "RMD10000")
            Method(_INI)
            {
                // disable EHCI#1
                // put EHCI#1 in D3hot (sleep mode)
                Store(3, ^^EH01.PSTE)
                // disable EHCI#1 PCI space
                Store(1, ^^LPCB.FDE1)
            }
        }
    }
}
//EOF
Click to expand...

You have an extraneous close brace:
Code: 
}  // extraneous
//
// Disabling EHCI #1
//
 
Hello RehabMan, I have a USB3.1 controller on my MB, device ID is 15b6. I can not found any change in the "IORegistryExplorer"(XHC part) when I plug or unplug device.
And I can not find 15b6 in that template file either.
Now my USB3.0 a12f is done, work perfectly, but how should I treat with my USB3.1 15b6? The USB3.0 disk plug into this port, sometimes ok, but sometimes not, so I think I should do something.

Thanks
 
RehabMan said:
Ports connected to internal devices are relatively obvious, as the port shows as attached to a device upon booting, but without plugging anything in.
Click to expand...
Thank you.
 
Hillperson said:
Hello RehabMan, I have a USB3.1 controller on my MB, device ID is 15b6. I can not found any change in the "IORegistryExplorer"(XHC part) when I plug or unplug device.
And I can not find 15b6 in that template file either.
Now my USB3.0 a12f is done, work perfectly, but how should I treat with my USB3.1 15b6? The USB3.0 disk plug into this port, sometimes ok, but sometimes not, so I think I should do something.

Thanks
Click to expand...
No "Problem Reporting" files attached.
Read FAQ, "Problem Reporting" again. Carefully. Attach all requested files/output.
https://www.tonymacx86.com/threads/faq-read-first-laptop-frequent-questions.164990/
Use the gen_debug.sh tool mentioned in the FAQ, that way it is less likely you'll omit something.
 
I am running into confusion at the partial injection step. How are you able to inject each individual type, i.e. "Injection of just HSxx:" vs. "Injection of just HS03,SSxx,USRx:"? My IOReg always just looked like your screenshot for "Injection of just HSxx:", I have no idea how to get the SSxx to appear. I ahve followed all the steps up to this point closely, installing the kexts, copying patches from your config.plist_patches, etc.
 
GryphonP3 said:
I am running into confusion at the partial injection step. How are you able to inject each individual type, i.e. "Injection of just HSxx:" vs. "Injection of just HS03,SSxx,USRx:"? My IOReg always just looked like your screenshot for "Injection of just HSxx:", I have no idea how to get the SSxx to appear. I ahve followed all the steps up to this point closely, installing the kexts, copying patches from your config.plist_patches, etc.
Click to expand...

You don't have the patch already in you EFI by chance do you? And are you plugging a 3.0 device into the port?
 
NorthAmTransAm said:
You don't have the patch already in you EFI by chance do you? And are you plugging a 3.0 device into the port?
Click to expand...

I am not exactly sure what you are asking by "already in EFI"

I copied the patches from the conig.plist_patches in Rehabman's github as per the guide, and pasted them into the same area within my own config.plist in my EFI->Clover folder. Was this incorrect?

And yes, my external hard drives are USB3.0 which is really killing me because I can't access any of my music projects since upgrading to Mojave, and this computer is solely a studio machine.
 
GryphonP3 said:
I am not exactly sure what you are asking by "already in EFI"

I copied the patches from the conig.plist_patches in Rehabman's github as per the guide, and pasted them into the same area within my own config.plist in my EFI->Clover folder. Was this incorrect?

And yes, my external hard drives are USB3.0 which is really killing me because I can't access any of my music projects since upgrading to Mojave, and this computer is solely a studio machine.
Click to expand...

Thats what I meant. I left that patch out while discovering ports and it worked for me. Just stick it on your desktop for now.
 
GryphonP3 said:
I am running into confusion at the partial injection step. How are you able to inject each individual type, i.e. "Injection of just HSxx:" vs. "Injection of just HS03,SSxx,USRx:"? My IOReg always just looked like your screenshot for "Injection of just HSxx:", I have no idea how to get the SSxx to appear. I ahve followed all the steps up to this point closely, installing the kexts, copying patches from your config.plist_patches, etc.
Click to expand...

As per post #1, use -uia_exclude_hs to test your SSxx ports.

GryphonP3 said:
I copied the patches from the conig.plist_patches
Click to expand...

config_patches.plist has nothing to do with this guide.
You should read post #1. Again. Carefully.
 
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