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[Guide] Creating a Custom SSDT for USBInjectAll.kext

RehabMan said:
There is some discussion about the way Apple chose a poor name with regards to "port-count":
https://www.tonymacx86.com/threads/guide-10-11-usb-changes-and-solutions.173616/

(hint: it really isn't a "count" at all)
Click to expand...
sigh - OK, maximum port address (as specified by 'port'). For my 8086_9d2f, should I in any case leave the "port-count" at SSDT-UIAC-ALL.dsl default setting of 18 for 8086_9d2f IN ANY CASE (even if with "port-count" 15, all 8 ports show up in IOReg XHC? With port-count 14 one SS02 went missing)?

baohiep (hieplpvip) in his ASUS Zenbook SSDT-UIAC-UX430-KABYR.dsl is using 22 for port-count under 8086_9d2f, why ever.

I am not understanding clearly yet where I see the maximum port address (as specified by 'port') - I guess in IOreg under XHC? It seems I need to find out that value to set what's most recommended - 15 (my current), 18 (SSDT-UIAC-ALL.dsl default), or 22 (baohiep for Zenbook UX430 Kaby Lake R).
 
Last edited:
bugsb said:
sigh - OK. For my 8086_9d2f, should I in any case leave the "port-count" at SSDT-UIAC-ALL.dsl default setting of 18 for 8086_9d2f IN ANY CASE (even if with "port-count" 15, all 8 ports show up in IOReg XHC? With port.count 14 one SS02 went missing)?

baohiep (hieplpvip) in his ASUS Zenbook SSDT-UIAC-UX430-KABYR.dsl is using 22 for port-count under 8086_9d2f.

I am not understanding clearly yet which value is most recommended - 15 (my current), 18 (SSDT-UIAC-ALL.dsl default), 22 (baohiep)
Click to expand...

I cannot make any comments regarding specific configurations when you don't upload PR files that represent that scenario.

Bottom line: It is best to leave "port-count" as-is in SSDT-UIAC-ALL.dsl. If you read post #1 carefully, you will find there is no mention in the guide of changing it!
 
I had to replace my mobo, GA-X97MX Gaming 5 with a GA-X97X Gaming 7. I have updated my signature to reflect the change.

I am running the USB injection / detection sequence on this replacement Gaming -7 as I suspected there was a slight USB routing change between the -5 and the -7.

I have removed, temporarily for injection testing, SSDT-UIAC.asl from patched folder, i have added
-uia_ignore_rmcf
to my boot options, I believe I have disabled all the port limiting Clover KERNEL patches, BUT>>>
I can't get the SSP2 through SSP6 to appear in the LEFT pane of the IOREG app. It looks like this:
Screen Shot 2018-08-20 at 9.25.21 PM.png

Notice the ports in right hand pane go to SSP6 but in left go only to SSP1.

So I can't map the USB3 ports using my USB3 hub. What have i done wrong? I have also attached the full debug download with an IOREG dump etc.

Thanks in advance.
 

Attachments

  • debug_10949.zip
    2 MB · Views: 90
renderingrocks said:
Thank you RehabMan for you response and patience for helping myself and so many. Sorry for such basic questions, I appreciate all you do. Too bad there wasn't a way to automate some of this process to free up your time. Im determined to get this!
Click to expand...

Thanks again Rehabman, I did it and it works! The usb 3 hub makes this so much easier. I did notice the red usb 3.1 port is on RP05@1C,4. Do we leave it alone? It does work as is. Im amazed how you master this stuff.
 
tecemac said:
I had to replace my mobo, GA-X97MX Gaming 5 with a GA-X97X Gaming 7. I have updated my signature to reflect the change.

I am running the USB injection / detection sequence on this replacement Gaming -7 as I suspected there was a slight USB routing change between the -5 and the -7.

I have removed, temporarily for injection testing, SSDT-UIAC.asl from patched folder, i have added
-uia_ignore_rmcf
to my boot options, I believe I have disabled all the port limiting Clover KERNEL patches, BUT>>>
I can't get the SSP2 through SSP6 to appear in the LEFT pane of the IOREG app. It looks like this:
View attachment 347218
Notice the ports in right hand pane go to SSP6 but in left go only to SSP1.

So I can't map the USB3 ports using my USB3 hub. What have i done wrong? I have also attached the full debug download with an IOREG dump etc.

Thanks in advance.
Click to expand...

You need to add the correct port limit patch to your config.plist.
Refer to config_patches.plist from the USBInjectAll repo.
 
RehabMan said:
You need to add the correct port limit patch to your config.plist.
Click to expand...

I am obviously misunderstanding something. I thought if I DISABLED, or REMOVED all the Clover port limit patches, OR use the the -uia_ignore_rmcf boot flag then I am effectively enabling all the available USB ports?

But I suppose this must mean I'm hitting the Apple limit of 16 (24?), that's why I don't see the SSPx ports?

So finally, please confirm that there exists a Clover patch that raises the limit to 24 (or X > 16), and I just have to find it?
 
tecemac said:
But I suppose this must mean I'm hitting the Apple limit of 16 (24?), that's why I don't see the SSPx ports?
Click to expand...

@RehabMan

OK I see that in IOREGs that the port count is set to 15 - i.e. limited. I have applied ALL combinations of the config_patches.plist from your repo. I can see the patches getting applied in the bootlog.txt file (attached).

But I can't figure out what is disabling the port limit patch, or why this is failing to raise to 24?
Can you help?

attached is my latest debug attempt.
 

Attachments

  • debug_27594.zip
    2.2 MB · Views: 103
@RehabMan - I'm hoping that maybe you can shine some light on this...

I'm in the preliminary stages of creating a custom SSDT for my Gigabyte GA-Z170X-UD3 Ultra Motherboard (to hopefully address sleep not functioning properly for me in 10.13.6) and so far, I have logged the locations of every physical port available on the board using a USB 3.0 hub I had lying around, per your guide:

USB 2.0/1.1 and USB 3.0 Ports

HS01 <01 00 00 00> - USB2 device on front panel USB3 (left)
HS02 <02 00 00 00> - USB2 device on front panel USB3 (right)
HS03 <03 00 00 00> - USB2 device on IO panel USB3 (bottom-left)
HS04 <04 00 00 00> - USB2 device on IO panel USB3 (bottom-right)
HS05 <05 00 00 00> - USB2 device on IO panel USB3 (top-left)
HS06 <06 00 00 00> - USB2 device on rear panel USB3 top-right
HS07 <07 00 00 00> - (unused/eliminate)
HS08 <08 00 00 00> - Motherboard USB2 header #1 (eliminate)
HS09 <09 00 00 00> - (unused/eliminate)
HS10 <0a 00 00 00> - (unused/eliminate)
HS11 <0b 00 00 00> - Motherboard USB2 header #2 (eliminate)
HS12 <0c 00 00 00> - (unused/eliminate)
HS13 <0d 00 00 00> - USB2/3 device on IO panel USB2 (right)
HS14 <0e 00 00 00> - USB2/3 device on IO panel USB2 (left)
SS01 <11 00 00 00> - USB3 device on front panel USB3 (left)
SS02 <12 00 00 00> - USB3 device on front panel USB3 (right)
SS03 <13 00 00 00> - USB3 device on IO panel USB3 (bottom-left)
SS04 <14 00 00 00> - USB3 device on IO panel USB3 (bottom-right)
SS05 <15 00 00 00> - USB3 device on rear panel USB3 (top-left)
SS06 <16 00 00 00> - USB3 device on rear panel USB3 (top-right)
SS07 <17 00 00 00> - (unused/eliminate)
SS08 <18 00 00 00> - (unused/eliminate)
SS09 <19 00 00 00> - (unused/eliminate)
SS10 <1a 00 00 00> - (unused/eliminate)
USR1 <0f 00 00 00> - (unused/eliminate)
USR2 <10 00 00 00> - (unused/eliminate)

Total Ports Injected: 26
Trimmed Target: 14​


USB 3.1 (Type-A) and USB 3.1/Thunderbolt 3 (Type-C) Ports

According to Gigabyte, these 2 ports are supplied by the onboard Alpine Ridge controller and not the Z170 chipset. Both ports appear to be attached at pci-bridge@2, under a device ID defined as pci8086, 15b6@0 in IOReg instead of being listed under XHC like the rest of the USB ports. Thus, I’m not exactly sure what I need to do with these two ports when constructing my custom SSDT, if anything.

AppleUSB20XHCIPort@00100000 <01 00 00 00> - USB2 device attached to Type-C port
AppleUSB20XHCIPort@00200000 <02 00 00 00> - USB2 device attached to Type-A port
AppleUSB30XHCIPort@00300000 <03 00 00 00> - USB3 device attached to Type-C port
AppleUSB30XHCIPort@00400000 <04 00 00 00> - USB3 device attached to Type-A port

Total Ports Injected: 4

**NOTE: I currently don't have a Thunderbolt 3 device to test with, so I'm not entirely certain whether a Thunderbolt device would assign a dedicated port or not. I may order an adapter to test things with a couple of my old TB2 dongles for FW800 and Ethernet that I have lying around.
​
If I do need to do something special for these, am I correct in assuming that because these ports are supplied by a separate controller that they're on their own 15-port limit?

My apologies in advance if you think I may have missed anything in your guide. This is my first attempt at a Hackintosh. Any pointers would be greatly appreciated. Thanks!
 
Nick's Hacktintosh
GA-Z170X-UD3 Ultra |  i7 6700K |  GeForce GTX 1070 FTW
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