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10.7.4 Sandy Bridge CPU Power Management Fix

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For those of you waiting for an updated flAKed Speedstepper program, from what I heard he's not going to update it. So there are only 3 alternatives:

1) Use a patched BIOS if available

2) Use an alternative tool, but it requires that Xcode be installed.

3) Use NullCPUPowerManagement.
 
@ MacMan : it's better to keep SSDT that one extracted and patched on it's own machine,or use the universal one you made? It's there any difference of any kind?
 
MacMan said:
For those of you waiting for an updated flAKed Speedstepper program, from what I heard he's not going to update it. So there are only 3 alternatives:

1) Use a patched BIOS if available

2) Use an alternative tool, but it requires that Xcode be installed.

3) Use NullCPUPowerManagement.

Well that sucks :p any word on how the Asus Z77 packed BIOS are coming along?
 
SSDT not working on ASUS P6H61-LE/CSM with 0805 patched BIOS. Still locked to x16.

To be more specific, I'm still getting the P-State stepper Error 18 on all 4 cores.
 
ok, I tryed some days ago to shift to 10.7.4. I had problems using the old fix. System became a bit unstable, and geekbench went down a bit (from 15000 to 13000, more or less).
I then decided to rollback to 10.7.3, waiting for a permanent fix. So today I:
1) upgraded to 10.7.4
2) installed ssdt.aml for overclocked i7

as a result, I get stuck at apple logo.
I checked my org.chameleon.boot.plist file and it is completely unchanged. Do I have to add some lines there regarding ssdt? do I have to remove GeneratePstates? I am a bit confused...
 
All good here - i7 2600K (stock speed) Z68-UD3H-B3 F10

P-States and C-States enabled.

Updated fakesmc.kext and M/Board kexts from MB 4.5.

Using Greggen's SSDT.

P-States 16/23/25/27/35/36/37

:D
 
Well crap.. Getting a panic w/ P-State Stepper error 18 at step 29 after using the latest mbeast w/ i5 ssdt (non-overclocked). Can only boot w/ rboot. Using an asus P8H61-M LE/CSM with i5 2500k. P and C states are in plist, dropssdt is not. Any thoughts?
 
@H8TR @MacMan

There is something different with Asus and MSI UEFI boards. H8TR and my extracted SSDT looks totally different. But I found something interesting:

Speedstepping is defined in the DSDT, not in the SSDT. That's different than on Gigabytes board.

The Scope (_PR) on Gigabytes boards defines the Processor:

Code:
 Scope (_PR)
    {
        Processor (CPU0, 0x00, 0x00000410, 0x06) {}
        Processor (CPU1, 0x01, 0x00000410, 0x06) {}
        Processor (CPU2, 0x02, 0x00000410, 0x06) {}
        Processor (CPU3, 0x03, 0x00000410, 0x06) {}
        Processor (CPU4, 0x04, 0x00000410, 0x06) {}
        Processor (CPU5, 0x05, 0x00000410, 0x06) {}
        Processor (CPU6, 0x06, 0x00000410, 0x06) {}
        Processor (CPU7, 0x07, 0x00000410, 0x06) {}
    }

On my board (MSI H67MA-E35) the Scope (_PR) is totally different as it defines three Arguments that are needed, when the CPUs will be defined in the SSDT(!)

It looks like this (DSDT, I already added missing P-States, normally there is one missing between two (200MHz steps)):

Code:
Scope (_PR)
    {
        OperationRegion (SSDT, SystemMemory, 0xBF60AC18, 0x038C)
        OperationRegion (CSDT, SystemMemory, 0xBF60BE18, 0x84)
        Name (NCST, 0x02)
        Name (NPSS, 0x0B)
        Name (HNDL, 0x80000000)
        Name (CHDL, 0x80000000)
        Name (TNLP, 0x04)
        Name (CINT, Zero)
        Name (PDCV, 0xFFFFFFFF)
        Name (APSS, Package (0x0B)
        {
            Package (0x06)
            {
                0x0CE5, 
                0x00017318, 
                0x0A, 
                0x0A, 
                0x2500, 
                0x2500
            }, 

            Package (0x06)
            {
                0x0CE4, 
                0x00017318, 
                0x0A, 
                0x0A, 
                0x2100, 
                0x2100
            }, 

            Package (0x06)
            {
                0x0C1C, 
                0x000153D8, 
                0x0A, 
                0x0A, 
                0x1F00, 
                0x1F00
            }, 

            Package (0x06)
            {
                0x0B54, 
                0x00013880, 
                0x0A, 
                0x0A, 
                0x1D00, 
                0x1D00
            }, 

            Package (0x06)
            {
                0x0A8C, 
                0x00011940, 
                0x0A, 
                0x0A, 
                0x1B00, 
                0x1B00
            }, 

            Package (0x06)
            {
                0x09C4, 
                0x000101D0, 
                0x0A, 
                0x0A, 
                0x1900, 
                0x1900
            }, 

            Package (0x06)
            {
                0x08FC, 
                0xE678, 
                0x0A, 
                0x0A, 
                0x1700, 
                0x1700
            }, 

            Package (0x06)
            {
                0x0834, 
                0xCF08, 
                0x0A, 
                0x0A, 
                0x1500, 
                0x1500
            }, 

            Package (0x06)
            {
                0x076C, 
                0xB798, 
                0x0A, 
                0x0A, 
                0x1300, 
                0x1300
            }, 

            Package (0x06)
            {
                0x06A4, 
                0xA028, 
                0x0A, 
                0x0A, 
                0x1100, 
                0x1100
            }, 

            Package (0x06)
            {
                0x0640, 
                0x9470, 
                0x0A, 
                0x0A, 
                0x1000, 
                0x1000
            }
        })
        Name (PTCI, Package (0x02)
        {
            ResourceTemplate ()
            {
                Register (SystemIO, 
                    0x04,               // Bit Width
                    0x01,               // Bit Offset
                    0x0000000000000410, // Address
                    ,)
            }, 

            ResourceTemplate ()
            {
                Register (SystemIO, 
                    0x04,               // Bit Width
                    0x01,               // Bit Offset
                    0x0000000000000410, // Address
                    ,)
            }
        })
        Name (\PSTE, Zero)
        Name (\TSTE, Zero)
        Name (TSSI, Package (0x01)
        {
            Package (0x05)
            {
                0x64, 
                0x03E8, 
                Zero, 
                Zero, 
                Zero
            }
        })
        Name (TSSM, Package (0x08)
        {
            Package (0x05)
            {
                0x64, 
                0x03E8, 
                Zero, 
                Zero, 
                Zero
            }, 

            Package (0x05)
            {
                0x58, 
                0x036B, 
                Zero, 
                0x1E, 
                Zero
            }, 

            Package (0x05)
            {
                0x4B, 
                0x02EE, 
                Zero, 
                0x1C, 
                Zero
            }, 

            Package (0x05)
            {
                0x3F, 
                0x0271, 
                Zero, 
                0x1A, 
                Zero
            }, 

            Package (0x05)
            {
                0x32, 
                0x01F4, 
                Zero, 
                0x18, 
                Zero
            }, 

            Package (0x05)
            {
                0x26, 
                0x0177, 
                Zero, 
                0x16, 
                Zero
            }, 

            Package (0x05)
            {
                0x19, 
                0xFA, 
                Zero, 
                0x14, 
                Zero
            }, 

            Package (0x05)
            {
                0x0D, 
                0x7D, 
                Zero, 
                0x12, 
                Zero
            }
        })
        Name (C1ST, Package (0x02)
        {
            One, 
            Package (0x04)
            {
                ResourceTemplate ()
                {
                    Register (FFixedHW, 
                        0x00,               // Bit Width
                        0x00,               // Bit Offset
                        0x0000000000000000, // Address
                        ,)
                }, 

                One, 
                One, 
                0x03E8
            }
        })
        Name (CMST, Package (0x03)
        {
            0x02, 
            Package (0x04)
            {
                ResourceTemplate ()
                {
                    Register (FFixedHW, 
                        0x00,               // Bit Width
                        0x00,               // Bit Offset
                        0x0000000000000000, // Address
                        ,)
                }, 

                One, 
                One, 
                0x03E8
            }, 

            Package (0x04)
            {
                ResourceTemplate ()
                {
                    Register (FFixedHW, 
                        0x01,               // Bit Width
                        0x02,               // Bit Offset
                        0x0000000000000020, // Address
                        0x03,               // Access Size
                        )
                }, 

                0x03, 
                0x68, 
                0x015E
            }
        })
        Name (CIST, Package (0x03)
        {
            0x02, 
            Package (0x04)
            {
                ResourceTemplate ()
                {
                    Register (FFixedHW, 
                        0x00,               // Bit Width
                        0x00,               // Bit Offset
                        0x0000000000000000, // Address
                        ,)
                }, 

                One, 
                One, 
                0x03E8
            }, 

            Package (0x04)
            {
                ResourceTemplate ()
                {
                    Register (SystemIO, 
                        0x08,               // Bit Width
                        0x00,               // Bit Offset
                        0x0000000000000415, // Address
                        ,)
                }, 

                0x03, 
                0x68, 
                0x015E
            }
        })
        Method (CST, 0, NotSerialized)
        {
            If (LNotEqual (And (PDCV, 0x0200), 0x0200))
            {
                If (LEqual (NCST, 0x02))
                {
                    Store (One, NCST)
                }
            }

            If (LEqual (NCST, Zero))
            {
                Return (C1ST)
            }

            If (LEqual (NCST, One))
            {
                Return (CIST)
            }

            If (LEqual (NCST, 0x02))
            {
                Return (CMST)
            }

            Return (C1ST)
        }

        Method (PDC, 1, NotSerialized)
        {
            CreateDWordField (Arg0, Zero, REVS)
            CreateDWordField (Arg0, 0x04, SIZE)
            Store (SizeOf (Arg0), Local0)
            Store (Subtract (Local0, 0x08), Local1)
            CreateField (Arg0, 0x40, Multiply (Local1, 0x08), TEMP)
            Name (STS0, Buffer (0x04)
            {
                0x00, 0x00, 0x00, 0x00
            })
            Concatenate (STS0, TEMP, Local2)
            OSC (Buffer (0x10)
                {
                    /* 0000 */    0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 0xBE, 0x47, 
                    /* 0008 */    0x9E, 0xBD, 0xD8, 0x70, 0x58, 0x71, 0x39, 0x53
                }, REVS, SIZE, Local2)
        }

        Method (OSC, 4, NotSerialized)
        {
            CreateDWordField (Arg3, Zero, STS)
            CreateDWordField (Arg3, 0x04, CAP)
            CreateDWordField (Arg0, Zero, IID0)
            CreateDWordField (Arg0, 0x04, IID1)
            CreateDWordField (Arg0, 0x08, IID2)
            CreateDWordField (Arg0, 0x0C, IID3)
            Name (UID0, Buffer (0x10)
            {
                /* 0000 */    0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 0xBE, 0x47, 
                /* 0008 */    0x9E, 0xBD, 0xD8, 0x70, 0x58, 0x71, 0x39, 0x53
            })
            CreateDWordField (UID0, Zero, EID0)
            CreateDWordField (UID0, 0x04, EID1)
            CreateDWordField (UID0, 0x08, EID2)
            CreateDWordField (UID0, 0x0C, EID3)
            If (LNot (LAnd (LAnd (LEqual (IID0, EID0), LEqual (IID1, EID1)), 
                LAnd (LEqual (IID2, EID2), LEqual (IID3, EID3)))))
            {
                Store (0x06, Index (STS, Zero))
                Return (Arg3)
            }

            And (PDCV, CAP, PDCV)
            If (LEqual (CINT, Zero))
            {
                Store (One, CINT)
                If (LEqual (And (PDCV, 0x09), 0x09))
                {
                    If (LNotEqual (NPSS, Zero))
                    {
                        Load (SSDT, HNDL)
                    }
                }

                If (LEqual (And (PDCV, 0x10), 0x10))
                {
                    If (LNotEqual (NCST, 0xFF))
                    {
                        Load (CSDT, CHDL)
                    }
                }
            }

            Return (Arg3)
        }
    }

The first two lines "OperationRegion (SSDT, SystemMemory, 0xBF60AC18, 0x038C)" and "OperationRegion (CSDT, SystemMemory, 0xBF60BE18, 0x84)" are pointing two the SSDT and a CSDT. I really do not know what this CSDT is and how to extract it.

If we look now into the SSDT, we will see that the Processor-Objects are created here and get the information from the DSDT.

Code:
Scope (\_PR)
    {
        Processor (P000, 0x01, 0x00000410, 0x06)
        {
            Method (_PDC, 1, NotSerialized)
            {
                \_PR.PDC (Arg0)
            }

            Method (_OSC, 4, NotSerialized)
            {
                Return (\_PR.OSC)
                Arg0
                Arg1
                Arg2
                Arg3
            }
        }

        Processor (P001, 0x02, 0x00000410, 0x06)
        {
            Method (_PDC, 1, NotSerialized)
            {
                \_PR.PDC (Arg0)
            }

            Method (_OSC, 4, NotSerialized)
            {
                Return (\_PR.OSC)
                Arg0
                Arg1
                Arg2
                Arg3
            }
        }

        Processor (P002, 0x03, 0x00000410, 0x06)
        {
            Method (_PDC, 1, NotSerialized)
            {
                \_PR.PDC (Arg0)
            }

            Method (_OSC, 4, NotSerialized)
            {
                Return (\_PR.OSC)
                Arg0
                Arg1
                Arg2
                Arg3
            }
        }

        Processor (P003, 0x04, 0x00000410, 0x06)
        {
            Method (_PDC, 1, NotSerialized)
            {
                \_PR.PDC (Arg0)
            }

            Method (_OSC, 4, NotSerialized)
            {
                Return (\_PR.OSC)
                Arg0
                Arg1
                Arg2
                Arg3
            }
        }
    }

This makes clear why H8TR and I cannot boot up, if we use DropSSDT. The kernel cannot recognize how many cores are there, I guess.

So, I didn't solve the problem yet. Although I added missing P-States, I'm still locked to the lowest P-State, also if I try your SSDT, but it is obvious why. :D

Maybe there is something wrong with my ideas, but maybe we find a solution together!

I will attach my DSDT and SSDT.

Greetings,

xxmacmanxx
 

Attachments

  • dsdt.aml
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  • acpi_ssdt.aml
    258 bytes · Views: 232
Here's my story.
I have i7 2600k, GA-Z68XP-UD3P mobo and MacPro3,1 smbios.
I tried to use my own edited SSDT and SSDT from MB. Both seem to work well. MSRDumper reports:
Code:
PStatesReached: 16 17 18 19 20 21 35 36 37 38
I would be happy but.. I noticed that in Cinebench my CPU points have dropped from ~7.39 in 10.7.3 to ~6.88 in 10.7.4. Unfortunately I can't remember what was the score in Geekbench but I believe it was bigger too (now it's ~13100 in 64-bit test).
Any thoughts?
Thanks : )
 
xxmacmanxx said:
@H8TR @MacMan

There is something different with Asus and MSI UEFI boards. H8TR and my extracted SSDT looks totally different. But I found something interesting:

Speedstepping is defined in the DSDT, not in the SSDT. That's different than on Gigabytes board.
I literally just (like 20 minutes ago) started to consider that as a possibility before I read your post. The DSDT I was using provided me sleep but when I decided to remove it on a whim, P-state stepper Error 18 was gone. Still locked to x16, but not error in sight. SSDT.aml was still in /Extra doing nothing as it always has.

The thing is, I'm not very technically inclined so I'm not 100% sure I'd be able to come up with a fix myself.

Scope PR from P6H61-LE/CSM
Code:
    Scope (_PR)
    {
        OperationRegion (SSDT, SystemMemory, 0xBF5D7C18, 0x038C)
        OperationRegion (CSDT, SystemMemory, 0xBF5D8E18, 0x84)
        Name (NCST, 0x02)
        Name (NPSS, 0x10)
        Name (HNDL, 0x80000000)
        Name (CHDL, 0x80000000)
        Name (TNLP, 0x04)
        Name (CINT, Zero)
        Name (PDCV, 0xFFFFFFFF)
        Name (APSS, Package (0x10)
        {
            Package (0x06)
            {
                0x0CE5, 
                0x0003E418, 
                0x0A, 
                0x0A, 
                0x2500, 
                0x2500
            }, 
            Package (0x06)
            {
                0x0CE4, 
                0x0003E418, 
                0x0A, 
                0x0A, 
                0x2400, 
                0x2400
            }, 
            Package (0x06)
            {
                0x0C80, 
                0x0003BD08, 
                0x0A, 
                0x0A, 
                0x2300, 
                0x2300
            }, 
            Package (0x06)
            {
                0x0C1C, 
                0x000395F8, 
                0x0A, 
                0x0A, 
                0x2200, 
                0x2200
            }, 
            Package (0x06)
            {
                0x0BB8, 
                0x000372D0, 
                0x0A, 
                0x0A, 
                0x2100, 
                0x2100
            }, 
            Package (0x06)
            {
                0x0B54, 
                0x00034FA8, 
                0x0A, 
                0x0A, 
                0x2000, 
                0x2000
            }, 
            Package (0x06)
            {
                0x0AF0, 
                0x00032C80, 
                0x0A, 
                0x0A, 
                0x1F00, 
                0x1F00
            }, 
            Package (0x06)
            {
                0x0A8C, 
                0x00030958, 
                0x0A, 
                0x0A, 
                0x1E00, 
                0x1E00
            }, 
            Package (0x06)
            {
                0x0A28, 
                0x0002E630, 
                0x0A, 
                0x0A, 
                0x1D00, 
                0x1D00
            }, 
            Package (0x06)
            {
                0x09C4, 
                0x0002C6F0, 
                0x0A, 
                0x0A, 
                0x1C00, 
                0x1C00
            }, 
            Package (0x06)
            {
                0x0960, 
                0x0002A3C8, 
                0x0A, 
                0x0A, 
                0x1B00, 
                0x1B00
            }, 
            Package (0x06)
            {
                0x08FC, 
                0x00028488, 
                0x0A, 
                0x0A, 
                0x1A00, 
                0x1A00
            }, 
            Package (0x06)
            {
                0x0898, 
                0x00026548, 
                0x0A, 
                0x0A, 
                0x1900, 
                0x1900
            }, 
            Package (0x06)
            {
                0x0834, 
                0x00024608, 
                0x0A, 
                0x0A, 
                0x1800, 
                0x1800
            }, 
            Package (0x06)
            {
                0x07D0, 
                0x000226C8, 
                0x0A, 
                0x0A, 
                0x1700, 
                0x1700
            }, 
            Package (0x06)
            {
                0x0640, 
                0x00016378, 
                0x0A, 
                0x0A, 
                0x1000, 
                0x1000
            }
        })
        Name (PTCI, Package (0x02)
        {
            ResourceTemplate ()
            {
                Register (SystemIO, 
                    0x04,               // Bit Width
                    0x01,               // Bit Offset
                    0x0000000000000410, // Address
                    ,)
            }, 
            ResourceTemplate ()
            {
                Register (SystemIO, 
                    0x04,               // Bit Width
                    0x01,               // Bit Offset
                    0x0000000000000410, // Address
                    ,)
            }
        })
        Name (\PSTE, Zero)
        Name (\TSTE, Zero)
        Name (TSSI, Package (0x01)
        {
            Package (0x05)
            {
                0x64, 
                0x03E8, 
                Zero, 
                Zero, 
                Zero
            }
        })
        Name (TSSM, Package (0x08)
        {
            Package (0x05)
            {
                0x64, 
                0x03E8, 
                Zero, 
                Zero, 
                Zero
            }, 
            Package (0x05)
            {
                0x58, 
                0x036B, 
                Zero, 
                0x1E, 
                Zero
            }, 
            Package (0x05)
            {
                0x4B, 
                0x02EE, 
                Zero, 
                0x1C, 
                Zero
            }, 
            Package (0x05)
            {
                0x3F, 
                0x0271, 
                Zero, 
                0x1A, 
                Zero
            }, 
            Package (0x05)
            {
                0x32, 
                0x01F4, 
                Zero, 
                0x18, 
                Zero
            }, 
            Package (0x05)
            {
                0x26, 
                0x0177, 
                Zero, 
                0x16, 
                Zero
            }, 
            Package (0x05)
            {
                0x19, 
                0xFA, 
                Zero, 
                0x14, 
                Zero
            }, 
            Package (0x05)
            {
                0x0D, 
                0x7D, 
                Zero, 
                0x12, 
                Zero
            }
        })
        Name (C1ST, Package (0x02)
        {
            One, 
            Package (0x04)
            {
                ResourceTemplate ()
                {
                    Register (FFixedHW, 
                        0x00,               // Bit Width
                        0x00,               // Bit Offset
                        0x0000000000000000, // Address
                        ,)
                }, 
                One, 
                One, 
                0x03E8
            }
        })
        Name (CMST, Package (0x04)
        {
            0x03, 
            Package (0x04)
            {
                ResourceTemplate ()
                {
                    Register (FFixedHW, 
                        0x00,               // Bit Width
                        0x00,               // Bit Offset
                        0x0000000000000000, // Address
                        ,)
                }, 
                One, 
                One, 
                0x03E8
            }, 
            Package (0x04)
            {
                ResourceTemplate ()
                {
                    Register (FFixedHW, 
                        0x01,               // Bit Width
                        0x02,               // Bit Offset
                        0x0000000000000010, // Address
                        0x03,               // Access Size
                        )
                }, 
                0x02, 
                0x50, 
                0x01F4
            }, 
            Package (0x04)
            {
                ResourceTemplate ()
                {
                    Register (FFixedHW, 
                        0x01,               // Bit Width
                        0x02,               // Bit Offset
                        0x0000000000000020, // Address
                        0x03,               // Access Size
                        )
                }, 
                0x03, 
                0x68, 
                0x015E
            }
        })
        Name (CIST, Package (0x04)
        {
            0x03, 
            Package (0x04)
            {
                ResourceTemplate ()
                {
                    Register (FFixedHW, 
                        0x00,               // Bit Width
                        0x00,               // Bit Offset
                        0x0000000000000000, // Address
                        ,)
                }, 
                One, 
                One, 
                0x03E8
            }, 
            Package (0x04)
            {
                ResourceTemplate ()
                {
                    Register (SystemIO, 
                        0x08,               // Bit Width
                        0x00,               // Bit Offset
                        0x0000000000000414, // Address
                        ,)
                }, 
                0x02, 
                0x50, 
                0x01F4
            }, 
            Package (0x04)
            {
                ResourceTemplate ()
                {
                    Register (SystemIO, 
                        0x08,               // Bit Width
                        0x00,               // Bit Offset
                        0x0000000000000415, // Address
                        ,)
                }, 
                0x03, 
                0x68, 
                0x015E
            }
        })
 
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