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Re: Possible fix for usb
Have you check out this:
5.19 Integrated USB 2.0 Rate Matching Hub 5.19.1 Overview
The PCH has integrated two USB 2.0 Rate Matching Hubs (RMH). One hub is connected to each of the EHCI controllers as shown in the figure below. The Hubs convert low and full-speed traffic into high-speed traffic. When the RMHs are enabled, they will appear to software like an external hub is connected to Port 0 of each EHCI controller. In addition, port 1 of each of the RMHs is muxed with Port 1 of the EHCI controllers and is able to bypass the RMH for use as the Debug Port.
The hub operates like any USB 2.0 Discrete Hub and will consume one tier of hubs allowed by the USB 2.0 Spec. section 4.1.1. A maximum of four additional non-root hubs can be supported on any of the PCH USB Ports. The RMH will report the following Vendor ID = 8087h and Product ID = 0020h.
Architecture
A hub consists of three components: the Hub Repeater, the Hub Controller, and the Transaction Translator.
1. The Hub Repeater is responsible for connectivity setup and tear-down. It also supports exception handling, such as bus fault detection and recovery and connect/ disconnect detect.
2. The Hub Controller provides the mechanism for host-to-hub communication. Hub- specific status and control commands permit the host to configure a hub and to monitor and control its individual downstream facing ports.
3. The Transaction Translator (TT) responds to high-speed split transactions and translates them to full-/low-speed transactions with full-/low-speed devices attached on downstream facing ports. There is 1 TT per RMH in the PCH.
See chapter 11 of the USB 2.0 Specification for more details on the architecture of the hubs.
From:
http://www.intel.com/Assets/PDF/datasheet/322169.pdf page 220
Have you check out this:
5.19 Integrated USB 2.0 Rate Matching Hub 5.19.1 Overview
The PCH has integrated two USB 2.0 Rate Matching Hubs (RMH). One hub is connected to each of the EHCI controllers as shown in the figure below. The Hubs convert low and full-speed traffic into high-speed traffic. When the RMHs are enabled, they will appear to software like an external hub is connected to Port 0 of each EHCI controller. In addition, port 1 of each of the RMHs is muxed with Port 1 of the EHCI controllers and is able to bypass the RMH for use as the Debug Port.
The hub operates like any USB 2.0 Discrete Hub and will consume one tier of hubs allowed by the USB 2.0 Spec. section 4.1.1. A maximum of four additional non-root hubs can be supported on any of the PCH USB Ports. The RMH will report the following Vendor ID = 8087h and Product ID = 0020h.
Architecture
A hub consists of three components: the Hub Repeater, the Hub Controller, and the Transaction Translator.
1. The Hub Repeater is responsible for connectivity setup and tear-down. It also supports exception handling, such as bus fault detection and recovery and connect/ disconnect detect.
2. The Hub Controller provides the mechanism for host-to-hub communication. Hub- specific status and control commands permit the host to configure a hub and to monitor and control its individual downstream facing ports.
3. The Transaction Translator (TT) responds to high-speed split transactions and translates them to full-/low-speed transactions with full-/low-speed devices attached on downstream facing ports. There is 1 TT per RMH in the PCH.
See chapter 11 of the USB 2.0 Specification for more details on the architecture of the hubs.
From:
http://www.intel.com/Assets/PDF/datasheet/322169.pdf page 220