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Lenovo Y510p USB Troubleshooting

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A quick question :

Attached are my ACPI tables (decompiled) extracted from linux. As you can see there's a "dynamic" folder inside. I don't need to include those in final patching set. But there's a SSDT2.dsl which i never included in final before. Do i need to include it? If no, then why?

Imp info: Also i use custom SSDT for CPU by using ssdtPRgen.sh.
 

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  • ACPI.zip
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intruder16 said:
A quick question :

Attached are my ACPI tables (decompiled) extracted from linux.
Click to expand...

No change in SystemMemory region addresses...

As you can see there's a "dynamic" folder inside. I don't need to include those in final patching set. But there's a SSDT2.dsl which i never included in final before. Do i need to include it? If no, then why?
Click to expand...

If you've been following along with the discussion on native CPU PM using OEM CPU PM SSDTs, then you'd include it. Dynamic tables should not be included. Note: No patch to PNOT in that case...

Imp info: Also i use custom SSDT for CPU by using ssdtPRgen.sh.
Click to expand...

Yes.
 
Sorry i was quite busy. I added the xhci debug code and the value i got is "0x3".

EDIT: to be specific:

Code: 
Mar 30 11:01:59 localhost kernel[0]: ACPIDebug: { "XSEL1:", 0x0, 0x0, 0x0, }
Mar 30 11:01:59 localhost kernel[0]: ACPIDebug: { "XSEL2:", 0x0, 0x0, }
Mar 30 11:01:59 localhost kernel[0]: ACPIDebug: { "XSEL3:", 0x3fff, 0xf, }
Mar 30 11:01:59 localhost kernel[0]: ACPIDebug: { "XSEL4: XHCI is", 0x3, }
 
intruder16 said:
Sorry i was quite busy. I added the xhci debug code and the value i got is "0x3".

EDIT: to be specific:

Code: 
Mar 30 11:01:59 localhost kernel[0]: ACPIDebug: { "XSEL1:", 0x0, 0x0, 0x0, }
Mar 30 11:01:59 localhost kernel[0]: ACPIDebug: { "XSEL2:", 0x0, 0x0, }
Mar 30 11:01:59 localhost kernel[0]: ACPIDebug: { "XSEL3:", 0x3fff, 0xf, }
Mar 30 11:01:59 localhost kernel[0]: ACPIDebug: { "XSEL4: XHCI is", 0x3, }
Click to expand...

So it should be falling into this case:
Code: 
                    If (LOr (LEqual (XHCI, 0x02), LEqual (XHCI, 0x03)))
                    {
                        Store (One, XUSB)
                        Store (One, XRST)
                        Store (Zero, Local0)
                        And (PR3, 0xFFFFFFC0, Local0)
                        Or (Local0, PR3M, PR3)
                        Store (Zero, Local0)
                        And (PR2, 0xFFFF8000, Local0)
                        Or (Local0, PR2M, PR2)
                    }

You should verify (by adding a debug trace to that code).
 
RehabMan said:
....You should verify (by adding a debug trace to that code).
Click to expand...
Yes
Code: 
                Else
                {
                    \rmdt.p2("XSEL4: XHCI2 is", XHCI)
                    If (LOr (LEqual (XHCI, 0x02), LEqual (XHCI, 0x03)))
                    {
                        Store (One, XUSB)
                        Store (One, XRST)
                        Store (Zero, Local0)
                        And (PR3, 0xFFFFFFC0, Local0)
                        Or (Local0, PR3M, PR3)
                        If (LEqual (GP70, One))
                        {
                            And (PR3, 0x0E, PR3)
                        }
                        Else
                        {
                            And (PR3, 0x0A, PR3)
                        }

                        Store (Zero, Local0)
                        And (PR2, 0xFFFF8000, Local0)
                        Or (Local0, PR2M, PR2)
                    }
                }

it gives
Code: 
Mar 30 20:05:34 localhost kernel[0]: ACPIDebug: { "XSEL4: XHCI2 is", 0x3, }
DSDT attached just in case.

EDIT:

This is the 8-series data sheet https://www-ssl.intel.com/content/d...datasheets/8-series-chipset-pch-datasheet.pdf, right? I don't understand a single thing :D I jumped to chapter 16, still nothing :D
 

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  • DSDT.dsl.zip
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Now you have more investigation to do. That section of code is a bit different than my u430 (although my u430 is not taking that code path).

You have this:
Code: 
                        Store (One, XUSB)
                        Store (One, XRST)
                        Store (Zero, Local0)
                        And (PR3, 0xFFFFFFC0, Local0)
                        Or (Local0, PR3M, PR3)
                        If (LEqual (GP70, One))
                        {
                            And (PR3, 0x0E, PR3)
                        }
                        Else
                        {
                            And (PR3, 0x0A, PR3)
                        }

                        Store (Zero, Local0)
                        And (PR2, 0xFFFF8000, Local0)
                        Or (Local0, PR2M, PR2)


Simplified (removing dead stores):
Code: 
                        Store (One, XUSB)
                        Store (One, XRST)
                        And (PR3, 0xFFFFFFC0, Local0)
                        Or (Local0, PR3M, PR3)
                        If (LEqual (GP70, One))
                        {
                            And (PR3, 0x0E, PR3)
                        }
                        Else
                        {
                            And (PR3, 0x0A, PR3)
                        }

                        And (PR2, 0xFFFF8000, Local0)
                        Or (Local0, PR2M, PR2)

Maybe it is aborting somewhere in there and never reaching the part that stores PR2M to PR2 (the last line). That's the code that will setup for USB2 pass through.

If GP70 isn't reachable (eg. perhaps you dropped an SSDT that contains its definition), then that's what would happen (if that was the case, would also cause other problems...)
 
RehabMan said:
...If GP70 isn't reachable (eg. perhaps you dropped an SSDT that contains its definition), then that's what would happen (if that was the case, would also cause other problems...)
Click to expand...

No sign of GP70 in any tables except DSDT.
 
intruder16 said:
...
EDIT:

This is the 8-series data sheet https://www-ssl.intel.com/content/d...datasheets/8-series-chipset-pch-datasheet.pdf, right? I don't understand a single thing :D I jumped to chapter 16, still nothing :D
Click to expand...

The port routing from XHC->EHC is in section 16.1.36 page 593. Register XUSB2PR. It is a 32-bit register at offset 0xD0 in PCI_Config. Next page has the details for XUSB2PRM. The XUSB2PRM is supposed to be initialized in BIOS and essentially contains a value that can be used to initialize XUSB2PR with (it describes the XHC ports which "can be" routed to EHC).

If you look at the offsets of PR2 and PR2M in your DSDT, you'll see they correspond exactly...

Code: 
            OperationRegion (XPRT, PCI_Config, Zero, 0x0100)
            Field (XPRT, AnyAcc, NoLock, Preserve)
            {
...
                        Offset (0xD0), 
                PR2,    32, 
                PR2M,   32, 
                PR3,    32, 
                PR3M,   32
            }
 
Ok. I'm reading that, but i'm not sure exactly what we are trying to accomplish here. Do we not want 2.0 ports to route through xhc?

EDIT: I also have a setting in BIOS "Always on USB" which works on usb 2.0. It keeps usb 2.0 powered on even if laptop's powered off (shutdown).

This setting may have a bigger impact in PRM2 value. I'll try setting "Always on USB" to both "Enabled" and "Disabled". Then see if there's any change.
FYI its currently set to "Disabled".
 
intruder16 said:
Ok. I'm reading that, but i'm not sure exactly what we are trying to accomplish here. Do we not want 2.0 ports to route through xhc?
Click to expand...

We want USB2 ports that are on XHC to be handled by EHC (eg. routed through EHC). PR2/XUSB2PR allows that on a port-by-port basis.
 
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