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i7 5700HQ Power management

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silverlaine

silverlaine

Joined
Feb 6, 2014
Messages
29
Motherboard
GS60 Ghost Pro
CPU
i7 5700HQ
Graphics
Intel HD 5600 + GTX 970m
Mac
  1. 0
Classic Mac
  1. 0
Mobile Phone
  1. 0
Hello,

I've got a problem with ssdtPRGen.sh script to generate SSDT. When I run it it says unknown processor model (mine is i7-5700HQ). So I'm trying it like this:

Code: 
./ssdtPRGen.sh -p 'i7-5700HQ' -f 2700 -turbo 3500 -c 3 -t 47 -l 8 -lfm 600

This is the output:

Code: 
verride value: (-p) processor model, now using: i7-5700HQ!
Override value: (-f) clock frequency, now using: 2700 MHz!
Override value: (-turbo) maximum (turbo) frequency, now using: 3500 MHz!
Override value: (-c) CPU type, now using: Broadwell!
Override value: (-t) maximum TDP, now using: 47 Watt!
Override value: (-l) number of logical processors, now using: 8!
Override value: (-lfm) low frequency mode, now using: 600!

System information: Mac OS X 10.11 (15A284)
Brandstring 'Intel(R) Core(TM) i7-5700HQ CPU @ 2.70GHz'

Error: Unknown processor model ...
       Visit http://ark.intel.com to gather the required data:
       Processor Number
       TDP
       Low Frequency Mode (use AppleIntelInfo.kext)
       Base Frequency
       Max Turbo Frequency
       Cores
       Threads
Aborting ...
Done.

Info about my cpu is here: http://ark.intel.com/products/87716/Intel-Core-i7-5700HQ-Processor-6M-Cache-up-to-3_50-GHz

Thanks for any help
 
silverlaine said:
Hello,

I've got a problem with ssdtPRGen.sh script to generate SSDT. When I run it it says unknown processor model (mine is i7-5700HQ). So I'm trying it like this:

Code: 
./ssdtPRGen.sh -p 'i7-5700HQ' -f 2700 -turbo 3500 -c 3 -t 47 -l 8 -lfm 600

This is the output:

Code: 
verride value: (-p) processor model, now using: i7-5700HQ!
Override value: (-f) clock frequency, now using: 2700 MHz!
Override value: (-turbo) maximum (turbo) frequency, now using: 3500 MHz!
Override value: (-c) CPU type, now using: Broadwell!
Override value: (-t) maximum TDP, now using: 47 Watt!
Override value: (-l) number of logical processors, now using: 8!
Override value: (-lfm) low frequency mode, now using: 600!

System information: Mac OS X 10.11 (15A284)
Brandstring 'Intel(R) Core(TM) i7-5700HQ CPU @ 2.70GHz'

Error: Unknown processor model ...
       Visit http://ark.intel.com to gather the required data:
       Processor Number
       TDP
       Low Frequency Mode (use AppleIntelInfo.kext)
       Base Frequency
       Max Turbo Frequency
       Cores
       Threads
Aborting ...
Done.

Info about my cpu is here: http://ark.intel.com/products/87716/Intel-Core-i7-5700HQ-Processor-6M-Cache-up-to-3_50-GHz

Thanks for any help
Click to expand...

Did you try the beta branch of ssdtPRgen.sh?

In order to use -p, you must specify a *recognized* CPU name.
 
RehabMan said:
Did you try the beta branch of ssdtPRgen.sh?

In order to use -p, you must specify a *recognized* CPU name.
Click to expand...

I added it to the Data/broadwell.cfg and it works, although it warns me about board id

Code: 
Warning: 'cpu-type' may be set improperly (0x0705 instead of 0x0905)

Error: board-id [Mac-3CBD00234E554E41] not supported by Broadwell – check SMBIOS data / use the -c option

Do you want to continue (y/n)? y

I entered "y" and it genereted it without warning or errors. Should I be concerned about the warning with board id?
 
silverlaine said:
I added it to the Data/broadwell.cfg and it works, although it warns me about board id

Code: 
Warning: 'cpu-type' may be set improperly (0x0705 instead of 0x0905)

Error: board-id [Mac-3CBD00234E554E41] not supported by Broadwell – check SMBIOS data / use the -c option

Do you want to continue (y/n)? y

I entered "y" and it genereted it without warning or errors. Should I be concerned about the warning with board id?
Click to expand...

I think it is telling you that you're not using a Broadwell SMBIOS.
 
RehabMan said:
I think it is telling you that you're not using a Broadwell SMBIOS.
Click to expand...

I switched to SMBIOS and it seemed to generate ssdt succesfully. However now I have different problem, I accidentally installed AppleIntelInfo kext, which I wasn't supposed to apparently and it's causing kernel panic, I can't even get to single user mode to remove it. I deleted it from the s/l/e in windows, and deleted the cache folder, but the kernel panic still remains, saying that the AppleIntelInfo kext is causing it.

Is there something else I should remove or do to get rid of the kext?
 
silverlaine said:
I switched to SMBIOS and it seemed to generate ssdt succesfully. However now I have different problem, I accidentally installed AppleIntelInfo kext, which I wasn't supposed to apparently and it's causing kernel panic, I can't even get to single user mode to remove it. I deleted it from the s/l/e in windows, and deleted the cache folder, but the kernel panic still remains, saying that the AppleIntelInfo kext is causing it.

Is there something else I should remove or do to get rid of the kext?
Click to expand...

Try safe mode. Otherwise, you can clean cache by running the OS X installer.

This is one of those kexts that should not be marked OSBundleRequired=Root. Hopefully it isn't...
 
RehabMan said:
Try safe mode. Otherwise, you can clean cache by running the OS X installer.

This is one of those kexts that should not be marked OSBundleRequired=Root. Hopefully it isn't...
Click to expand...

It's working again. I can't load the kext however, this is the output in terminal:

Code: 
➜  ~  sudo kextload AppleIntelInfo.kext
/Users/Thundercow/AppleIntelInfo.kext failed to load - (libkern/kext) authentication failure (file ownership/permissions); check the system/kernel logs for errors or try kextutil(8).

Code: 
➜  ~  sudo kextutil AppleIntelInfo.kext
Diagnostics for AppleIntelInfo.kext:
Authentication Failures:
    File owner/permissions are incorrect (must be root:wheel, nonwritable by group/other):
        AppleIntelInfo.kext
        Contents
        Info.plist
        MacOS
        AppleIntelInfo

Code Signing Failure: not code signed

Was I supposed to code sign it in xcode? It was set to "Dont't sign" in build settings
 
silverlaine said:
It's working again. I can't load the kext however, this is the output in terminal:

Code: 
➜  ~  sudo kextload AppleIntelInfo.kext
/Users/Thundercow/AppleIntelInfo.kext failed to load - (libkern/kext) authentication failure (file ownership/permissions); check the system/kernel logs for errors or try kextutil(8).

Code: 
➜  ~  sudo kextutil AppleIntelInfo.kext
Diagnostics for AppleIntelInfo.kext:
Authentication Failures:
    File owner/permissions are incorrect (must be root:wheel, nonwritable by group/other):
        AppleIntelInfo.kext
        Contents
        Info.plist
        MacOS
        AppleIntelInfo

Code Signing Failure: not code signed

Was I supposed to code sign it in xcode? It was set to "Dont't sign" in build settings
Click to expand...

Permissions are wrong for the kext.

Try this:
Code: 
sudo mkdir /kexts
sudo cp -R AppleIntelInfo.kext /kexts

Then try to kextload it from /kexts/AppleIntelInfo.kext.
 
Yes it worked :)

This is the output:

Code: 
➜  ~  sudo kextload /kexts/AppleIntelInfo.kext
➜  ~  sudo cat /tmp/AppleIntelInfo.dat

AppleIntelInfo.kext v1.2 Copyright © 2012-2015 Pike R. Alpha. All rights reserved

Settings:
------------------------------------
logMSRs............................: 1
logIGPU............................: 1
logIntelRegs.......................: 1
logCStates.........................: 1
logIPGStyle........................: 1
InitialTSC.........................: 0x35353a61542
MWAIT C-States.....................: 8480

Model Specific Regiters
------------------------------------
MSR_CORE_THREAD_COUNT......(0x35)  : 0x40008
MSR_PLATFORM_INFO..........(0xCE)  : 0x8083BF3011B00
MSR_PMG_CST_CONFIG_CONTROL.(0xE2)  : 0x1E008403
MSR_PMG_IO_CAPTURE_BASE....(0xE4)  : 0x11814
IA32_MPERF.................(0xE7)  : 0x6FB34AFCB7
IA32_APERF.................(0xE8)  : 0x5EC9D2D27C
MSR_FLEX_RATIO.............(0x194) : 0x40000
MSR_IA32_PERF_STATUS.......(0x198) : 0x1EEE00001B00
MSR_IA32_PERF_CONTROL......(0x199) : 0x1B00
IA32_CLOCK_MODULATION......(0x19A) : 0x0
IA32_THERM_STATUS..........(0x19C) : 0x883C0800
IA32_MISC_ENABLES..........(0x1A0) : 0x850089
MSR_MISC_PWR_MGMT..........(0x1AA) : 0x400001
MSR_TURBO_RATIO_LIMIT......(0x1AD) : 0x232323232323
IA32_ENERGY_PERF_BIAS......(0x1B0) : 0x5
MSR_POWER_CTL..............(0x1FC) : 0x4005F
MSR_RAPL_POWER_UNIT........(0x606) : 0xA0E03
MSR_PKG_POWER_LIMIT........(0x610) : 0x804281D600DD8178
MSR_PKG_ENERGY_STATUS......(0x611) : 0x8B35FD9
MSR_PKG_POWER_INFO.........(0x614) : 0x178
MSR_PP0_CURRENT_CONFIG.....(0x601) : 0x101414800002A8
MSR_PP0_POWER_LIMIT........(0x638) : 0x0
MSR_PP0_ENERGY_STATUS......(0x639) : 0x3818D8F
MSR_PP0_POLICY.............(0x63a) : 0x0
MSR_PKGC6_IRTL.............(0x60b) : 0x8873
MSR_PKGC7_IRTL.............(0x60c) : 0x8891
MSR_PKG_C2_RESIDENCY.......(0x60d) : 0x14CA40AF9C4
MSR_PKG_C3_RESIDENCY.......(0x3f8) : 0x123D605FB5E
MSR_PKG_C6_RESIDENCY.......(0x3f9) : 0x0
MSR_PKG_C7_RESIDENCY.......(0x3fa) : 0x0
IA32_TSC_DEADLINE..........(0x6E0) : 0x35355BE60E3
PCH device.................: 0x8C4B8086

Intel Register Data
------------------------------------
CPU_VGACNTRL...............: 0xFF333333
IS_HASWELL(devid) || IS_BROADWELL(devid)
HSW_PWR_WELL_CTL1..........: 0xff000000
HSW_PWR_WELL_CTL2..........: 0xff333333
HSW_PWR_WELL_CTL3..........: 0xff333333
HSW_PWR_WELL_CTL4..........: 0xff333333
HSW_PWR_WELL_CTL5..........: 0xff000000
HSW_PWR_WELL_CTL6..........: 0xff333333
PIPE_DDI_FUNC_CTL_A........: 0xff333333 (enabled, port reserved, mode reserved, 12 bpc, +VSync, +HSync, EDP input reserved, x2)
PIPE_DDI_FUNC_CTL_B........: 0xff333333 (enabled, port reserved, mode reserved, 12 bpc, +VSync, +HSync, EDP input reserved, x2)
PIPE_DDI_FUNC_CTL_C........: 0xff000000 (enabled, port reserved, mode reserved, 8 bpc, -VSync, -HSync, EDP A ON, x1)
PIPE_DDI_FUNC_CTL_EDP......: 0xff333333 (enabled, port reserved, mode reserved, 12 bpc, +VSync, +HSync, EDP input reserved, x2)
DP_TP_CTL_A................: 0xff333333
DP_TP_CTL_B................: 0xff333333
DP_TP_CTL_C................: 0xff333333
DP_TP_CTL_D................: 0xff333333
DP_TP_CTL_E................: 0xff333333
DP_TP_STATUS_A.............: 0xff333333
DP_TP_STATUS_B.............: 0xff333333
DP_TP_STATUS_C.............: 0xff333333
DP_TP_STATUS_D.............: 0xff333333
DP_TP_STATUS_E.............: 0xff333333
DDI_BUF_CTL_A..............: 0xff333333 (enabled reversed x2 detected)
DDI_BUF_CTL_B..............: 0xff333333 (enabled reversed x2 detected)
DDI_BUF_CTL_C..............: 0xff333333 (enabled reversed x2 detected)
DDI_BUF_CTL_D..............: 0xff333333 (enabled reversed x2 detected)
DDI_BUF_CTL_E..............: 0xff333333 (enabled reversed x2 detected)
SPLL_CTL...................: 0xff333333
LCPLL_CTL..................: 0xff333333
WRPLL_CTL1.................: 0xff333333
WRPLL_CTL2.................: 0xff333333
PORT_CLK_SEL_A.............: 0xff333333 (None)
PORT_CLK_SEL_B.............: 0xff333333 (None)
PORT_CLK_SEL_C.............: 0xff333333 (None)
PORT_CLK_SEL_D.............: 0xff333333 (None)
PORT_CLK_SEL_E.............: 0xff333333 (None)
PIPE_CLK_SEL_A.............: 0xff333333 (Reserved)
PIPE_CLK_SEL_B.............: 0xff333333 (Reserved)
PIPE_CLK_SEL_C.............: 0xff333333 (Reserved)
SFUSE_STRAP................: 0xff333333 (display enabled, crt no, lane reversal yes, port b no, port c yes, port d yes)
PIPEASRC...................: 0xff333333 (65332, 13108)
DSPACNTR...................: 0xff333333 (enabled)
DSPASTRIDE.................: 0xff333333 (66899148)
DSPASURF...................: 0xff333333
DSPATILEOFF................: 0xff333333 (13107, 65331)
PIPEBSRC...................: 0xff333333 (65332, 13108)
DSPBCNTR...................: 0xff000000 (enabled)
DSPBSTRIDE.................: 0xff333333 (66899148)
DSPBSURF...................: 0xff333333
DSPBTILEOFF................: 0xff333333 (13107, 65331)
PIPECSRC...................: 0xff333333 (65332, 13108)
DSPCCNTR...................: 0xff000000 (enabled)
DSPCSTRIDE.................: 0xff333333 (66899148)
DSPCSURF...................: 0xff333333
DSPCTILEOFF................: 0xff333333 (13107, 65331)
PIPEACONF..................: 0xff333333 (enabled, active, pf-id, rotate 0, 10bpc)
HTOTAL_A...................: 0xff333333 (13108 active, 65332 total)
HBLANK_A...................: 0xff333333 (13108 start, 65332 end)
HSYNC_A....................: 0xff333333 (13108 start, 65332 end)
VTOTAL_A...................: 0xff333333 (13108 active, 65332 total)
VBLANK_A...................: 0xff333333 (13108 start, 65332 end)
VSYNC_A....................: 0xff333333 (13108 start, 65332 end)
VSYNCSHIFT_A...............: 0xff333333
PIPEA_DATA_M1..............: 0xff333333 (TU 128, val 0x333333 3355443)
PIPEA_DATA_N1..............: 0xff333333 (val 0x333333 3355443)
PIPEA_LINK_M1..............: 0xff333333 (val 0x333333 3355443)
PIPEA_LINK_N1..............: 0xff333333 (val 0x333333 3355443)
PIPEBCONF..................: 0xff333333 (enabled, active, pf-id, rotate 0, 10bpc)
HTOTAL_B...................: 0xff333333 (13108 active, 65332 total)
HBLANK_B...................: 0xff333333 (13108 start, 65332 end)
HSYNC_B....................: 0xff333333 (13108 start, 65332 end)
VTOTAL_B...................: 0xff333333 (13108 active, 65332 total)
VBLANK_B...................: 0xff333333 (13108 start, 65332 end)
VSYNC_B....................: 0xff333333 (13108 start, 65332 end)
VSYNCSHIFT_B...............: 0xff333333
PIPEB_DATA_M1..............: 0xff333333 (TU 128, val 0x333333 3355443)
PIPEB_DATA_N1..............: 0xff333333 (val 0x333333 3355443)
PIPEB_LINK_M1..............: 0xff333333 (val 0x333333 3355443)
PIPEB_LINK_N1..............: 0xff333333 (val 0x333333 3355443)
PIPECCONF..................: 0xff333333 (enabled, active, pf-id, rotate 0, 10bpc)
HTOTAL_C...................: 0xff000000 (1 active, 65281 total)
HBLANK_C...................: 0xff333333 (13108 start, 65332 end)
HSYNC_C....................: 0xff333333 (13108 start, 65332 end)
VTOTAL_C...................: 0xff333333 (13108 active, 65332 total)
VBLANK_C...................: 0xff000000 (1 start, 65281 end)
VSYNC_C....................: 0xff333333 (13108 start, 65332 end)
VSYNCSHIFT_C...............: 0xff333333
PIPEC_DATA_M1..............: 0xff000000 (TU 128, val 0x0 0)
PIPEC_DATA_N1..............: 0xff333333 (val 0x333333 3355443)
PIPEC_LINK_M1..............: 0xff000000 (val 0x0 0)
PIPEC_LINK_N1..............: 0xff333333 (val 0x333333 3355443)
PIPEEDPCONF................: 0xff333333 (enabled, active, pf-id, rotate 0, 10bpc)
HTOTAL_EDP.................: 0xff333333 (13108 active, 65332 total)
HBLANK_EDP.................: 0xff333333 (13108 start, 65332 end)
HSYNC_EDP..................: 0xff333333 (13108 start, 65332 end)
VTOTAL_EDP.................: 0xff333333 (13108 active, 65332 total)
VBLANK_EDP.................: 0xff333333 (13108 start, 65332 end)
VSYNC_EDP..................: 0xff333333 (13108 start, 65332 end)
VSYNCSHIFT_EDP.............: 0xff333333
PIPEEDP_DATA_M1............: 0xff333333 (TU 128, val 0x333333 3355443)
PIPEEDP_DATA_N1............: 0xff333333 (val 0x333333 3355443)
PIPEEDP_LINK_M1............: 0xff333333 (val 0x333333 3355443)
PIPEEDP_LINK_N1............: 0xff333333 (val 0x333333 3355443)
PFA_CTL_1..................: 0xff333333 (enable, auto_scale no, auto_scale_cal yes, v_filter bypass, vadapt enable, mode most, filter_sel edge_enhance,chroma pre-filter disable, vert3tap force, v_inter_invert field 0)
PFA_WIN_POS................: 0xff333333 (7987, 819)
PFA_WIN_SIZE...............: 0xff333333 (7987, 819)
PFB_CTL_1..................: 0xff333333 (enable, auto_scale no, auto_scale_cal yes, v_filter bypass, vadapt enable, mode most, filter_sel edge_enhance,chroma pre-filter disable, vert3tap force, v_inter_invert field 0)
PFB_WIN_POS................: 0xff333333 (7987, 819)
PFB_WIN_SIZE...............: 0xff333333 (7987, 819)
PFC_CTL_1..................: 0xff333333 (enable, auto_scale no, auto_scale_cal yes, v_filter bypass, vadapt enable, mode most, filter_sel edge_enhance,chroma pre-filter disable, vert3tap force, v_inter_invert field 0)
PFC_WIN_POS................: 0xff333333 (7987, 819)
PFC_WIN_SIZE...............: 0xff333333 (7987, 819)
TRANS_HTOTAL_A.............: 0xff333333 (13108 active, 65332 total)
TRANS_HBLANK_A.............: 0xff333333 (13108 start, 65332 end)
TRANS_HSYNC_A..............: 0xff333333 (13108 start, 65332 end)
TRANS_VTOTAL_A.............: 0xff333333 (13108 active, 65332 total)
TRANS_VBLANK_A.............: 0xff333333 (13108 start, 65332 end)
TRANS_VSYNC_A..............: 0xff333333 (13108 start, 65332 end)
TRANS_VSYNCSHIFT_A.........: 0xff333333
TRANSACONF.................: 0xff333333 (enable, active, rsvd)
FDI_RXA_MISC...............: 0xff333333 (FDI Delay 4915)
FDI_RXA_TUSIZE1............: 0xff333333
FDI_RXA_IIR................: 0xff333333
FDI_RXA_IMR................: 0xff333333
BLC_PWM_CPU_CTL2...........: 0xff333333 (enable 1, pipe EDP, blinking 1, granularity 8)
BLC_PWM_CPU_CTL............: 0xff333333 (cycle 13107, freq 65331)
BLC_PWM2_CPU_CTL2..........: 0xff333333 (enable 1, pipe EDP, blinking 1, granularity 8)
BLC_PWM2_CPU_CTL...........: 0xff333333 (cycle 13107, freq 65331)
BLC_MISC_CTL...............: 0xff333333 (PWM1-CPU PWM2-PCH)
BLC_PWM_PCH_CTL1...........: 0xff333333 (enable 1, override 1, inverted polarity 1)
BLC_PWM_PCH_CTL2...........: 0xff333333 (freq 65331, cycle 13107)
UTIL_PIN_CTL...............: 0xff333333 (enable 1, transcoder EDP, mode reserved, data 0 inverted polarity 0)
PCH_PP_STATUS..............: 0xff333333 (on, ready, sequencing unknown)
PCH_PP_CONTROL.............: 0xff333333 (blacklight disabled, power down on reset, panel on)
PCH_PP_ON_DELAYS...........: 0xff333333
PCH_PP_OFF_DELAYS..........: 0xff333333
PCH_PP_DIVISOR.............: 0xff333333
PIXCLK_GATE................: 0xff333333
SDEISR.....................: 0xff000000 (port d:0, port c:0, port b:0, crt:0)
RC6_RESIDENCY_TIME.........: 0xff333333

CPU Ratio Info:
------------------------------------
CPU Low Frequency Mode.............: 800 MHz
CPU Maximum non-Turbo Frequency....: 2700 MHz
CPU Maximum Turbo Frequency........: 3500 MHz

IGPU Info:
------------------------------------
IGPU Current Frequency.............:  300 MHz
IGPU Minimum Frequency.............:  300 MHz
IGPU Maximum Non-Turbo Frequency...:  300 MHz
IGPU Maximum Turbo Frequency.......: 1050 MHz
IGPU Maximum limit.................: No Limit

CPU P-States [ (13) 23 27 ] iGPU P-States [ (6) ]
CPU C3-Cores [ 0 1 4 5 6 ]
CPU C6-Cores [ 0 1 3 6 7 ]
CPU P-States [ (13) 15 23 27 ] iGPU P-States [ (6) ]
CPU C6-Cores [ 0 1 3 4 6 7 ]
CPU C6-Cores [ 0 1 3 4 5 6 7 ]
CPU C6-Cores [ 0 1 2 3 4 5 6 7 ]
CPU C3-Cores [ 0 1 2 3 4 5 6 ]
CPU P-States [ (13) 14 15 23 27 ] iGPU P-States [ (6) ]
CPU P-States [ (13) 14 15 23 25 27 ] iGPU P-States [ (6) ]
CPU C3-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ (13) 14 15 23 25 26 27 ] iGPU P-States [ (6) ]
CPU P-States [ (13) 14 15 21 23 25 26 27 ] iGPU P-States [ (6) ]
CPU P-States [ (13) 14 15 16 21 23 25 26 27 ] iGPU P-States [ (6) ]
CPU P-States [ (13) 14 15 16 17 21 23 25 26 27 ] iGPU P-States [ (6) ]
CPU P-States [ (13) 14 15 16 17 21 22 23 25 26 27 ] iGPU P-States [ (6) ]
CPU P-States [ 13 14 15 16 (17) 18 21 22 23 25 26 27 ] iGPU P-States [ (6) ]
CPU P-States [ 13 14 15 16 17 18 21 22 23 24 25 26 (27) ] iGPU P-States [ (6) ]
CPU P-States [ (13) 14 15 16 17 18 20 21 22 23 24 25 26 27 ] iGPU P-States [ (6) ]

Does the native power management work now? I can't tell :D
 
silverlaine said:
Yes it worked :)

This is the output:

Code: 
...
CPU P-States [ (13) 23 27 ] iGPU P-States [ (6) ]
CPU C3-Cores [ 0 1 4 5 6 ]
CPU C6-Cores [ 0 1 3 6 7 ]
CPU P-States [ (13) 15 23 27 ] iGPU P-States [ (6) ]
CPU C6-Cores [ 0 1 3 4 6 7 ]
CPU C6-Cores [ 0 1 3 4 5 6 7 ]
CPU C6-Cores [ 0 1 2 3 4 5 6 7 ]
CPU C3-Cores [ 0 1 2 3 4 5 6 ]
CPU P-States [ (13) 14 15 23 27 ] iGPU P-States [ (6) ]
CPU P-States [ (13) 14 15 23 25 27 ] iGPU P-States [ (6) ]
CPU C3-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ (13) 14 15 23 25 26 27 ] iGPU P-States [ (6) ]
CPU P-States [ (13) 14 15 21 23 25 26 27 ] iGPU P-States [ (6) ]
CPU P-States [ (13) 14 15 16 21 23 25 26 27 ] iGPU P-States [ (6) ]
CPU P-States [ (13) 14 15 16 17 21 23 25 26 27 ] iGPU P-States [ (6) ]
CPU P-States [ (13) 14 15 16 17 21 22 23 25 26 27 ] iGPU P-States [ (6) ]
CPU P-States [ 13 14 15 16 (17) 18 21 22 23 25 26 27 ] iGPU P-States [ (6) ]
CPU P-States [ 13 14 15 16 17 18 21 22 23 24 25 26 (27) ] iGPU P-States [ (6) ]
CPU P-States [ (13) 14 15 16 17 18 20 21 22 23 24 25 26 27 ] iGPU P-States [ (6) ]

Does the native power management work now? I can't tell :D
Click to expand...

CPU PM working (assuming verification of X86PlatformPlugin in ioreg). IGPU probably not.
 
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