Enable SpeedStep Core-i7 860

Musicalchairs · Feb 8, 2010

Having a little trouble trying to figure out where I should put this code within my exisiting DSDT.

Easy enough to find the CPU section of my current UD6 DSDT from Tony's archive.
Just dont know where it ends.

Any help would be greatly appreciated

tonymacx86 · Feb 8, 2010

In this example, the i7 860 SpeedStep has not been applied.

Code:

DefinitionBlock ("./dsdt.aml", "DSDT", 1, "GBT   ", "GBTUACPI", 0x00001000)
{
    Scope (_PR)
    {
        Processor (CPU0, 0x00, 0x00000410, 0x06) {}
        Processor (CPU1, 0x01, 0x00000410, 0x06) {}
        Processor (CPU2, 0x02, 0x00000410, 0x06) {}
        Processor (CPU3, 0x03, 0x00000410, 0x06) {}
        Processor (CPU4, 0x04, 0x00000410, 0x06) {}
        Processor (CPU5, 0x05, 0x00000410, 0x06) {}
        Processor (CPU6, 0x06, 0x00000410, 0x06) {}
        Processor (CPU7, 0x07, 0x00000410, 0x06) {}
    }

    Name (_S0, Package (0x04)
    {
        Zero, 
        Zero, 
        Zero, 
        Zero
    })

In this example, the i7 860 SpeedStep has been applied.

Code:

DefinitionBlock ("./dsdt.aml", "DSDT", 1, "GBT   ", "GBTUACPI", 0x00001000)
{
    Scope (_PR)
    {
        Processor (CPU0, 0x00, 0x00000410, 0x06) {}
        Processor (CPU1, 0x01, 0x00000410, 0x06) {}
        Processor (CPU2, 0x02, 0x00000410, 0x06) {}
        Processor (CPU3, 0x03, 0x00000410, 0x06) {}
        Processor (CPU4, 0x04, 0x00000410, 0x06) {}
        Processor (CPU5, 0x05, 0x00000410, 0x06) {}
        Processor (CPU6, 0x06, 0x00000410, 0x06) {}
        Processor (CPU7, 0x07, 0x00000410, 0x06) {}
    }

    Scope (_PR.CPU0)  // HERE IS WHERE THE CODE BEGINS
    {
        Method (_PSS, 0, NotSerialized)
        {
            Return (Package (0x0E)
            {
                Package (0x06)
                {
                    0x0AEA, 
                    0x00017318, 
                    0x0A, 
                    0x0A, 
                    0x16, 
                    0x16
                }, 

                Package (0x06)
                {
                    0x0AE9, 
                    0x00017318, 
                    0x0A, 
                    0x0A, 
                    0x15, 
                    0x15
                }, 

                Package (0x06)
                {
                    0x0A64, 
                    0x000130B0, 
                    0x0A, 
                    0x0A, 
                    0x14, 
                    0x14
                }, 

                Package (0x06)
                {
                    0x09DF, 
                    0x00011170, 
                    0x0A, 
                    0x0A, 
                    0x13, 
                    0x13
                }, 

                Package (0x06)
                {
                    0x095A, 
                    0xDEA8, 
                    0x0A, 
                    0x0A, 
                    0x12, 
                    0x12
                }, 

                Package (0x06)
                {
                    0x08D5, 
                    0xC738, 
                    0x0A, 
                    0x0A, 
                    0x11, 
                    0x11
                }, 

                Package (0x06)
                {
                    0x0850, 
                    0xA028, 
                    0x0A, 
                    0x0A, 
                    0x10, 
                    0x10
                }, 

                Package (0x06)
                {
                    0x07CB, 
                    0x8CA0, 
                    0x0A, 
                    0x0A, 
                    0x0F, 
                    0x0F
                }, 

                Package (0x06)
                {
                    0x0746, 
                    0x7D00, 
                    0x0A, 
                    0x0A, 
                    0x0E, 
                    0x0E
                }, 

                Package (0x06)
                {
                    0x06C1, 
                    0x61A8, 
                    0x0A, 
                    0x0A, 
                    0x0D, 
                    0x0D
                }, 

                Package (0x06)
                {
                    0x063C, 
                    0x55F0, 
                    0x0A, 
                    0x0A, 
                    0x0C, 
                    0x0C
                }, 

                Package (0x06)
                {
                    0x05B7, 
                    0x4268, 
                    0x0A, 
                    0x0A, 
                    0x0B, 
                    0x0B
                }, 

                Package (0x06)
                {
                    0x0532, 
                    0x3A98, 
                    0x0A, 
                    0x0A, 
                    0x0A, 
                    0x0A
                }, 

                Package (0x06)
                {
                    0x04AD, 
                    0x2AF8, 
                    0x0A, 
                    0x0A, 
                    0x09, 
                    0x09
                }
            })
        }

        Method (_PSD, 0, NotSerialized)
        {
            Return (Package (0x05)
            {
                0x05, 
                Zero, 
                Zero, 
                0xFC, 
                0x04
            })
        }

        Method (_CST, 0, NotSerialized)
        {
            Return (Package (0x02)
            {
                One, 
                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000000, // Address
                            0x01,               // Access Size
                            )
                    }, 

                    One, 
                    0x9D, 
                    0x03E8
                }
            })
        }
    }

    Scope (_PR.CPU1)
    {
        Method (_PSS, 0, NotSerialized)
        {
            Return (^^CPU0._PSS ())
        }

        Method (_PSD, 0, NotSerialized)
        {
            Return (^^CPU0._PSD ())
        }

        Method (_CST, 0, NotSerialized)
        {
            Return (Package (0x04)
            {
                0x03, 
                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000000, // Address
                            ,)
                    }, 

                    One, 
                    Zero, 
                    0x03E8
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x08,               // Bit Width
                            0x00,               // Bit Offset
                            0x0000000000000414, // Address
                            ,)
                    }, 

                    0x02, 
                    One, 
                    0x01F4
                }, 

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW, 
                            0x08,               // Bit Width
                            0x00,               // Bit Offset
                            0x0000000000000415, // Address
                            ,)
                    }, 

                    0x03, 
                    0x55, 
                    0xFA
                }
            })
        }
    }

    Scope (_PR.CPU2)
    {
        Method (_PSS, 0, NotSerialized)
        {
            Return (^^CPU0._PSS ())
        }

        Method (_PSD, 0, NotSerialized)
        {
            Return (^^CPU0._PSD ())
        }

        Method (_CST, 0, NotSerialized)
        {
            Return (^^CPU1._CST ())
        }
    }

    Scope (_PR.CPU3)
    {
        Method (_PSS, 0, NotSerialized)
        {
            Return (^^CPU0._PSS ())
        }

        Method (_PSD, 0, NotSerialized)
        {
            Return (^^CPU0._PSD ())
        }

        Method (_CST, 0, NotSerialized)
        {
            Return (^^CPU1._CST ())
        }
    }

    Scope (_PR.CPU4)
    {
        Method (_PSS, 0, NotSerialized)
        {
            Return (^^CPU0._PSS ())
        }

        Method (_PSD, 0, NotSerialized)
        {
            Return (^^CPU0._PSD ())
        }

        Method (_CST, 0, NotSerialized)
        {
            Return (^^CPU1._CST ())
        }
    }

    Scope (_PR.CPU5)
    {
        Method (_PSS, 0, NotSerialized)
        {
            Return (^^CPU0._PSS ())
        }

        Method (_PSD, 0, NotSerialized)
        {
            Return (^^CPU0._PSD ())
        }

        Method (_CST, 0, NotSerialized)
        {
            Return (^^CPU1._CST ())
        }
    }

    Scope (_PR.CPU6)
    {
        Method (_PSS, 0, NotSerialized)
        {
            Return (^^CPU0._PSS ())
        }

        Method (_PSD, 0, NotSerialized)
        {
            Return (^^CPU0._PSD ())
        }

        Method (_CST, 0, NotSerialized)
        {
            Return (^^CPU1._CST ())
        }
    }

    Scope (_PR.CPU7)
    {
        Method (_PSS, 0, NotSerialized)
        {
            Return (^^CPU0._PSS ())
        }

        Method (_PSD, 0, NotSerialized)
        {
            Return (^^CPU0._PSD ())
        }

        Method (_CST, 0, NotSerialized)
        {
            Return (^^CPU1._CST ())
        }
    } // HERE IS WHERE THE CODE ENDS

    Name (_S0, Package (0x04)
    {
        Zero, 
        Zero, 
        Zero, 
        Zero
    })

It's really as simple as inserting the code between the first block

Code:

DefinitionBlock ("./dsdt.aml", "DSDT", 1, "GBT   ", "GBTUACPI", 0x00001000)
{
    Scope (_PR)
    {
        Processor (CPU0, 0x00, 0x00000410, 0x06) {}
        Processor (CPU1, 0x01, 0x00000410, 0x06) {}
        Processor (CPU2, 0x02, 0x00000410, 0x06) {}
        Processor (CPU3, 0x03, 0x00000410, 0x06) {}
        Processor (CPU4, 0x04, 0x00000410, 0x06) {}
        Processor (CPU5, 0x05, 0x00000410, 0x06) {}
        Processor (CPU6, 0x06, 0x00000410, 0x06) {}
        Processor (CPU7, 0x07, 0x00000410, 0x06) {}
    }

And the Second Block:

Code:

    Name (_S0, Package (0x04)
    {
        Zero, 
        Zero, 
        Zero, 
        Zero
    })

Musicalchairs · Feb 8, 2010

Okay..

After typing that all out and getting 2 syntax errors.

Your reply came through and i realised i could have just copied from 1 to the other via two open windows of DSDTSE

iStat reports my CPU Temp is 59 celcius, so no reduction in temp.

in WIN7 it floats around 36 celcius with stock fan on cpu.

Is speed step supposed to reduce cpu temp?

UPDATE

Thanks again Tony. Once again you've made it easy for me.

My Geekbench score is 7733

Floating Point Processor floating point performance 12613
Memory Memory performance 3668
Stream Memory bandwidth performance 3961

Curious to know how i can get my CPU temp down though.

konsti · Jul 22, 2010

Dear tonymacx86 thanks for your speed-stepping guide. I would like to post my (alternative) method as used in my other mobo's DSDT (ICH7) for speed-step on the Q9550 processor, with your Core i7-860 values (on my P55M-UD4). But I do have some questions that I hope you can help me out.

First of all, here's my code (not much different than yours, just the syntax I guess):

Code:

Scope (\_PR)
{
    Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06)
    {
        Name (_PSS, Package (0x0E)
        {
         // Package {CoreFrequency, Power, TransitionLatency, BusMasterLatency, Control, Status}
            Package (0x06) {0x0AEA, 0x00017318, 0x0A, 0x0A, 0x16, 0x16},
            Package (0x06) {0x0AE9, 0x00017318, 0x0A, 0x0A, 0x15, 0x15},
            Package (0x06) {0x0A64, 0x000130B0, 0x0A, 0x0A, 0x14, 0x14},
            Package (0x06) {0x09DF, 0x00011170, 0x0A, 0x0A, 0x13, 0x13},
            Package (0x06) {0x095A, 0x0000DEA8, 0x0A, 0x0A, 0x12, 0x12},
            Package (0x06) {0x08D5, 0x0000C738, 0x0A, 0x0A, 0x11, 0x11},
            Package (0x06) {0x0850, 0x0000A028, 0x0A, 0x0A, 0x10, 0x10},
            Package (0x06) {0x07CB, 0x00008CA0, 0x0A, 0x0A, 0x0F, 0x0F},
            Package (0x06) {0x0746, 0x00007D00, 0x0A, 0x0A, 0x0E, 0x0E},
            Package (0x06) {0x06C1, 0x000061A8, 0x0A, 0x0A, 0x0D, 0x0D},
            Package (0x06) {0x063C, 0x000055F0, 0x0A, 0x0A, 0x0C, 0x0C},
            Package (0x06) {0x05B7, 0x00004268, 0x0A, 0x0A, 0x0B, 0x0B},
            Package (0x06) {0x0532, 0x00003A98, 0x0A, 0x0A, 0x0A, 0x0A},
            Package (0x06) {0x04AD, 0x00002AF8, 0x0A, 0x0A, 0x09, 0x09}
        })

        Name (_PSD, Package (0x05)
        {
            0x05, Zero, Zero, 0xFC, 0x04
        })

        Name (_CST, Package (0x02)
        {
            0x01,
            Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0x0000, 0x01, )}, 0x01, 0x9D, 0x03E8}
        })
    }

    Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06)
    {
        Alias (\_PR.CPU0._PSS, _PSS)
        Alias (\_PR.CPU0._PSD, _PSD)

        Name (_CST, Package (0x04)
        {
            0x03,
            Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0x0000, , )}, 0x01, 0x00, 0x03E8},
            Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x08, 0x00, 0x0414, , )}, 0x02, 0x01, 0x01F4},
            Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x08, 0x00, 0x0415, , )}, 0x03, 0x55, 0x00FA}
        })
    }

    Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06)
    {
        Alias (\_PR.CPU0._PSS, _PSS)
        Alias (\_PR.CPU0._PSD, _PSD)
        Alias (\_PR.CPU1._CST, _CST)
    }

    Processor (\_PR.CPU3, 0x03, 0x00000410, 0x06)
    {
        Alias (\_PR.CPU0._PSS, _PSS)
        Alias (\_PR.CPU0._PSD, _PSD)
        Alias (\_PR.CPU1._CST, _CST)
    }

    Processor (\_PR.CPU4, 0x04, 0x00000410, 0x06)
    {
        Alias (\_PR.CPU0._PSS, _PSS)
        Alias (\_PR.CPU0._PSD, _PSD)
        Alias (\_PR.CPU1._CST, _CST)
    }

    Processor (\_PR.CPU5, 0x05, 0x00000410, 0x06)
    {
        Alias (\_PR.CPU0._PSS, _PSS)
        Alias (\_PR.CPU0._PSD, _PSD)
        Alias (\_PR.CPU1._CST, _CST)
    }

    Processor (\_PR.CPU6, 0x06, 0x00000410, 0x06)
    {
        Alias (\_PR.CPU0._PSS, _PSS)
        Alias (\_PR.CPU0._PSD, _PSD)
        Alias (\_PR.CPU1._CST, _CST)
    }

    Processor (\_PR.CPU7, 0x07, 0x00000410, 0x06)
    {
        Alias (\_PR.CPU0._PSS, _PSS)
        Alias (\_PR.CPU0._PSD, _PSD)
        Alias (\_PR.CPU1._CST, _CST)
    }
}

First question: After reading many pages and many DSDT code over at InsanelyMac for my Q9550, could you please explain/expand as to why in CPU1 and _CST package, the second and third Registers are FFixedHW and not SystemIO as I've seen around? I mean, the code could be for CPU1:

Code:

Name (_CST, Package (0x04)
{
    0x03,
    Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0x0000, , )}, 0x01, 0x00, 0x03E8},
    Package (0x04) {ResourceTemplate () {Register (SystemIO, 0x08, 0x00, 0x0414, , )}, 0x02, 0x01, 0x01F4},
    Package (0x04) {ResourceTemplate () {Register (SystemIO, 0x08, 0x00, 0x0415, , )}, 0x03, 0x55, 0x00FA}
})

Any idea on differences in behaviour?

Second question: Does Core i7-860 only support 3 C-States, as declared in (_CST) of CPU1? I could not find any info on that... but judging from some guy over at InsanelyMac with a Core i7-920 he has 6 C-States in his DSDT!

Third question: After reading the code syntax for (_PSS) on the internet (probably ACPI Spec v4.0.pdf) the values should be:

// Package {CoreFrequency, Power, TransitionLatency, BusMasterLatency, Control, Status}

but I have seen many people skipping the Frequency and Power, only to insert Control and Status codes, like in my example below:

Code:

Name (_PSS, Package (0x06)
{
    Package (0x06) {Zero, Zero, 0x0A, 0x0A, 0x4824, 0x00},    // Q9550 P-State 1: 0x4824
    Package (0x06) {Zero, Zero, 0x0A, 0x0A, 0x0821, 0x01},    // Q9550 P-State 2: 0x821
    Package (0x06) {Zero, Zero, 0x0A, 0x0A, 0x471E, 0x02},    // Q9550 P-State 3: 0x471E
    Package (0x06) {Zero, Zero, 0x0A, 0x0A, 0x071B, 0x03},    // Q9550 P-State 4: 0x71B
    Package (0x06) {Zero, Zero, 0x0A, 0x0A, 0x4619, 0x04},    // Q9550 P-State 5: 0x4619
    Package (0x06) {Zero, Zero, 0x0A, 0x0A, 0x0616, 0x05}     // Q9550 P-State 6: 0x616
})

so that the system/board manages it better. Any idea if things are different for Core i7 processors? How come you have (sequential) inverted numbers in your code for Status? Most people start with the highest Status as 0x01...

Final question: I tried to install VoodooMonitor on my P55M-UD4 together with basic 10.6.4 system but it causes a KP, therefore I can't see the values reported for Status (_PSS). This is probably caused by the VoodooMonitor.kext and the Core i7 combination. This proggie helped me some time ago to get the Status values for the DSDT section (_PSS) for my Q9550. I see that the first two frequencies (converted to decimal, also accepted in DSDT) are close. How did you manage to get these values, mate? I am really curious :lol:

I apologize for the long post; I do hope we can collaborate for a more optimal DSDT code! Many many thanks in advance

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Enable SpeedStep Core-i7 860

Musicalchairs

tonymacx86

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konsti

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