- Joined
- Aug 16, 2011
- Messages
- 14
- Motherboard
- p8z68-vpro
- CPU
- i7 2600k
- Graphics
- GA 6870 OC
- Mac
- Classic Mac
- Mobile Phone
I'm using the ASUS p8z67-v-PRO motherboard running on a i7 2600k. I've got the cpu overclocked to 4.6ghz. So I installed the 4.2ghz overclocked ssdt and edited the SSDT file and compiled it.
The following is my SSDT, I followed the guide from Macman's blog and I don't believe I've made a mistake anywhere. I've added 4 states, 4300, 4400, 4500 and 4600. I've also added 1 to each of the control and statuses and added 4 to the Package(0x1F), which totals to 31 states.
However after restarting I'm still stuck at 16x.
Any help would be great!
The following is my SSDT, I followed the guide from Macman's blog and I don't believe I've made a mistake anywhere. I've added 4 states, 4300, 4400, 4500 and 4600. I've also added 1 to each of the control and statuses and added 4 to the Package(0x1F), which totals to 31 states.
However after restarting I'm still stuck at 16x.
Any help would be great!
Code:
DefinitionBlock ("SSDT.aml", "SSDT", 1, "APPLE ", "CpuPm", 0x00001000)
{
External (\_PR_.CPU7, DeviceObj)
External (\_PR_.CPU6, DeviceObj)
External (\_PR_.CPU5, DeviceObj)
External (\_PR_.CPU4, DeviceObj)
External (\_PR_.CPU3, DeviceObj)
External (\_PR_.CPU2, DeviceObj)
External (\_PR_.CPU1, DeviceObj)
External (\_PR_.CPU0, DeviceObj)
Scope (\_PR.CPU0)
{
Name (VERS, "4.2 GHz Maximum Clock SSDT based on Greggen\'s at tonymacx86.com 2012-05-16")
Name (APSN, 0x04)
Name (APSS, Package (0x1F)
{
Package (0x06)
{
0x11F8,
Zero,
0x0A,
0x0A,
0x2E00,
0x2E00
},
Package (0x06)
{
0x1194,
Zero,
0x0A,
0x0A,
0x2D00,
0x2D00
},
Package (0x06)
{
0x1130,
Zero,
0x0A,
0x0A,
0x2C00,
0x2C00
},
Package (0x06)
{
0x10CC,
Zero,
0x0A,
0x0A,
0x2B00,
0x2B00
},
Package (0x06)
{
0x1068,
Zero,
0x0A,
0x0A,
0x2A00,
0x2A00
},
Package (0x06)
{
0x1004,
Zero,
0x0A,
0x0A,
0x2900,
0x2900
},
Package (0x06)
{
0x0FA0,
Zero,
0x0A,
0x0A,
0x2800,
0x2800
},
Package (0x06)
{
0x0F3C,
Zero,
0x0A,
0x0A,
0x2700,
0x2700
},
Package (0x06)
{
0x0ED8,
Zero,
0x0A,
0x0A,
0x2600,
0x2600
},
Package (0x06)
{
0x0E74,
Zero,
0x0A,
0x0A,
0x2500,
0x2500
},
Package (0x06)
{
0x0E10,
Zero,
0x0A,
0x0A,
0x2400,
0x2400
},
Package (0x06)
{
0x0DAC,
Zero,
0x0A,
0x0A,
0x2300,
0x2300
},
Package (0x06)
{
0x0D48,
Zero,
0x0A,
0x0A,
0x2200,
0x2200
},
Package (0x06)
{
0x0CE4,
Zero,
0x0A,
0x0A,
0x2100,
0x2100
},
Package (0x06)
{
0x0C80,
Zero,
0x0A,
0x0A,
0x2000,
0x2000
},
Package (0x06)
{
0x0C1C,
Zero,
0x0A,
0x0A,
0x1F00,
0x1F00
},
Package (0x06)
{
0x0BB8,
Zero,
0x0A,
0x0A,
0x1E00,
0x1E00
},
Package (0x06)
{
0x0B54,
Zero,
0x0A,
0x0A,
0x1D00,
0x1D00
},
Package (0x06)
{
0x0AF0,
Zero,
0x0A,
0x0A,
0x1C00,
0x1C00
},
Package (0x06)
{
0x0A8C,
Zero,
0x0A,
0x0A,
0x1B00,
0x1B00
},
Package (0x06)
{
0x0A28,
Zero,
0x0A,
0x0A,
0x1A00,
0x1A00
},
Package (0x06)
{
0x09C4,
Zero,
0x0A,
0x0A,
0x1900,
0x1900
},
Package (0x06)
{
0x0960,
Zero,
0x0A,
0x0A,
0x1800,
0x1800
},
Package (0x06)
{
0x08FC,
Zero,
0x0A,
0x0A,
0x1700,
0x1700
},
Package (0x06)
{
0x0898,
Zero,
0x0A,
0x0A,
0x1600,
0x1600
},
Package (0x06)
{
0x0834,
Zero,
0x0A,
0x0A,
0x1500,
0x1500
},
Package (0x06)
{
0x07D0,
Zero,
0x0A,
0x0A,
0x1400,
0x1400
},
Package (0x06)
{
0x076C,
Zero,
0x0A,
0x0A,
0x1300,
0x1300
},
Package (0x06)
{
0x0708,
Zero,
0x0A,
0x0A,
0x1200,
0x1200
},
Package (0x06)
{
0x06A4,
Zero,
0x0A,
0x0A,
0x1100,
0x1100
},
Package (0x06)
{
0x0640,
Zero,
0x0A,
0x0A,
0x1000,
0x1000
}
})
Method (ACST, 0, NotSerialized)
{
Return (Package (0x06)
{
One,
0x04,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
One,
0x03,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x03, // Access Size
)
},
0x03,
0xCD,
0x01F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000020, // Address
0x03, // Access Size
)
},
0x06,
0xF5,
0x015E
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000030, // Address
0x03, // Access Size
)
},
0x07,
0xF5,
0xC8
}
})
}
}
Scope (\_PR.CPU1)
{
Method (APSS, 0, NotSerialized)
{
Return (\_PR.CPU0.APSS)
}
}
Scope (\_PR.CPU2)
{
Method (APSS, 0, NotSerialized)
{
Return (\_PR.CPU0.APSS)
}
}
Scope (\_PR.CPU3)
{
Method (APSS, 0, NotSerialized)
{
Return (\_PR.CPU0.APSS)
}
}
Scope (\_PR.CPU4)
{
Method (APSS, 0, NotSerialized)
{
Return (\_PR.CPU0.APSS)
}
}
Scope (\_PR.CPU5)
{
Method (APSS, 0, NotSerialized)
{
Return (\_PR.CPU0.APSS)
}
}
Scope (\_PR.CPU6)
{
Method (APSS, 0, NotSerialized)
{
Return (\_PR.CPU0.APSS)
}
}
Scope (\_PR.CPU7)
{
Method (APSS, 0, NotSerialized)
{
Return (\_PR.CPU0.APSS)
}
}
}
