SpeedStep and Power States

[IceBear]

Hi All, Can anybody explain help me understand why the 860 SpeedStep code has different power states for the CPU0 and CPU1 sections?

It is the same physical chip so surely the power states should be the same across all cores?

Thanks in advance.

IB

 

[thelostswede]

That's unlikely, as CPU 0 would be the last one to power down, but I really don't know enough about it.

 

[IceBear]

OK. Time for me to eat humble pie

Who knows what I was thinking when I posted this question... Turns out I was just reading the code wrong... The p-states are the same; it is the c-states which are different which makes complete sense.

Never-mind, I'll crawl back under the rock from which I came.