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Z690 Chipset and Alder Lake CPUs

CaseySJ

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Interesting.
I'm a Frontend developer, compiling Webpack (Javascript bundler) can consume 100% cpu usage for 1min or more.
Other than that, I don't have any other real 100% cpu demanding tasks
I'm really not sure, I do have a budget for the i9-12900k but I wonder if an 120mm AIO is enough
I would pick the i7-12700K in a heartbeat over the 19-12900K. Though I must say my i5-12600K is doing such a great job that I don't feel the need to upgrade.
 

CaseySJ

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If I use dmidecode -u command, on my laptop, I have :
View attachment 534745

Here, we have Core Count to 6, Core Enabled to 6 and Thread Count to 12

For Z690, we could try patching Core Count and Core Enabled to 8 (instead of current 10) and let Thread Count to 16
Do you mean patching the kernel? Or patching an ACPI table?
 
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@Elias64Fr

For the sake of thoroughness, here is the output from dmidecode:

Case 1: P + E only (no HT)

Result:

  • Core Count: 10
  • Core Enabled: 10
  • Thread Count: 10
Code:
Processor Information
    Socket Designation: U3E1
    Type: Central Processor
    Family: Core i5
    Manufacturer: Intel(R) Corporation
    ID: 72 06 09 00 FF FB EB BF
    Signature: Type 0, Family 6, Model 151, Stepping 2
    Flags:
        FPU (Floating-point unit on-chip)
        VME (Virtual mode extension)
        DE (Debugging extension)
        PSE (Page size extension)
        TSC (Time stamp counter)
        MSR (Model specific registers)
        PAE (Physical address extension)
        MCE (Machine check exception)
        CX8 (CMPXCHG8 instruction supported)
        APIC (On-chip APIC hardware supported)
        SEP (Fast system call)
        MTRR (Memory type range registers)
        PGE (Page global enable)
        MCA (Machine check architecture)
        CMOV (Conditional move instruction supported)
        PAT (Page attribute table)
        PSE-36 (36-bit page size extension)
        CLFSH (CLFLUSH instruction supported)
        DS (Debug store)
        ACPI (ACPI supported)
        MMX (MMX technology supported)
        FXSR (FXSAVE and FXSTOR instructions supported)
        SSE (Streaming SIMD extensions)
        SSE2 (Streaming SIMD extensions 2)
        SS (Self-snoop)
        HTT (Multi-threading)
        TM (Thermal monitor supported)
        PBE (Pending break enabled)
    Version: 12th Gen Intel(R) Core(TM) i5-12600K
    Voltage: 1.1 V
    External Clock: 100 MHz
    Max Speed: 3680 MHz
    Current Speed: 3680 MHz
    Status: Populated, Enabled
    Upgrade: Other
    L1 Cache Handle: 0x0080
    L2 Cache Handle: 0x0081
    L3 Cache Handle: 0x0082
    Serial Number: To Be Filled By O.E.M.
    Asset Tag: To Be Filled By O.E.M.
    Part Number: To Be Filled By O.E.M.
    Core Count: 10
    Core Enabled: 10
    Thread Count: 10
    Characteristics:
        64-bit capable
        Multi-Core
        Hardware Thread
        Execute Protection
        Enhanced Virtualization
        Power/Performance Control
Case 2: P + HT only (no E)

Result:

  • Core Count: 10
  • Core Enabled: 6
  • Thread Count: 12
Code:
Processor Information
    Socket Designation: U3E1
    Type: Central Processor
    Family: Core i5
    Manufacturer: Intel(R) Corporation
    ID: 72 06 09 00 FF FB EB BF
    Signature: Type 0, Family 6, Model 151, Stepping 2
    Flags:
        FPU (Floating-point unit on-chip)
        VME (Virtual mode extension)
        DE (Debugging extension)
        PSE (Page size extension)
        TSC (Time stamp counter)
        MSR (Model specific registers)
        PAE (Physical address extension)
        MCE (Machine check exception)
        CX8 (CMPXCHG8 instruction supported)
        APIC (On-chip APIC hardware supported)
        SEP (Fast system call)
        MTRR (Memory type range registers)
        PGE (Page global enable)
        MCA (Machine check architecture)
        CMOV (Conditional move instruction supported)
        PAT (Page attribute table)
        PSE-36 (36-bit page size extension)
        CLFSH (CLFLUSH instruction supported)
        DS (Debug store)
        ACPI (ACPI supported)
        MMX (MMX technology supported)
        FXSR (FXSAVE and FXSTOR instructions supported)
        SSE (Streaming SIMD extensions)
        SSE2 (Streaming SIMD extensions 2)
        SS (Self-snoop)
        HTT (Multi-threading)
        TM (Thermal monitor supported)
        PBE (Pending break enabled)
    Version: 12th Gen Intel(R) Core(TM) i5-12600K
    Voltage: 1.0 V
    External Clock: 100 MHz
    Max Speed: 3680 MHz
    Current Speed: 3680 MHz
    Status: Populated, Enabled
    Upgrade: Other
    L1 Cache Handle: 0x0080
    L2 Cache Handle: 0x0081
    L3 Cache Handle: 0x0082
    Serial Number: To Be Filled By O.E.M.
    Asset Tag: To Be Filled By O.E.M.
    Part Number: To Be Filled By O.E.M.
    Core Count: 10
    Core Enabled: 6
    Thread Count: 12
    Characteristics:
        64-bit capable
        Multi-Core
        Hardware Thread
        Execute Protection
        Enhanced Virtualization
        Power/Performance Control
Case 2 is very interesting:
  • Core Count: 10
  • Core Enabled: 6
  • Thread Count: 12
Even if E-cores are disabled, we still have Core Count to 10 (6P +4E) .. From full cores and HT, Core Enabled and Thread Count dropped by 4.

Core Enabled seem to be the key ?! We should find a mean to have :
  • Core Count: 10
  • Core Enabled: 8
  • Thread Count: 16
 

CaseySJ

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Case 2 is very interesting:
  • Core Count: 10
  • Core Enabled: 6
  • Thread Count: 12
Even if E-cores are disabled, we still have Core Count to 10 (6P +4E) .. From full cores and HT, Core Enabled and Thread Count dropped by 4.

Core Enabled seem to be the key ?! We should find a mean to have :
  • Core Count: 10
  • Core Enabled: 8
  • Thread Count: 16
Yes, I see what you mean:
  • With cores enabled = 8, thread count will be 16, and all 16 threads will be real.
  • After a little breakfast, I'll try to patch the kernel to set core_count = 8.
    • Q: Is core_count in cpu_thread.c referring to "cores enabled" or "total physical cores"?
C:
nLThreadsPerCore = thread_count / core_count = 16 / 10 = 1;
nLThreadsPerPackage = nLCoresPerPackage * nLThreadsPerCore = 10 * 1 = 10;
nCPUs = nPackages * nLThreadsPerPackage = 1 * 10 = 10;
If we patch kernel so that core_count = 8:
  • nLThreadsPerCore = 16 / 8 = 2
  • nLThreadsPerPackage = 8 * 2 = 16 (this assumes nLCoresPerPackage is dependent on core_count as well)
  • nCPUs = 1 * 16 = 16
 
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Do you mean patching the kernel? Or patching an ACPI table?
I thought about patching SMBIOS or ACPI ... But first we can try by a Kernel Patch :)

If you see my previous post, for answering your question, I think core_count refers to "cores enabled" from SMBIOS.
 
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Genuine MacBookPro15,1:
 

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Reinstall the system from Big Sur to Monterey tonight.
1. The SSDT-CPUR-Z690-12900-2S-8PHT-8E.aml was found in the running score test just now. The running branch automatically restarted and loaded ssdt-cpur-z690.aml in the configuration file. This test is OK, but the score is low, only 1343 and 8296
2. Using SSDT-CPUR-Z690-12900-2S-8PHT-8E.aml, test scores under Big Sur a few days ago, 1980 and 14649
 

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EFI folder v. 0.5

I have amended the standard OpenCore 0.7.5 EFI folder for Alder Lake with the feedback of the last days.
  • There are now two different EFIs: Debug-TXT and Release-GUI.
  • 'Debug' is a minimal folder, which is primarily intended to dump a SysReport for reference and adjustments. It has quirk XhciPortLimit enabled, for USB mapping under Catalina or Big Sur 11.2.3 and lower, and features the free version of memtest to validate a build. When it's done, switch to 'Release'.
  • 'Release' is the full folder, with GUI by default. It features UsbInjectAll for USB mapping with Big Sur 11.3. (If you have made a map with XhciPortLimit under an older OS, or mapped from Windows or Linux, just use this map and disable the USB quirk/kext.)
  • 'Release' has two sample.plist: One for iMacPro1,1 (simplest setup) and one for MacPro7,1. The latter uses RestrictEvents, CPUFriend and the frequency vectors from iMP1,1 (provided by @darthsian ) to match the performance of the former (as shown in benchmarks by @CaseySJ ).
  • To save some space, memtest is only present in 'Debug' and AppleALC is only present in 'Release'. Copy them around and activate the corresponding entries as you want.
  • Networking assumes Realtek 2,5 GbE by default. Amend as needed. There is a stub device-i225.plist with the Device Properties values as used by @CaseySJ and @Stork ; if your board has an i225V use either—but not both at the same time.
As with previous versions, pick the sample.plist which most suits you, add serial numbers and rename to config.plist. This should work for most Z690 boards. In BIOS, either disable E-cores (P-cores +HT) or disable Hyper-Threading (P+E cores, no HT). Happy hackintoshing!

Edit. Added missing attachment, and caveat:
I compile these folders without having an actual Alder Lake build to validate, so there could be errors. Please carefully check the settings and use ocvalidate on the final config.plist.
 

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