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X299 Big Sur Support

CaseySJ

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Now I have two problems to solve
1) Titan Ridge - a) I flashed the card with @CaseySJ "GC-TITAN-RIDGE-NVM23-Elias64Fr.bin" firmware. 2) I installed the TTR on slot2 3) I activated the related BIOS section 4) I edited the DROM and created the SSDT-TBOLT3.aml
Now seeing apple system info I have this situation
View attachment 486145

View attachment 486146

View attachment 486147

what did i do wrong? I attach my SSDT

2) when the monitor goes into standby, moving the mouse or digit something on the keyboard don't not wake the monitor until after several attempts ...
Is the GC-Titan Ridge attached to RP05? This can be checked by running IORegistryExplorer and scrolling the device tree until you get to RP05 (do not use the 'search' bar).

An alternative method is to run Hackintool and select the PCIe tab:
Screen Shot 2020-08-29 at 4.41.15 AM.png

The SSDT you posted assumes that the controller is on RP05, but if it's attached to a different PCI path, we'll need to modify the SSDT.
 
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Just to clarify: The problem you're reporting is the low link speed of 20 Gbps instead of 40 Gbps?
Yes, as a sign that something have to be adjusted ...
 
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@Loloflatsix It happened again ...
Schermata 2020-08-29 alle 15.47.04.png


and few minutes later:

Schermata 2020-08-29 alle 16.07.26.png
 
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Yes, as a sign that something have to be adjusted ...

Change the scope from PCI0 to PC00. Can you also upload the rest of your ssdts and order in config.plist?

@Loloflatsix can you make a note of this for OpenCore users? We don't do PCI0 to PC00 rename patch anymore and I've answered this question multiple times...
 
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IMPORTANT NOTE FOR OC (OpenCore) USERS :

Unlike Clover , on OC there is NO ACPI rename patch PCI0 --------> PC00

So basically the SSDTs assigned to PCI0 won't load and you should have issue or instability .

You must ensure that all your SSDT are correctly assigned to PC00 according to the ACPI path on IOReg :

Explanation :

With CLOVER :

Capture d’écran 2020-08-29 à 18.49.03.png



With OC :


Capture d’écran 2020-08-29 à 18.26.17.png


So all of these SSDTs must be with PC00 :

Capture d’écran 2020-08-29 à 18.40.09.png


Enjoy with OC :thumbup:
 
Last edited:
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Change the scope from PCI0 to PC00. Can you also upload the rest of your ssdts and order in config.plist?
@djlild7hina I changed to PC00 all PCI0 in my TB3 SSDT and now --> 40Gb It's ok. I attach the rest
 

Attachments

  • SSDT-EC-USBX.aml
    239 bytes · Views: 58
  • SSDT-PLUG.aml
    120 bytes · Views: 57
  • SSDT-RTC0.aml
    172 bytes · Views: 55
  • SSDT-SBUS-MCHC.aml
    264 bytes · Views: 61
  • config.plist
    27.3 KB · Views: 55
Joined
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I changed to PC00 all PCI0 in my TB3 SSDT and now --> 40Gb It's ok. I attach the rest
Good : maybe you can share a screen shot from your IOReg too ;)
 
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