- May 15, 2016
- GIGABYTE X470 Arous Gaming 7 WiFi
- Ryzen R9 3900X
- RX 480
This is the hardest part matching your system IOReg to the SSDT.You will probably need to modify the script to match your PCI bus. For example, when I run Hackintool or IORegistry, under PCI ->Display, I see something that looks like this:
03:00.0 1002:73af /PCI0@0/D0A0@1,1/D0A7@0/pci-bridge@0/display@0 = PciRoot(0x0)/Pci(0x1,0x1)/Pci(0x0,0x0)/Pci(0x0,0x0)/Pci(0x0,0x0)
Using this, I only had to change these two lines:
External (_SB_.PCI0.D0A0.D0A7, DeviceObj)
When I was done, IORegistry showed my display as:
I hope this helps, because I realize this stuff is cryptic.
AMD hacks need to edit it as well.
IOPP/GPP1/GFX0, or IOPP/GP07/GFX0 etc….
You need to use IOReg and Hackintool PCI tab or equivalent to find and replace the nomenclature and the Devices/Properties as well.