[SUCCESS] Gigabyte Designare Z390 (Thunderbolt 3) + i7-9700K + AMD RX 580

[CaseySJ]

Wouldn't it make more sense to look at the SSDT from the new Macpro7.1? @Elias64Fr

Apple has both TbtOnPch and TbtOnPci depending on the Mac model. We're specifically looking for TbtOnPch, so if either iMac19,1 or MacPro7,1 has this then we can examine and borrow from it. However, all of these SSDTs are also contained in the Apple firmware.bin files.

 

[Elias64Fr]

Wouldn't it make more sense to look at the SSDT from the new Macpro7.1? @Elias64Fr

Hi @S1lla,

Unfortunately, It (CRMW written data) seem to be same as iMac19,1 .. Titan ridge too !

Attached MacPro7,1 SSDT TBT:

 

[S1lla]

Where did you get this data from if it is not a secret?

 

[Elias64Fr]

Where did you get this data from if it is not a secret?

Somewhere on web .. during search ! I have save it immediately after but I agree that isn't sure source

 

[CaseySJ]

** Thunderbolt ROM Extracted Info **​

Some information extracted form the Designare Thunderbolt ROM.

• Active partition begins at offset 0x4000.
• Byte offset 0x0A from the beginning of active partition represents the firmware version.
• For us, it is 0x33 or decimal 51.
  
  
• Offset 0x0200 to 0x0600 from the beginning of active partition is the Thunderbolt DROM.
  
  

Thanks to @Elias64Fr we can decode the DROM bytes as follows:

These are the actual DROM bytes starting at offset 0x020F:
71000000 000000ED 00E04034 98016900 ED0008C0 01010881 80028000 00000882 90018000 00000883 80048001 00000884 90038001 00000585 50000005 86500000 02C70B88 20010064 00000000 00038980 058A5040 00058B50 40000B01 47494741 42595445 0011025A 33393020 44455349 474E4152 4500

What these bytes mean:

• 71 -- CRC (cyclic redundancy check)
• 00 00 00 00 00 00 ED 00 -- UID SwitchType3: ED000000000000
• E0 -- CRC
• 40 34 98 01 69 00 ED 00 -- To be defined
• 08 C0 01 01 -- To be defined
• 08 81 80 02 80 00 0000 -- TBPort1 DualLinkport2 HPMAddr0
• 08 82 90 01 80 00 0000 -- TBPort2 DualLinkport1 HPMAddr0
• 08 83 80 04 80 01 0000 -- TBPort3 DualLinkport4 HPMAddr1
• 08 84 90 03 80 01 0000 -- TBPort4 DualLinkport3 HPMAddr1
• 05 85 50 00 00 -- TBPort5 DisplayPort Adapter
• 05 86 50 00 00 -- TBPort6 DisplayPort Adapter
• 02 C7 -- TBSwitch7
• 0B 88 20 01 00 64 00 00 00 00 00 -- TBPort8 PCI Down Adapter DSB1
• 03 89 80 -- TBPort9 PCI Down Adapter DSB4
• 05 8A 50 40 00 -- TBPortA DisplayPort Adapter
• 05 8B 50 40 00 -- TBPortB DisplayPort Adapter
• 0B 01 47 49 47 41 42 59 54 45 00 -- The string "GIGABYTE"
• 11 02 5A 33 39 30 20 44 45 53 49 47 4E 41 52 45 00 -- The string "Z390 DESIGNARE"

 

[Elias64Fr]

But step too,
Now we have to find the firmware of an iMac with embedded TitanRidge like iMac19,1 to make diff like osy86 Method !

I can't find any Firmware version 33 for iMac19,1 from Mojave to Catalina. It seem that the last version is

Mac-AA95B1DDAB278B95-C0_6.90.0-C1_47.1-R0

It's the same file from Catalina 10.15.0 to Catalina 10.15.2 !

 

[CaseySJ]

I can't find any Firmware version 33 for iMac19,1 from Mojave to Catalina. It seem that the last version is

Mac-AA95B1DDAB278B95-C0_6.90.0-C1_47.1-R0

It's the same file from Catalina 10.15.0 to Catalina 10.15.2 !

Designare Z390 firmware version is 0x33 or decimal 51. So have a look at this!! Mac-53FDB3D8DB8CA971. Edit: Looks like @Elias64Fr is correct -- we need to look for Apple version "33" and not "51".



Side by side comparison:


UPDATE: My understanding about version numbers seems to be INCORRECT. If it says "33" in the ROM file, we need to find "33" and not the decimal equivalent of "33".

 

[tasc]

At the rate this thread is going, I'm fully expecting CaseySJ to reverse engineer the T2 chip and provide instructions for how we can wire it in ourselves by Christmas 2020.

 

[Feartech]

At the rate this thread is going, I'm fully expecting CaseySJ to reverse engineer the T2 chip and provide instructions for how we can wire it in ourselves by Christmas 2020.

or by tomorrow afternoon after lunch

 

[CaseySJ]

At the rate this thread is going, I'm fully expecting CaseySJ to reverse engineer the T2 chip and provide instructions for how we can wire it in ourselves by Christmas 2020.

or by tomorrow afternoon after lunch

Don't want to over-promise and under-deliver! That is always a danger in this field...