hey this pike thanks for your help this is the output of the code.
/*
* Intel ACPI Component Architecture
* AML Disassembler version 20130210-00 [Feb 10 2013]
* Copyright (c) 2000 - 2013 Intel Corporation
*
* Original Table Header:
* Signature "SSDT"
* Length 0x0000036A (874)
* Revision 0x01
* Checksum 0x00
* OEM ID "APPLE "
* OEM Table ID "CpuPm"
* OEM Revision 0x00004100 (16640)
* Compiler ID "INTL"
* Compiler Version 0x20130210 (538116624)
*/
DefinitionBlock ("SSDT_PR.aml", "SSDT", 1, "APPLE ", "CpuPm", 0x00004100)
{
External (\_PR_.CPU0, DeviceObj)
External (\_PR_.CPU1, DeviceObj)
External (\_PR_.CPU2, DeviceObj)
External (\_PR_.CPU3, DeviceObj)
External (\_PR_.CPU4, DeviceObj)
External (\_PR_.CPU5, DeviceObj)
External (\_PR_.CPU6, DeviceObj)
External (\_PR_.CPU7, DeviceObj)
Store ("ssdtPRGen.sh v4.1", Debug)
Store ("baseFrequency : 1600", Debug)
Store ("frequency : 3500", Debug)
Store ("logicalCPUs : 8", Debug)
Store ("tdp : 77", Debug)
Store ("packageLength : 31", Debug)
Store ("turboStates : 11", Debug)
Store ("maxTurboFrequency: 4600", Debug)
Scope (\_PR.CPU0)
{
Name (APLF, 0x08)
Name (APSN, 0x0C)
Name (APSS, Package (0x28)
{
/* Workaround for Ivy Bridge PM bug */
Package (0x06) { 0x11F9, 0x012CC8, 0x0A, 0x0A, 0x2F00, 0x2F00 },
/* High Frequency Modes (turbo) */
Package (0x06) { 0x11F8, 0x012CC8, 0x0A, 0x0A, 0x2E00, 0x2E00 },
Package (0x06) { 0x1194, 0x012CC8, 0x0A, 0x0A, 0x2D00, 0x2D00 },
Package (0x06) { 0x1130, 0x012CC8, 0x0A, 0x0A, 0x2C00, 0x2C00 },
Package (0x06) { 0x10CC, 0x012CC8, 0x0A, 0x0A, 0x2B00, 0x2B00 },
Package (0x06) { 0x1068, 0x012CC8, 0x0A, 0x0A, 0x2A00, 0x2A00 },
Package (0x06) { 0x1004, 0x012CC8, 0x0A, 0x0A, 0x2900, 0x2900 },
Package (0x06) { 0x0FA0, 0x012CC8, 0x0A, 0x0A, 0x2800, 0x2800 },
Package (0x06) { 0x0F3C, 0x012CC8, 0x0A, 0x0A, 0x2700, 0x2700 },
Package (0x06) { 0x0ED8, 0x012CC8, 0x0A, 0x0A, 0x2600, 0x2600 },
Package (0x06) { 0x0E74, 0x012CC8, 0x0A, 0x0A, 0x2500, 0x2500 },
Package (0x06) { 0x0E10, 0x012CC8, 0x0A, 0x0A, 0x2400, 0x2400 },
/* High Frequency Modes (non-turbo) */
Package (0x06) { 0x0DAC, 0x012CC8, 0x0A, 0x0A, 0x2300, 0x2300 },
Package (0x06) { 0x0D48, 0x0120E0, 0x0A, 0x0A, 0x2200, 0x2200 },
Package (0x06) { 0x0CE4, 0x01152F, 0x0A, 0x0A, 0x2100, 0x2100 },
Package (0x06) { 0x0C80, 0x0109B4, 0x0A, 0x0A, 0x2000, 0x2000 },
Package (0x06) { 0x0C1C, 0x00FE6F, 0x0A, 0x0A, 0x1F00, 0x1F00 },
Package (0x06) { 0x0BB8, 0x00F35F, 0x0A, 0x0A, 0x1E00, 0x1E00 },
Package (0x06) { 0x0B54, 0x00E884, 0x0A, 0x0A, 0x1D00, 0x1D00 },
Package (0x06) { 0x0AF0, 0x00DDDD, 0x0A, 0x0A, 0x1C00, 0x1C00 },
Package (0x06) { 0x0A8C, 0x00D36A, 0x0A, 0x0A, 0x1B00, 0x1B00 },
Package (0x06) { 0x0A28, 0x00C92B, 0x0A, 0x0A, 0x1A00, 0x1A00 },
Package (0x06) { 0x09C4, 0x00BF1F, 0x0A, 0x0A, 0x1900, 0x1900 },
Package (0x06) { 0x0960, 0x00B546, 0x0A, 0x0A, 0x1800, 0x1800 },
Package (0x06) { 0x08FC, 0x00AB9F, 0x0A, 0x0A, 0x1700, 0x1700 },
Package (0x06) { 0x0898, 0x00A229, 0x0A, 0x0A, 0x1600, 0x1600 },
Package (0x06) { 0x0834, 0x0098E6, 0x0A, 0x0A, 0x1500, 0x1500 },
Package (0x06) { 0x07D0, 0x008FD3, 0x0A, 0x0A, 0x1400, 0x1400 },
Package (0x06) { 0x076C, 0x0086F1, 0x0A, 0x0A, 0x1300, 0x1300 },
Package (0x06) { 0x0708, 0x007E3F, 0x0A, 0x0A, 0x1200, 0x1200 },
Package (0x06) { 0x06A4, 0x0075BD, 0x0A, 0x0A, 0x1100, 0x1100 },
/* Low Frequency Mode */
Package (0x06) { 0x0640, 0x006D6A, 0x0A, 0x0A, 0x1000, 0x1000 },
Package (0x06) { 0x05DC, Zero, 0x0A, 0x0A, 0x0F00, 0x0F00 },
Package (0x06) { 0x0578, Zero, 0x0A, 0x0A, 0x0E00, 0x0E00 },
Package (0x06) { 0x0514, Zero, 0x0A, 0x0A, 0x0D00, 0x0D00 },
Package (0x06) { 0x04B0, Zero, 0x0A, 0x0A, 0x0C00, 0x0C00 },
Package (0x06) { 0x044C, Zero, 0x0A, 0x0A, 0x0B00, 0x0B00 },
Package (0x06) { 0x03E8, Zero, 0x0A, 0x0A, 0x0A00, 0x0A00 },
Package (0x06) { 0x0384, Zero, 0x0A, 0x0A, 0x0900, 0x0900 },
Package (0x06) { 0x0320, Zero, 0x0A, 0x0A, 0x0800, 0x0800 }
})
Method (ACST, 0, NotSerialized)
{
Store ("CPU0 C-States : 13", Debug)
/* Low Power Modes for CPU0 */
Return (Package (0x05)
{
One,
0x03,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
One,
Zero,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x03, // Access Size
)
},
0x03,
0xCD,
0x01F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000020, // Address
0x03, // Access Size
)
},
0x06,
0xF5,
0x015E
}
})
}
Method (_DSM, 4, NotSerialized)
{
If (LEqual (Arg2, Zero))
{
Return (Buffer (One)
{
0x03
})
}
Return (Package (0x02)
{
"plugin-type",
One
})
}
}
Scope (\_PR.CPU1)
{
Method (APSS, 0, NotSerialized) { Return (\_PR.CPU0.APSS) }
Method (ACST, 0, NotSerialized)
{
Store ("CPU1 C-States : 7", Debug)
/* Low Power Modes for CPU1 */
Return (Package (0x05)
{
One,
0x03,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
One,
0x03E8,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x03, // Access Size
)
},
0x02,
0x94,
0x01F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000030, // Address
0x03, // Access Size
)
},
0x03,
0xC6,
0xC8
}
})
}
}
Scope (\_PR.CPU2)
{
Method (APSS, 0, NotSerialized) { Return (\_PR.CPU0.APSS) }
Method (ACST, 0, NotSerialized) { Return (\_PR.CPU1.ACST ()) }
}
Scope (\_PR.CPU3)
{
Method (APSS, 0, NotSerialized) { Return (\_PR.CPU0.APSS) }
Method (ACST, 0, NotSerialized) { Return (\_PR.CPU1.ACST ()) }
}
Scope (\_PR.CPU4)
{
Method (APSS, 0, NotSerialized) { Return (\_PR.CPU0.APSS) }
Method (ACST, 0, NotSerialized) { Return (\_PR.CPU1.ACST ()) }
}
Scope (\_PR.CPU5)
{
Method (APSS, 0, NotSerialized) { Return (\_PR.CPU0.APSS) }
Method (ACST, 0, NotSerialized) { Return (\_PR.CPU1.ACST ()) }
}
Scope (\_PR.CPU6)
{
Method (APSS, 0, NotSerialized) { Return (\_PR.CPU0.APSS) }
Method (ACST, 0, NotSerialized) { Return (\_PR.CPU1.ACST ()) }
}
Scope (\_PR.CPU7)
{
Method (APSS, 0, NotSerialized) { Return (\_PR.CPU0.APSS) }
Method (ACST, 0, NotSerialized) { Return (\_PR.CPU1.ACST ()) }
}
}