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SSDT for Yorkfield?

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Dec 27, 2015
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Motherboard
Gigabyte GA-EP45-UD3R 1.0/F12
CPU
Q9650
Graphics
GTX 750 Ti
Mac
  1. MacBook
Mobile Phone
  1. iOS
I've got this old box running Sierra just fine, but there's one final feature I had in El Capitan that I'm trying to enable: power savings.

In El Capitan, using the old MacPro3,1 sysdef, it was enough to simply set the GenerateCStates and GeneratePStates flags to 'true'. That doesn't seem to work with Sierra: since my box requires the iMac 14,2 definition—a Mac with a very different CPU than the old Core2 series—it looks like I'm going to need to specify more items to get this working. (For the record, when I was experimenting with an iMac10,1 sysdef during beta testing, I couldn't get it to work either, but at the time I was busy with just (a) getting a working installer built, and then (b) getting USB and graphics working.)

I'm using the latest versions of both Clover (3961) and Clover Configurator (4.38.0).

AppleIntelInfo.kext is no help here, since it doesn't support the Core2 Quad CPUs (I've tried it). The only information I've been able to glean so far indicates C2 and C4 states are supported, and that SpeedStep works in 333 MHz steps, with a minimum speed of 2.00 GHz (or was it 1.66 GHz? I forget...), which means a MinMult of 6 (or 5) and a MaxMult of 9. Voltage ranges from 0.8500 to 1.3625V (HW Monitor currently claims 1.2320V at full speed). TDP is 95W. As for voltage stepping, or other stuff like C3 latency, plugin type, PLimit info, QPI (whatever that is), I don't have a clue.

Since this isn't a Skylake, I'm assuming that Skylake-specific info isn't needed. Also, since this CPU doesn't have Turbo Boost, I'm leaving the TurboDisable flag set to 'false'. As for the QEMU flag, I'm assuming that's for virtualized/emulated CPUs, and so that's also set to 'false'.

Any suggestions?
 
OK...here's what I've been able to find out.

C3 Latency works like a switch: values of 0x3E8 (1000) or lower turn on SpeedStep, 0x3E9 or higher turns it off.

QPI is Quick Path Interconnect. On a Core2, this is basically just actual bus speed * 4, or what Intel advertises, q.v., 1333 MHz.

PLimit Dict is for power limiting; for newer CPUs, this should be set to 0 for full power, but on the Core2, this should be set to 1. Higher values limit power and speed. Ditto for UnderVolt Step, except 0 in this case may mean full voltage!

Here's a gotcha: Bus Speed (again, the actual bus speed) is in kHz, not MHz!

Type is the hex CPUID string; for a Yorkfield, that's 0x1067A.

Still not sure what Plugin Type or the other checkboxes do just yet, though I suspect Drop OEM should be checked...Here's the Clover Configurator screenshots of what I've got so far, from the ACPI:

ACPI entries for SSDT.png


and the CPU:

CPU entries for SSDT.png
 
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