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[solved] How to combine SSDTs?

Joined
Feb 8, 2010
Messages
164
Motherboard
Gigabyte GA-Z87X-UD4H
CPU
i5-4670K
Graphics
RX 580
Mac
  1. MacBook Air
Mobile Phone
  1. iOS
Apologies if covered already, I have tried searching this forum and googling and checking the MaciASL wiki.

How can I combine my Sierra USB fix and power management SSDTs?

Sierra USB fix SSDT:
Code:
DefinitionBlock ("", "SSDT", 2, "hack", "EC", 0x00000000)
{
    Device (_SB.EC)
    {
        Name (_HID, "EC000000")  // _HID: Hardware ID
    }
}

Start of power management SSDT (full attached):
Code:
DefinitionBlock ("", "SSDT", 1, "PmRef", "CpuPm", 0x00003000)
{
    External (_PR_.CPU0, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU1, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU2, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU3, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU4, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU5, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU6, DeviceObj)    // Warning: Unknown object
    External (_PR_.CPU7, DeviceObj)    // Warning: Unknown object

    Scope (\_PR.CPU0)
    {
        Name (PSS, Package (0x1F)
        {
            Package (0x06)
            {
                0x00000ED8, 
                0x000076C0, 
                0x0000000A, 
                0x0000000A, 
                0x00002600, 
                0x00002600
            }, 

            Package (0x06)
            {
                0x00000E74, 
                0x000073A0, 
                0x0000000A, 
                0x0000000A, 
                0x00002500, 
                0x00002500
            },
...

Here is what I have tried:
Code:
DefinitionBlock ("", "SSDT", 1, "PmRef", "CpuPm", 0x00003000)
{
    External (_PR_.CPU0, DeviceObj)    // (from opcode)
    External (_PR_.CPU1, DeviceObj)    // (from opcode)
    External (_PR_.CPU2, DeviceObj)    // (from opcode)
    External (_PR_.CPU3, DeviceObj)    // (from opcode)
    External (_PR_.CPU4, DeviceObj)    // (from opcode)
    External (_PR_.CPU5, DeviceObj)    // (from opcode)
    External (_PR_.CPU6, DeviceObj)    // (from opcode)
    External (_PR_.CPU7, DeviceObj)    // (from opcode)
    External (_SB_.EC__, DeviceObj)    // (from opcode)

    Scope (\_SB.EC)
    {
        Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
        {
            Return (Package (0x01)
            {
                "EC000000"
            })
        }
    }

This does not work.
 

Attachments

  • SSDT.aml
    1.6 KB · Views: 67
Joined
Feb 8, 2010
Messages
164
Motherboard
Gigabyte GA-Z87X-UD4H
CPU
i5-4670K
Graphics
RX 580
Mac
  1. MacBook Air
Mobile Phone
  1. iOS
Oh! Looks like the below from your link answers this. I have a Haswell processor.
Toledo said:
ssdtPRGen applies to Sandy Bridge, Ivy Bridge and certain server processors.

P-States without SSDT:
Code:
CPU P-States [ (8) 35 38 ]
CPU C3-Cores [ 0 1 3 ]
CPU C6-Cores [ 0 1 3 ]
CPU C7-Cores [ 0 1 3 ]
CPU P-States [ (8) 26 35 38 ]
CPU P-States [ (8) 26 35 37 38 ]
CPU C3-Cores [ 0 1 2 3 ]
CPU C6-Cores [ 0 1 2 3 ]
CPU C7-Cores [ 0 1 2 3 ]
CPU P-States [ (8) 26 31 35 37 38 ]
CPU P-States [ (8) 26 27 31 35 37 38 ]
CPU P-States [ (8) 26 27 30 31 35 37 38 ]
CPU P-States [ 8 20 26 27 30 31 (34) 35 37 38 ]
CPU P-States [ (8) 20 24 26 27 30 31 34 35 37 38 ]
CPU P-States [ (8) 20 24 26 27 28 30 31 34 35 37 38 ]
CPU P-States [ 8 20 24 26 27 28 29 30 31 (34) 35 37 38 ]
CPU P-States [ 8 20 24 26 27 28 29 30 31 33 (34) 35 37 38 ]
CPU P-States [ (8) 20 24 25 26 27 28 29 30 31 33 34 35 37 38 ]
CPU P-States [ (8) 20 21 24 25 26 27 28 29 30 31 33 34 35 37 38 ]
CPU P-States [ (8) 20 21 24 25 26 27 28 29 30 31 32 33 34 35 37 38 ]
CPU P-States [ (8) 20 21 23 24 25 26 27 28 29 30 31 32 33 34 35 37 38 ]
CPU P-States [ 8 20 21 23 24 25 26 27 28 29 30 31 32 33 34 35 (36) 37 38 ]
CPU P-States [ 8 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (34) 35 36 37 38 ]
CPU P-States [ 8 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (34) 35 36 37 38 ]
CPU P-States [ (8) 10 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ]
CPU P-States [ (8) 10 15 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ]
CPU P-States [ (8) 10 14 15 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ]
CPU P-States [ 8 10 14 15 16 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (34) 35 36 37 38 ]
CPU P-States [ (8) 10 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ]
CPU P-States [ (8) 10 11 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ]
CPU P-States [ (8) 10 11 12 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ]
CPU P-States [ (8) 10 11 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ]
CPU P-States [ (8) 9 10 11 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ]

P-States with SSDT:
Code:
CPU P-States [ (8) 35 38 ]
CPU C3-Cores [ 0 2 ]
CPU C6-Cores [ 0 2 3 ]
CPU C7-Cores [ 0 2 3 ]
CPU P-States [ 8 (34) 35 37 38 ]
CPU C3-Cores [ 0 1 2 ]
CPU C6-Cores [ 0 1 2 3 ]
CPU C7-Cores [ 0 1 2 3 ]
CPU P-States [ 8 34 35 (36) 37 38 ]
CPU C3-Cores [ 0 1 2 3 ]
CPU P-States [ (8) 32 34 35 36 37 38 ]
CPU P-States [ (8) 25 32 34 35 36 37 38 ]
CPU P-States [ 8 25 32 33 (34) 35 36 37 38 ]
CPU P-States [ (8) 25 29 32 33 34 35 36 37 38 ]
CPU P-States [ (8) 25 27 29 32 33 34 35 36 37 38 ]
CPU P-States [ 8 25 27 29 30 32 33 (34) 35 36 37 38 ]
CPU P-States [ 8 25 27 29 30 31 32 33 (34) 35 36 37 38 ]
CPU P-States [ (8) 25 27 28 29 30 31 32 33 34 35 36 37 38 ]
CPU P-States [ 8 25 26 27 28 29 30 31 32 33 (34) 35 36 37 38 ]
CPU P-States [ 8 23 25 26 27 28 29 30 31 32 33 (34) 35 36 37 38 ]
CPU P-States [ (8) 20 23 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ]
CPU P-States [ (8) 19 20 23 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ]
CPU P-States [ (8) 14 19 20 23 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ]
CPU P-States [ (8) 14 17 19 20 23 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ]
CPU P-States [ (8) 14 17 19 20 21 23 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ]
CPU P-States [ (8) 14 17 19 20 21 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ]
CPU P-States [ (8) 14 16 17 19 20 21 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ]
CPU P-States [ (8) 12 14 16 17 19 20 21 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ]
CPU P-States [ 8 12 14 16 17 18 19 20 21 23 24 25 26 27 28 29 30 31 32 33 (34) 35 36 37 38 ]
CPU P-States [ (8) 12 14 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ]
CPU P-States [ 8 12 13 14 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (34) 35 36 37 38 ]
CPU P-States [ (8) 10 12 13 14 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ]
CPU P-States [ (8) 10 11 12 13 14 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 ]

Which has better power management? I am guessing without SSDT as it has 30 total states, whereas with SSDT has 29 total states.
 
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