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[Solved] El Capitan sleep/wake problems!

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I see. I will try removing SSDT-PRW & Keep XWAK to ZWAK.

For the SSDT-XHC.aml file on your Github, do you have a .dsl file too? I thought I had to change .dsl first & then compile into .aml? Can I just change based on your .aml? Sorry I'm not familiar with changing .aml file. Thank you.

SSDT-XHC is already made ready but will require to be modified for Series 100. & for SATA thats probably a easy one to do also.

Code:
 If (CondRefOf (_SB.PCI0.XHC))
    {
        Method (_SB.PCI0.XHC._DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
        {
            If (LNot (Arg2))
            {
                Return (Buffer (One)
                {
                     0x03                                         
                })
            }

            Store (Package (0x1A)
                {
                    "AAPL,clock-id",
                    Buffer (0x04)
                    {
                         0x02                                         
                    },

                    "AAPL,slot-name",
                    "Built In",
                    "name",
                    "Intel XHCI Controller",
                    "model",
                    Buffer (0x37)
                    {
                        "Intel 9 Series Chipset Family USB xHCI Host Controller"
                    },

                    "device_type",
                    Buffer (0x0F)
                    {
                        "USB Controller"
                    },

                    "AAPL,current-available",
                    Buffer (0x04)
                    {
                         0x34, 0x08, 0x00, 0x00                       
                    },

                    "AAPL,current-extra",
                    Buffer (0x04)
                    {
                         0x98, 0x08, 0x00, 0x00                       
                    },

                    "AAPL,current-in-sleep",
                    Buffer (0x04)
                    {
                         0x40, 0x06, 0x00, 0x00                       
                    },

                    "AAPL,current-extra-in-sleep",
                    Buffer (0x04)
                    {
                         0x40, 0x06, 0x00, 0x00                       
                    },

                    "AAPL,max-port-current-in-sleep",
                    Buffer (0x04)
                    {
                         0x34, 0x08, 0x00, 0x00                       
                    },

                    "AAPL,device-internal",
                    Buffer (0x04)
                    {
                         0x02, 0x00, 0x00, 0x00                       
                    },

                    "subsystem-id",
                    Buffer (0x04)
                    {
                         0x07, 0x50, 0x00, 0x00                       
                    },

                    "subsystem-vendor-id",
                    Buffer (0x04)
                    {
                         0x58, 0x14, 0x00, 0x00                       
                    }
                }, Local0)
            If (CondRefOf (\_SB.PCI0.RMD2))
            {
                CreateDWordField (DerefOf (Index (Local0, One)), Zero, PR2F)
                Store (0x3FFF, PR2F)
            }

            Return (Local0)
        }
    }
}
 
SSDT-XHC is already made ready but will require to be modified for Series 100. & for SATA thats probably a easy one to do also.

Code:
 If (CondRefOf (_SB.PCI0.XHC))
    {
        Method (_SB.PCI0.XHC._DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
        {
            If (LNot (Arg2))
            {
                Return (Buffer (One)
                {
                     0x03                                        
                })
            }

            Store (Package (0x1A)
                {
                    "AAPL,clock-id",
                    Buffer (0x04)
                    {
                         0x02                                        
                    },

                    "AAPL,slot-name",
                    "Built In",
                    "name",
                    "Intel XHCI Controller",
                    "model",
                    Buffer (0x37)
                    {
                        "Intel 9 Series Chipset Family USB xHCI Host Controller"
                    },

                    "device_type",
                    Buffer (0x0F)
                    {
                        "USB Controller"
                    },

                    "AAPL,current-available",
                    Buffer (0x04)
                    {
                         0x34, 0x08, 0x00, 0x00                      
                    },

                    "AAPL,current-extra",
                    Buffer (0x04)
                    {
                         0x98, 0x08, 0x00, 0x00                      
                    },

                    "AAPL,current-in-sleep",
                    Buffer (0x04)
                    {
                         0x40, 0x06, 0x00, 0x00                      
                    },

                    "AAPL,current-extra-in-sleep",
                    Buffer (0x04)
                    {
                         0x40, 0x06, 0x00, 0x00                      
                    },

                    "AAPL,max-port-current-in-sleep",
                    Buffer (0x04)
                    {
                         0x34, 0x08, 0x00, 0x00                      
                    },

                    "AAPL,device-internal",
                    Buffer (0x04)
                    {
                         0x02, 0x00, 0x00, 0x00                      
                    },

                    "subsystem-id",
                    Buffer (0x04)
                    {
                         0x07, 0x50, 0x00, 0x00                      
                    },

                    "subsystem-vendor-id",
                    Buffer (0x04)
                    {
                         0x58, 0x14, 0x00, 0x00                      
                    }
                }, Local0)
            If (CondRefOf (\_SB.PCI0.RMD2))
            {
                CreateDWordField (DerefOf (Index (Local0, One)), Zero, PR2F)
                Store (0x3FFF, PR2F)
            }

            Return (Local0)
        }
    }
}

Thanks a lot. What field(s) do I change to modify for Series 100? Sorry I'm not familiar with the differences between Series 9 & 100.
 
Thanks a lot. What field(s) do I change to modify for Series 100? Sorry I'm not familiar with the differences between Series 9 & 100.

Attach ioreg.
 

Attachments

  • SSDT-SATA.aml
    457 bytes · Views: 309
  • SSDT-XHC.aml
    558 bytes · Views: 310
Try this. Attach ioreg & config after rebooting with the SSDTs i provided.

Here they are (IOREG & CLOVER). I copied the new SSDTs you provided to the ACPI Patched folder. Thank you. Seems like I can see SATA defined for Series 100 now & XHC also.

I tested the sleep / wake but it still fails to wake up with same frozen display (Keyboard / USB not responding - Power Button needs to be pushed to shut down & restart).

Note I haven't removed the "DropTables" TableId" / "CpuPm" yet.
 

Attachments

  • KDL18_NEW_IOREG.zip
    692 KB · Views: 226
  • KDL18_NEW_CLOVER.zip
    2.4 MB · Views: 231
Here they are (IOREG & CLOVER). I copied the new SSDTs you provided to the ACPI Patched folder. Thank you. Seems like I can see SATA defined for Series 100 now & XHC also.

I tested the sleep / wake but it still fails to wake up with same frozen display (Keyboard / USB not responding - Power Button needs to be pushed to shut down & restart).

Yep that is correct. Thats how it should look and if you noticed that AAPL is also injected so you'll have full Power through USB 3 and 2 ports.
 
Yep that is correct. Thats how it should look and if you noticed that AAPL is also injected so you'll have full Power through USB 3 and 2 ports.

Awesome for having full power USB 2 & 3, and APPL injected (not sure where to see it). Thanks so much. So my USB is fully functional now then, right?

Which means my wake problem might be related to something else (graphics card setup? I have a GTX970 on a PCI slot + H100i v2 cooler connected to an internal USB port). Is there a way to see what prevents the system from waking up properly?
 
Awesome for having full power USB 2 & 3, and APPL injected (not sure where to see it). Thanks so much. So my USB is fully functional now then, right?

Which means my wake problem might be related to something else (graphics card setup? I have a GTX970 on a PCI slot + H100i v2 cooler connected to an internal USB port). Is there a way to see what prevents the system from waking up?

You can look in ioreg by searching XHC or SATA its quite easy to use ioreg. USB function really depends on if you're over the 15 port limit. Im not quite sure on how stable the nvidia web drivers are don't use them and i certainly don't use Water-cooling but OS X will ignore it as theres no driver for that device.
 
You can look in ioreg by searching XHC or SATA its quite easy to use ioreg. USB function really depends on if you're over the 15 port limit. Im not quite sure on how stable the nvidia web drivers are don't use them and i certainly don't use Water-cooling but OS X will ignore it as theres no driver for that device.

Yes, I search in IOREG for XHC & SATA. For XHC, when I do the search, I see 14 ports defined. HS01 thru HS08 + SS01 thru SS06. Shouldn't it be fine? That's without counting the Hubs.

Though now, I don't see the attached devices anymore in my IOREG -> I used to see "Mouse" in one of the HS port / "Keyboard" in another port... Maybe that's what you mean by AAPL being injected - or - USB Full Power?

I need the Nvidia Web Drivers for Skylake & Sierra based on what I've been told / tried so far. Otherwise, I only get "14MB" of internal graphics RAM display and display is very slow.
 
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