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Kaby Lake 630 Graphics

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JCMunsonII said:
OK, here's the AppleIntelInfo file... Hopefully this point to successful?
Click to expand...

Did you fix X86PlatformPlugin loading?
Last ioreg you attached showed CPU PM not working due to an invalid SSDT.aml in ACPI/patched...
 
RehabMan said:
Did you fix X86PlatformPlugin loading?
Last ioreg you attached showed CPU PM not working due to an invalid SSDT.aml in ACPI/patched...
Click to expand...
OK, I'm a little confused...

Does that SSDT.aml need to actually be compiled (via MaciASL)?

And where did X86PlatformPlugin come into play?
 
I suppose it does need to be compiled. However, I end up with a series of errors.

Here is the code:
Code: 
/*
 * Intel ACPI Component Architecture
 * AML Disassembler version 20140210-00 [Feb 10 2014]
 * Copyright (c) 2000 - 2014 Intel Corporation
 *
 * Original Table Header:
 *     Signature        "SSDT"
 *     Length           0x0000036A (874)
 *     Revision         0x01
 *     Checksum         0x00
 *     OEM ID           "APPLE "
 *     OEM Table ID     "CpuPm"
 *     OEM Revision     0x00021500 (136448)
 *     Compiler ID      "INTL"
 *     Compiler Version 0x20140210 (538182160)
 */

DefinitionBlock ("ssdt.aml", "SSDT", 1, "APPLE ", "CpuPm", 0x00021500)
{
    External (\_PR.CPU0, DeviceObj)
    External (\_PR.CPU1, DeviceObj)
    External (\_PR.CPU0, DeviceObj)
    External (\_PR.CPU1, DeviceObj)
    External (\_PR.CPU0, DeviceObj)
    External (\_PR.CPU1, DeviceObj)
    External (\_PR.CPU0, DeviceObj)
    External (\_PR.CPU1, DeviceObj)

    Scope (\_PR.CPU0)
    {
        Method (_INI, 0, NotSerialized)
        {
            Store ("ssdtPRGen version.....: 21.5 / Mac OS X 10.11.6 (15G1421)", Debug)
            Store ("custom mode...........: 0", Debug)
            Store ("host processor........: Intel(R) Core(TM)2 Duo CPU E8435 @ 3.06GHz", Debug)
            Store ("target processor......: i7-7700K", Debug)
            Store ("number of processors..: 1", Debug)
            Store ("baseFrequency.........: 800", Debug)
            Store ("frequency.............: 4200", Debug)
            Store ("busFrequency..........: 100", Debug)
            Store ("logicalCPUs...........: 8", Debug)
            Store ("maximum TDP...........: 95", Debug)
            Store ("packageLength.........: 38", Debug)
            Store ("turboStates...........: 3", Debug)
            Store ("maxTurboFrequency.....: 4500", Debug)
            Store ("machdep.xcpm.mode.....: 0", Debug)
        }

        Name (APLF, Zero)
        Name (APSN, 0x03)
        Name (APSS, Package (0x26)
        {
            /* High Frequency Modes (turbo) */
            Package (0x06) { 0x1194, 0x017318, 0x0A, 0x0A, 0x2D00, 0x2D00 },
            Package (0x06) { 0x1130, 0x017318, 0x0A, 0x0A, 0x2C00, 0x2C00 },
            Package (0x06) { 0x10CC, 0x017318, 0x0A, 0x0A, 0x2B00, 0x2B00 },
            /* High Frequency Modes (non-turbo) */
            Package (0x06) { 0x1068, 0x017318, 0x0A, 0x0A, 0x2A00, 0x2A00 },
            Package (0x06) { 0x1004, 0x016627, 0x0A, 0x0A, 0x2900, 0x2900 },
            Package (0x06) { 0x0FA0, 0x01596F, 0x0A, 0x0A, 0x2800, 0x2800 },
            Package (0x06) { 0x0F3C, 0x014CF0, 0x0A, 0x0A, 0x2700, 0x2700 },
            Package (0x06) { 0x0ED8, 0x0140A9, 0x0A, 0x0A, 0x2600, 0x2600 },
            Package (0x06) { 0x0E74, 0x01349A, 0x0A, 0x0A, 0x2500, 0x2500 },
            Package (0x06) { 0x0E10, 0x0128C3, 0x0A, 0x0A, 0x2400, 0x2400 },
            Package (0x06) { 0x0DAC, 0x011D22, 0x0A, 0x0A, 0x2300, 0x2300 },
            Package (0x06) { 0x0D48, 0x0111B8, 0x0A, 0x0A, 0x2200, 0x2200 },
            Package (0x06) { 0x0CE4, 0x010683, 0x0A, 0x0A, 0x2100, 0x2100 },
            Package (0x06) { 0x0C80, 0x00FB85, 0x0A, 0x0A, 0x2000, 0x2000 },
            Package (0x06) { 0x0C1C, 0x00F0BC, 0x0A, 0x0A, 0x1F00, 0x1F00 },
            Package (0x06) { 0x0BB8, 0x00E627, 0x0A, 0x0A, 0x1E00, 0x1E00 },
            Package (0x06) { 0x0B54, 0x00DBC6, 0x0A, 0x0A, 0x1D00, 0x1D00 },
            Package (0x06) { 0x0AF0, 0x00D19A, 0x0A, 0x0A, 0x1C00, 0x1C00 },
            Package (0x06) { 0x0A8C, 0x00C7A0, 0x0A, 0x0A, 0x1B00, 0x1B00 },
            Package (0x06) { 0x0A28, 0x00BDDA, 0x0A, 0x0A, 0x1A00, 0x1A00 },
            Package (0x06) { 0x09C4, 0x00B447, 0x0A, 0x0A, 0x1900, 0x1900 },
            Package (0x06) { 0x0960, 0x00AAE5, 0x0A, 0x0A, 0x1800, 0x1800 },
            Package (0x06) { 0x08FC, 0x00A1B5, 0x0A, 0x0A, 0x1700, 0x1700 },
            Package (0x06) { 0x0898, 0x0098B6, 0x0A, 0x0A, 0x1600, 0x1600 },
            Package (0x06) { 0x0834, 0x008FE8, 0x0A, 0x0A, 0x1500, 0x1500 },
            Package (0x06) { 0x07D0, 0x00874B, 0x0A, 0x0A, 0x1400, 0x1400 },
            Package (0x06) { 0x076C, 0x007EDD, 0x0A, 0x0A, 0x1300, 0x1300 },
            Package (0x06) { 0x0708, 0x00769F, 0x0A, 0x0A, 0x1200, 0x1200 },
            Package (0x06) { 0x06A4, 0x006E90, 0x0A, 0x0A, 0x1100, 0x1100 },
            Package (0x06) { 0x0640, 0x0066AF, 0x0A, 0x0A, 0x1000, 0x1000 },
            Package (0x06) { 0x05DC, 0x005EFC, 0x0A, 0x0A, 0x0F00, 0x0F00 },
            Package (0x06) { 0x0578, 0x005778, 0x0A, 0x0A, 0x0E00, 0x0E00 },
            Package (0x06) { 0x0514, 0x005020, 0x0A, 0x0A, 0x0D00, 0x0D00 },
            Package (0x06) { 0x04B0, 0x0048F6, 0x0A, 0x0A, 0x0C00, 0x0C00 },
            Package (0x06) { 0x044C, 0x0041F7, 0x0A, 0x0A, 0x0B00, 0x0B00 },
            Package (0x06) { 0x03E8, 0x003B25, 0x0A, 0x0A, 0x0A00, 0x0A00 },
            Package (0x06) { 0x0384, 0x00347E, 0x0A, 0x0A, 0x0900, 0x0900 },
            /* Low Frequency Mode */
            Package (0x06) { 0x0320, 0x002E03, 0x0A, 0x0A, 0x0800, 0x0800 }
        })

        Method (ACST, 0, NotSerialized)
        {
            Store ("Method _PR.CPU0.ACST Called", Debug)
            Store ("CPU0 C-States    : 253", Debug)

            /* Low Power Modes for CPU0 */
            Return (Package (0x06)
            {
                One,
                0x04,
                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW,
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000000, // Address
                            0x01,               // Access Size
                            )
                    },
                    One,
                    Zero,
                    0x03E8
                },

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW,
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000010, // Address
                            0x03,               // Access Size
                            )
                    },
                    0x03,
                    0xCD,
                    0x01F4
                },

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW,
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000020, // Address
                            0x03,               // Access Size
                            )
                    },
                    0x06,
                    0xF5,
                    0x015E
                },

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW,
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000030, // Address
                            0x03,               // Access Size
                            )
                    },
                    0x07,
                    0xF5,
                    0xC8
                }
            })
        }

        Method (_DSM, 4, NotSerialized)
        {
            Store ("Method _PR.CPU0._DSM Called", Debug)

            If (LEqual (Arg2, Zero))
            {
                Return (Buffer (One)
                {
                    0x03
                })
            }

            Return (Package (0x02)
            {
                "plugin-type",
                One
            })
        }
    }

    Scope (\_PR.CPU1)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR.CPU1.APSS Called", Debug)

            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Store ("Method _PR.CPU1.ACST Called", Debug)
            Store ("CPU1 C-States    : 31", Debug)

            /* Low Power Modes for CPU1 */
            Return (Package (0x07)
            {
                One,
                0x05,
                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW,
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000000, // Address
                            0x01,               // Access Size
                            )
                    },
                    One,
                    0x03E8,
                    0x03E8
                },

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW,
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000010, // Address
                            0x03,               // Access Size
                            )
                    },
                    0x02,
                    0x94,
                    0x01F4
                },

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW,
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000030, // Address
                            0x03,               // Access Size
                            )
                    },
                    0x03,
                    0xC6,
                    0xC8
                },

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW,
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000040, // Address
                            0x03,               // Access Size
                            )
                    },
                    0x06,
                    0xF5,
                    0x015E
                },

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW,
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000050, // Address
                            0x03,               // Access Size
                            )
                    },
                    0x07,
                    0xF5,
                    0xC8
                }
            })
        }
    }

    Scope (\_PR.CPU0)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR.CPU0.APSS Called", Debug)

            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized) { Return (\_PR.CPU1.ACST ()) }
    }

    Scope (\_PR.CPU1)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR.CPU1.APSS Called", Debug)

            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized) { Return (\_PR.CPU1.ACST ()) }
    }

    Scope (\_PR.CPU0)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR.CPU0.APSS Called", Debug)

            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized) { Return (\_PR.CPU1.ACST ()) }
    }

    Scope (\_PR.CPU1)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR.CPU1.APSS Called", Debug)

            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized) { Return (\_PR.CPU1.ACST ()) }
    }

    Scope (\_PR.CPU0)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR.CPU0.APSS Called", Debug)

            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized) { Return (\_PR.CPU1.ACST ()) }
    }

    Scope (\_PR.CPU1)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR.CPU1.APSS Called", Debug)

            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized) { Return (\_PR.CPU1.ACST ()) }
    }
}

See attached screenshots for errors. In case the line numbers do not line up, the errors start at the "Scope" definitions...

What is the fix for that?
 

Attachments

  • Screen Shot 2017-05-12 at 5.59.16 PM.png
    Screen Shot 2017-05-12 at 5.59.16 PM.png
    174.2 KB · Views: 100
I removed the ".rtf" extension, rebooted, and ran AppleIntelInfo.kext. Attached is that output. I've also attached the current IOReg.

I think power management is implemented, but, I'll let you tell me based on these two files...
 

Attachments

  • IOReg.ioreg
    5.1 MB · Views: 101
  • i77700KTest.txt
    16.3 KB · Views: 95
JCMunsonII said:
I suppose it does need to be compiled. However, I end up with a series of errors.

Here is the code:
Code: 
/*
 * Intel ACPI Component Architecture
 * AML Disassembler version 20140210-00 [Feb 10 2014]
 * Copyright (c) 2000 - 2014 Intel Corporation
 *
 * Original Table Header:
 *     Signature        "SSDT"
 *     Length           0x0000036A (874)
 *     Revision         0x01
 *     Checksum         0x00
 *     OEM ID           "APPLE "
 *     OEM Table ID     "CpuPm"
 *     OEM Revision     0x00021500 (136448)
 *     Compiler ID      "INTL"
 *     Compiler Version 0x20140210 (538182160)
 */

DefinitionBlock ("ssdt.aml", "SSDT", 1, "APPLE ", "CpuPm", 0x00021500)
{
    External (\_PR.CPU0, DeviceObj)
    External (\_PR.CPU1, DeviceObj)
    External (\_PR.CPU0, DeviceObj)
    External (\_PR.CPU1, DeviceObj)
    External (\_PR.CPU0, DeviceObj)
    External (\_PR.CPU1, DeviceObj)
    External (\_PR.CPU0, DeviceObj)
    External (\_PR.CPU1, DeviceObj)

    Scope (\_PR.CPU0)
    {
        Method (_INI, 0, NotSerialized)
        {
            Store ("ssdtPRGen version.....: 21.5 / Mac OS X 10.11.6 (15G1421)", Debug)
            Store ("custom mode...........: 0", Debug)
            Store ("host processor........: Intel(R) Core(TM)2 Duo CPU E8435 @ 3.06GHz", Debug)
            Store ("target processor......: i7-7700K", Debug)
            Store ("number of processors..: 1", Debug)
            Store ("baseFrequency.........: 800", Debug)
            Store ("frequency.............: 4200", Debug)
            Store ("busFrequency..........: 100", Debug)
            Store ("logicalCPUs...........: 8", Debug)
            Store ("maximum TDP...........: 95", Debug)
            Store ("packageLength.........: 38", Debug)
            Store ("turboStates...........: 3", Debug)
            Store ("maxTurboFrequency.....: 4500", Debug)
            Store ("machdep.xcpm.mode.....: 0", Debug)
        }

        Name (APLF, Zero)
        Name (APSN, 0x03)
        Name (APSS, Package (0x26)
        {
            /* High Frequency Modes (turbo) */
            Package (0x06) { 0x1194, 0x017318, 0x0A, 0x0A, 0x2D00, 0x2D00 },
            Package (0x06) { 0x1130, 0x017318, 0x0A, 0x0A, 0x2C00, 0x2C00 },
            Package (0x06) { 0x10CC, 0x017318, 0x0A, 0x0A, 0x2B00, 0x2B00 },
            /* High Frequency Modes (non-turbo) */
            Package (0x06) { 0x1068, 0x017318, 0x0A, 0x0A, 0x2A00, 0x2A00 },
            Package (0x06) { 0x1004, 0x016627, 0x0A, 0x0A, 0x2900, 0x2900 },
            Package (0x06) { 0x0FA0, 0x01596F, 0x0A, 0x0A, 0x2800, 0x2800 },
            Package (0x06) { 0x0F3C, 0x014CF0, 0x0A, 0x0A, 0x2700, 0x2700 },
            Package (0x06) { 0x0ED8, 0x0140A9, 0x0A, 0x0A, 0x2600, 0x2600 },
            Package (0x06) { 0x0E74, 0x01349A, 0x0A, 0x0A, 0x2500, 0x2500 },
            Package (0x06) { 0x0E10, 0x0128C3, 0x0A, 0x0A, 0x2400, 0x2400 },
            Package (0x06) { 0x0DAC, 0x011D22, 0x0A, 0x0A, 0x2300, 0x2300 },
            Package (0x06) { 0x0D48, 0x0111B8, 0x0A, 0x0A, 0x2200, 0x2200 },
            Package (0x06) { 0x0CE4, 0x010683, 0x0A, 0x0A, 0x2100, 0x2100 },
            Package (0x06) { 0x0C80, 0x00FB85, 0x0A, 0x0A, 0x2000, 0x2000 },
            Package (0x06) { 0x0C1C, 0x00F0BC, 0x0A, 0x0A, 0x1F00, 0x1F00 },
            Package (0x06) { 0x0BB8, 0x00E627, 0x0A, 0x0A, 0x1E00, 0x1E00 },
            Package (0x06) { 0x0B54, 0x00DBC6, 0x0A, 0x0A, 0x1D00, 0x1D00 },
            Package (0x06) { 0x0AF0, 0x00D19A, 0x0A, 0x0A, 0x1C00, 0x1C00 },
            Package (0x06) { 0x0A8C, 0x00C7A0, 0x0A, 0x0A, 0x1B00, 0x1B00 },
            Package (0x06) { 0x0A28, 0x00BDDA, 0x0A, 0x0A, 0x1A00, 0x1A00 },
            Package (0x06) { 0x09C4, 0x00B447, 0x0A, 0x0A, 0x1900, 0x1900 },
            Package (0x06) { 0x0960, 0x00AAE5, 0x0A, 0x0A, 0x1800, 0x1800 },
            Package (0x06) { 0x08FC, 0x00A1B5, 0x0A, 0x0A, 0x1700, 0x1700 },
            Package (0x06) { 0x0898, 0x0098B6, 0x0A, 0x0A, 0x1600, 0x1600 },
            Package (0x06) { 0x0834, 0x008FE8, 0x0A, 0x0A, 0x1500, 0x1500 },
            Package (0x06) { 0x07D0, 0x00874B, 0x0A, 0x0A, 0x1400, 0x1400 },
            Package (0x06) { 0x076C, 0x007EDD, 0x0A, 0x0A, 0x1300, 0x1300 },
            Package (0x06) { 0x0708, 0x00769F, 0x0A, 0x0A, 0x1200, 0x1200 },
            Package (0x06) { 0x06A4, 0x006E90, 0x0A, 0x0A, 0x1100, 0x1100 },
            Package (0x06) { 0x0640, 0x0066AF, 0x0A, 0x0A, 0x1000, 0x1000 },
            Package (0x06) { 0x05DC, 0x005EFC, 0x0A, 0x0A, 0x0F00, 0x0F00 },
            Package (0x06) { 0x0578, 0x005778, 0x0A, 0x0A, 0x0E00, 0x0E00 },
            Package (0x06) { 0x0514, 0x005020, 0x0A, 0x0A, 0x0D00, 0x0D00 },
            Package (0x06) { 0x04B0, 0x0048F6, 0x0A, 0x0A, 0x0C00, 0x0C00 },
            Package (0x06) { 0x044C, 0x0041F7, 0x0A, 0x0A, 0x0B00, 0x0B00 },
            Package (0x06) { 0x03E8, 0x003B25, 0x0A, 0x0A, 0x0A00, 0x0A00 },
            Package (0x06) { 0x0384, 0x00347E, 0x0A, 0x0A, 0x0900, 0x0900 },
            /* Low Frequency Mode */
            Package (0x06) { 0x0320, 0x002E03, 0x0A, 0x0A, 0x0800, 0x0800 }
        })

        Method (ACST, 0, NotSerialized)
        {
            Store ("Method _PR.CPU0.ACST Called", Debug)
            Store ("CPU0 C-States    : 253", Debug)

            /* Low Power Modes for CPU0 */
            Return (Package (0x06)
            {
                One,
                0x04,
                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW,
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000000, // Address
                            0x01,               // Access Size
                            )
                    },
                    One,
                    Zero,
                    0x03E8
                },

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW,
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000010, // Address
                            0x03,               // Access Size
                            )
                    },
                    0x03,
                    0xCD,
                    0x01F4
                },

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW,
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000020, // Address
                            0x03,               // Access Size
                            )
                    },
                    0x06,
                    0xF5,
                    0x015E
                },

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW,
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000030, // Address
                            0x03,               // Access Size
                            )
                    },
                    0x07,
                    0xF5,
                    0xC8
                }
            })
        }

        Method (_DSM, 4, NotSerialized)
        {
            Store ("Method _PR.CPU0._DSM Called", Debug)

            If (LEqual (Arg2, Zero))
            {
                Return (Buffer (One)
                {
                    0x03
                })
            }

            Return (Package (0x02)
            {
                "plugin-type",
                One
            })
        }
    }

    Scope (\_PR.CPU1)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR.CPU1.APSS Called", Debug)

            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized)
        {
            Store ("Method _PR.CPU1.ACST Called", Debug)
            Store ("CPU1 C-States    : 31", Debug)

            /* Low Power Modes for CPU1 */
            Return (Package (0x07)
            {
                One,
                0x05,
                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW,
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000000, // Address
                            0x01,               // Access Size
                            )
                    },
                    One,
                    0x03E8,
                    0x03E8
                },

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW,
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000010, // Address
                            0x03,               // Access Size
                            )
                    },
                    0x02,
                    0x94,
                    0x01F4
                },

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW,
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000030, // Address
                            0x03,               // Access Size
                            )
                    },
                    0x03,
                    0xC6,
                    0xC8
                },

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW,
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000040, // Address
                            0x03,               // Access Size
                            )
                    },
                    0x06,
                    0xF5,
                    0x015E
                },

                Package (0x04)
                {
                    ResourceTemplate ()
                    {
                        Register (FFixedHW,
                            0x01,               // Bit Width
                            0x02,               // Bit Offset
                            0x0000000000000050, // Address
                            0x03,               // Access Size
                            )
                    },
                    0x07,
                    0xF5,
                    0xC8
                }
            })
        }
    }

    Scope (\_PR.CPU0)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR.CPU0.APSS Called", Debug)

            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized) { Return (\_PR.CPU1.ACST ()) }
    }

    Scope (\_PR.CPU1)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR.CPU1.APSS Called", Debug)

            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized) { Return (\_PR.CPU1.ACST ()) }
    }

    Scope (\_PR.CPU0)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR.CPU0.APSS Called", Debug)

            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized) { Return (\_PR.CPU1.ACST ()) }
    }

    Scope (\_PR.CPU1)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR.CPU1.APSS Called", Debug)

            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized) { Return (\_PR.CPU1.ACST ()) }
    }

    Scope (\_PR.CPU0)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR.CPU0.APSS Called", Debug)

            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized) { Return (\_PR.CPU1.ACST ()) }
    }

    Scope (\_PR.CPU1)
    {
        Method (APSS, 0, NotSerialized)
        {
            Store ("Method _PR.CPU1.APSS Called", Debug)

            Return (\_PR.CPU0.APSS)
        }

        Method (ACST, 0, NotSerialized) { Return (\_PR.CPU1.ACST ()) }
    }
}

See attached screenshots for errors. In case the line numbers do not line up, the errors start at the "Scope" definitions...

What is the fix for that?
Click to expand...

Your SSDT is bugged.
Regenerate with current ssdtPRgen.sh.

JCMunsonII said:
I removed the ".rtf" extension, rebooted, and ran AppleIntelInfo.kext. Attached is that output. I've also attached the current IOReg.

I think power management is implemented, but, I'll let you tell me based on these two files...
Click to expand...

Your ioreg shows CPU PM NOT implemented.
 
Alright, I think Watson's done it!

See attached, please let me know what you think.

As I've also fixed my USB ports, unless there's something else I need to address, should sleep now work?
 

Attachments

  • IOReg.ioreg
    5.1 MB · Views: 92
  • i77700KTest.txt
    17.2 KB · Views: 84
JCMunsonII said:
Alright, I think Watson's done it!

See attached, please let me know what you think.

As I've also fixed my USB ports, unless there's something else I need to address, should sleep now work?
Click to expand...

CPU PM looks fine.

USB is not correct.
The port limit is 15. You have 19 ports under XHC. Also, all HSxx ports are marked UsbConnector=3. There are 11 of them, yet only 6 SSxx ports. The number of HSxx ports with UsbConnector=3 is expected to match the number of SSxx ports (eg. you can't have a USB2 component of a USB3 port that doesn't exist).
HS14 looks like bluetooth, therefore is internal. Internal should be marked UsbConnector=255.
And probably other HSxx ports are USB2-only, therefore should be marked UsbConnector=0, unless of course they are attached to an internal device (then UsbConnector=255).

And not possible to predict the future regarding sleep/wake. Problems with sleep/wake can be caused by other mistake (eg. ACPI not patched correctly).
 
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