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iMac Pro X99 - Live the Future now with macOS 10.14 Mojave [Successful Build/Extended Guide]

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Thanks for the flowers. BTW.. if you are going to implement the missing SSDTs, note that all PCI devices under the same ACPI address like PCI0.BR2A.H000, but on different PCI bridges, must be part of the same SSDT.

Good luck, my friend!

KGP
Thanks for the reminder. And i just try to use the same way to modify the other ssdt. and the Wifi card showed in the CPI but lost the thunderbolt device.
399781
 

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Thanks for the flowers. BTW.. if you are going to implement the missing SSDTs, note that all PCI devices under the same ACPI address like PCI0.BR2A.H000, but on different PCI bridges, must be part of the same SSDT.

Good luck, my friend!

KGP
Hi KGP, i am sorry since as a newbie, a little difficult to modify the ssdt. I tried many times but failed. If you have some time, could you kindly help me with the ssdt. Much appreciate!
 

kgp

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Hi KGP, i am sorry since as a newbie, a little difficult to modify the ssdt. I tried many times but failed. If you have some time, could you kindly help me with the ssdt. Much appreciate!
You really should take the time and learn to do it yourself. It is impossible to permanently create all System SSDTs for nearly everybody. To adapt the TB-SSDT for you was rather an exception. A simple analysis of definition block, ACPI path and ACPI replacements within this TB-SSDT and a comparison of the original and subsequent IOREG ACPI table information should provide sufficient inside on all underlaying basics, which need to be considered for a proper adaptation of all other SSDTs available in my SSDT Github repositories. This small guideline might help in addition.

After adding any SSDT by considering all necessary adaptations, always verify "PCI" and IOREG ACPI table information. As soon you feel that everything is properly implemented, feel free to ask me for a final revision.

Good luck,

KGP
 
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gigabyte x79 ud3
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e5 2680 v2
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You really should take the time and learn to do it yourself. It is impossible to permanently create all System SSDTs for nearly everybody. To adapt the TB-SSDT for you was rather an exception. A simple analysis of definition block, ACPI path and ACPI replacements within this TB-SSDT and a comparison of the original and subsequent IOREG ACPI table information should provide sufficient inside on all underlaying basics, which need to be considered for a proper adaptation of all other SSDTs available in my SSDT Github repositories. This small guideline might help in addition.

After adding any SSDT by considering all necessary adaptations, always verify "PCI" and IOREG ACPI table information. As soon you feel that everything is properly implemented, feel free to ask me for a final revision.

Good luck,

KGP
Hi KGP,
Really appreciate for your help. I have already modified some of the PCI information to the correct ones. Your guidance was quite clearly. Now, i found there is a pci144d,a808 device showed in the PCI list. I even cannot find more details from IOREG. any advice for this one?
399877
 

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kgp

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Hi KGP,
Really appreciate for your help. I have already modified some of the PCI information to the correct ones. Your guidance was quite clearly. Now, i found there is a pci144d,a808 device showed in the PCI list. I even cannot find more details from IOREG. any advice for this one? View attachment 399877
As even stated in your screenshot, it is an NVMe controller you have to implement by means of a proper adaptation of SSDT-X99-ANS.aml.

Good luck,

KGP
 
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As even stated in your screenshot, it is an NVMe controller you have to implement by means of a proper adaptation of SSDT-X99-ANS.aml.

Good luck,

KGP
Hi KGP,

I tried to put the ssdt to the clover patched folder, and reboot. It just stopped at pci config begin... Could you help take a look and point out my mistake with the ssdt. Thanks a lot!
 

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kgp

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Hi KGP,

I tried to put the ssdt to the clover patched folder, and reboot. It just stopped at pci config begin... Could you help take a look and point out my mistake with the ssdt. Thanks a lot!
Vega PCI implementation must be part of the TB SDDT for PCI0.BR3A.H000, I created for you above, taking into account that Vega is implemented under pci-bridge@8 while TB adapter is assigned to pci-bridge@10 of PCI0.BR3A.H000.

Same approach, same solution..

Good luck,

KGP
 
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gigabyte x79 ud3
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Vega PCI implementation must be part of the TB SDDT for PCI0.BR3A.H000, I created for you above, taking into account that Vega is implemented under pci-bridge@8 while TB adapter is assigned to pci-bridge@10 of PCI0.BR3A.H000.

Same approach, same solution..

Good luck,

KGP
Basically, problems has solved through your guidance. Thank you again for your amazing job!:headbang:
 
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I think I might need some tweaks on my Vegas table speed set, she boost while Luxmark bench test but the results info shows only 945 Mhz, those results there no way can be done at that speed, this is a card that I bought at flea bay and I think this BIOS its not the factory one thanks that I got this card on water cause other wise would be fried by now.

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Hello, how to connect an Intel SSDPE2KX020T801 U2 drive ??? on such systems. and write to it macosx
 
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