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iMac Pro X99 - Live the Future now with macOS 10.14 Mojave [Successful Build/Extended Guide]

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The Veterant.
Share the secret of how you did it.
On your CPU type you should get event better scores or close to mine, do to your CPU family can Hack the CPU by a patch and have all the cores to turbo boost to I believed if Im not mistaking to 3.8, On mine I don't have that luxury Luck, so I'm happy w/ what I got
 
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What BIOS settings do you have and how did you do the cooling
 
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i just have the same hardware with the post except the mainboard. my mainboard is asus x99 e ws usb3.1. so the hardware address showed in ioregistry may totally difference. so the titan ridge cant implement well. hope you can help me with the ssdt modification. thanks so much! looking forward the replying.
 

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kgp

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i just have the same hardware with the post except the mainboard. my mainboard is asus x99 e ws usb3.1. so the hardware address showed in ioregistry may totally difference. so the titan ridge cant implement well. hope you can help me with the ssdt modification. thanks so much! looking forward the replying.
Attached TB SSDT needs to be used in line with SSDT-DTPG.aml and is just a first guess, as I am missing some original DSDT information.

Please reply with new IOREG.save after implementing both files under /EFI/Clover/ACPI/patched and rebooting your system.
 

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gigabyte x79 ud3
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Attached TB SSDT needs to be used in line with SSDT-DTPG.aml and is just a first guess, as I am missing some original DSDT information.

Please reply with new IOREG.save after implementing both files under /EFI/Clover/ACPI/patched and rebooting your system.
Thank you so much for the replying. I put the .aml you provide and can show the Ridge details in the PCI Content. However, the link speed seems only 2.5 G/s. Please see the original dsdt and the new ioreg.save from the attachments. Thanks again.
399748
 

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kgp

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Thank you so much for the replying. I put the .aml you provide and can show the Ridge details in the PCI Content. However, the link speed seems only 2.5 G/s. Please see the original dsdt and the new ioreg.save from the attachments. Thanks again.View attachment 399748
TB SSDT is properly implemented now. The rest might depend on your BIOS settings or factory default PCIe slot implementation. Actual TB PCIe bandwidth should be the same with and without SSDT implementation. Your PCIe slot must support PCI 3.0 to achieve the expected 8.0GT/s. Nothing else I could do from my side. Following your IOREG.save, you apparently miss also all other SSDTs for your current PCIe system implementation.

Good luck,

KGP
 
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TB SSDT is properly implemented now. The rest might depend on our BIOS settings or factory default PCIe slot implementation. Nothing else I could do from my side. Following your IREOG.save you apparently miss also all other SSDTs for your current PCIe system implementation.

Good luck,

KGP
Thank you so much KGP. Your post is amazing for the x99 and x299 guidance.
 

kgp

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Thank you so much KGP. Your post is amazing for the x99 and x299 guidance.
Thanks for the flowers. BTW.. if you are going to implement the missing SSDTs, note that all PCI devices under the same ACPI address like PCI0.BR2A.H000, but on different PCI bridges, must be part of the same SSDT.

Good luck, my friend!

KGP
 
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