How to build your own iMac Pro [Successful Build/Extended Guide]

Discussion in 'High Sierra Desktop Guides' started by kgp, Aug 13, 2017.

  1. kgp

    kgp

    Joined:
    May 30, 2014
    Messages:
    4,478
    Motherboard:
    Asus Prime X299 Deluxe, Asus X99-A II
    CPU:
    Intel i9-7980XE, Intel I7-6950X
    Graphics:
    AORUS GTX 1080 TI-X WB, AORUS GTX 1080 TI-X
    Mac:
    iMac, MacBook Pro, Mac mini
    Mobile Phone:
    iOS
    Aug 13, 2017 at 2:48 PM #1
    kgp

    kgp

    Joined:
    May 30, 2014
    Messages:
    4,478
    Motherboard:
    Asus Prime X299 Deluxe, Asus X99-A II
    CPU:
    Intel i9-7980XE, Intel I7-6950X
    Graphics:
    AORUS GTX 1080 TI-X WB, AORUS GTX 1080 TI-X
    Mac:
    iMac, MacBook Pro, Mac mini
    Mobile Phone:
    iOS
    cover-nice-small.png

    Successfully running my iMac Pro Skylake-X/X299 Build with macOS High Sierra 10.13.6 (17G65) - Final Release!

    X299-10.13.6.png


    Abstract and Introduction:

    This originating post constitutes a new macOS 10.13 High Sierra Desktop Guide for Skylake-X/X299, which certainly can still grow and improve by your estimated user feedback. This Skylake-X/X299 10.13 High Sierra Desktop Guide bases on the ASUS Prime X299 Deluxe. However, also other X299 ASUS mainboard models or X299 mainboards of other brands might be compatible with this guide after likely considering and implementing few mandatory modifications not accounted by this guide (see post #5079 for further clarifications). The i7-7800X (6-core) was chosen as the Skylake-X Startup Configuration Model in order to minimise the guide development costs. It has been replaced within the goal configuration by the i9-7980XE (18 core). All other Skylake-X models compatible with this guide are detailed in the figure below.

    Skylake-X-Guide-Compatibility.png

    Carefully consider, which Skylake-X model might be the correct choice for your specific needs. Also please take note of the following limitations:

    a.) The i7-7640X and 7740X only support two channels DDR4-2666 and only posses 16 PCI express 3.0 lanes, which are already used up by implementing a state-of-the-art 16 lane PCIe graphics adapter. Thus, there are no further PCI express 3.0 lanes for using PCIe NVMe drives or additional PCIe adapters!

    b.) The i7-7800X and i7-7820X already support four channels DDR4-2666 but however also possess only 28 PCI express 3.0 lanes! Thus by using a state-of-the-art 16 lane PCIe graphics adapter and a PCIe NVMe drive, there are nearly no PCI express 3.0 lanes remaining. When adding one or two additional PCIe adapters, one exceeds the 28 available PCI express 3.0 lanes by far! In this case, the resulting configuration might be error-prone!

    c.) Thus, considering a.) and b.), I strongly recommend to start at least with the i9-7900X, which already supports four channels DDR4-2666 and also implements 44 PCI express 3.0 lanes

    Further note, that for all Skylake-X processors, a sophisticated liquid cooling system is absolutely mandatory! For stock speeds something like the Corsair H115i might by sufficient. However, if somebody aims at OverClocking (OC) of the i9-7900X or Skylake-X Processors above, sophisticated Water Blocks for CPU and VRM of e.g. EKWB seem absolutely mandatory and unavoidable.

    My Skylake-X/X299 System is up, fully stable and fully functional apart from the yet non-functional onboard WLAN (WIFI) module (chipset not natively supported by OS X). For Wifi, I therefore use the OSX WIFI PCIe Adapter instead.

    Thanks to a very recent iMac Pro dump performed by @TheOfficialGypsy, we now have been able to successfully implement the necessary iMacPro1,1 details in both Clover_v2.4k_r4369 (thanks to Sherlocks) and Clover Configurator v4.60.0.0 (SMBIOS details, thanks to Mackie100) by beginning of January 2018. In collaboration with @macandrea we first achieved the direct implementation of macOSHigh Sierra 10.13.2 (17C2120), and now also the direct implementation of macOSHigh Sierra 10.13.6 (17G65), which can be subsequently updated to macOSHigh Sierra 10.13.6 Public Beta 2 (17G39b) via the Appstore.

    Note that with AptioMemoryFix.efi, the new Skylake/X299 iMac Pro build now also features fully native NVRAM support. No need for EmuVariableUefi-64.efi in /EFI/Clover/drivers64UEFI/ to properly transmit the SMBIOS iMacPro1,1 credentials to Apple.

    We also reached Native Display Brightness Control / Native NightShift Functionality for Monitors with DCC/IC Support like the LG 38 inch display thanks to users @Bendge and @Ramalama.


    Since 10.13 SU and with AppleIntelPCHPMC, Apple now e.g. implements IOPCIPrimaryMatchID "a2af8068" and AppleUSBXHCISPT on the ASUS Prime X299 Deluxe. All external and internal XHC USB 3.0 (USB 3.1 Gen 1 Type-A) and USB 2.0 (USB 2.0 Gen 1 Type-A) ports should work at expected data transfer rates on all X299 mainboards. All external and internal USB 3.1 (USB 3.1 Gen 2 Type-A and Type-C) ports are anyway natively implemented on different controllers than XHC and also work at expected data rates. Anybody unhappy with the current XHC USB OSX implementation can create a board specific XHC USB Kext by following my XHC USB Kext guideline to be accessed at https://www.tonymacx86.com/threads/macos-high-sierra-10-13-xhc-usb-kext-creation-guideline.242999/.

    Also the ASUS Thunderbolt EX3 Extension Card is now fully implemented including TB XHC USB and TB hot plug functionality. External Thunderbolt drives connected via Apples Thunderbolt 3 to Thunderbolt 2 Adapter work at expected data rates and speeds. The same states for all USB 3.1 Gen 2 Type-A and Type-C devices (see Section E.5 of my guide)!

    Note that opposite to my previous EFI-Folder distributions, EFI-X299-10.13.6-Release-iMacPro1,1-110718.zip does not contain any default audio configuration. You have to implement the audio approach of your choice during the Post Installation process in Section E.)! You can select between three possible audio implementations detailed in section E.3): 1.) The AppleALC audio approach (section E.3.1) bases on AppleALC.kext v1.2.7 and Lilu.kext v1.2.4 and could be implemented thanks to the extensive efforts and brilliant work of @vit9696, @apfelnico 2.) The VoodooHDA audio approach (section E.3.2) bases on the VoodooHDA.kext v2.9.0d10 and VoodooHDA.prefPane v1.2. 3.) Finally, @toleda 's cloverALC audio approach (section E.3.3) bases on the realtekALC.kext v2.8 and on an additional pathing of the native vanilla AppleHDA.kext in the /S/L/E/ directory of the System Disk and has been successfully implemented thanks to the instructions and help of @Ramalama. The correct HDAU HDMI/DP digital Audio PCI implementation will be detailed in Section E.9) of this guide in line with the HDEF and GPU PCI device implementation.

    The ASUS Prime X299 Deluxe on-board Bluetooth is natively supported and also Bluetooth Audio works OoB, however due to the non-functionality of the ASUS Prime X299 Deluxe on-board Wifi Module, I also use the Bluetooth 4.0 module of the OSX WIFI PCIe Adapter, which in line with its natively supported Wifi-module also provides native Airdrop, native Handoff and native Continuity as well as keyboard support in BIOS/UEFI and Clover Boot Loader. A full-featured alternative and more budget friendly BT/WIFI solution is the ABWB 802,11 AC WI-FI + Bluetooth 4.0 PCI-Express (PCI-E) BCM94360CD Combo PCIe Adapter of Flughafen Computer especially for our friends in Europe (thanks to @DSM2 for providing this information).

    Thanks to the SmallTree-Intel-211-AT-PCIe-GBE.kext, also the Intel I211_AT Gigabit on-board LAN controller of the ASUS Prime X299 Deluxe is now correctly implemented and fully functional, in addition to the anyway natively implemented and of course also fully operational Intel I219-V Gigabyte on-board LAN controller of the Asus Prime X299 Deluxe (see Section E.8 of my guide).

    In May 2018, @mm2margeret pointed me even to a fully working 10GBit Lan Solution (thanks to @mikeboss, @d5aquep and @Mieze) based on the ASUS XG-C100C 10-Gigabit Ethernet PCIe x4 Adapter. The latter adapter employs the same Aquantia AQC107 chip like the iMac Pro. How to successfully implement and run the ASUS XG-C100C is detailed in Sections E.8.2.1) and E.9.9). In addition, I also successfully implemented and tested the Intel X540-T1 single port 10GBit LAN PCIe Adapter after some Ubuntu modding of it's EEPROM to be compatible with the Small-Tree 10GB macOS 10.13 driver (see Sections E.8.2.2 and E.9.9 ). I now however use this latter adapter in my X99 rig. The Small-Tree P2EI0G-2T 2-Port 10GB LAN PCIe Adapter constitutes my actual 10GBit LAN implementation, working OoB with the Small-Tree 10GB macOS 10.13 driver. The 10Gbit NIC connects with a NetGear ProSave XS508M 8-port 10GBit switch, which further connects with a QNAP TS-431X2 Quad-core 4-Bay NAS tower with Built-in 10GbE SFP+ Port that harbours 4x 12 TB Seagate IronWolf in RAID 0 configuration (optimised for read/write speed). Let me express my gratitude to @gxsolace at this place for providing me with 1x Intel X540-T1, 1x Small-tree P2EI0G-2T and 4x 12 TB Seagate IronWolf hardware. You are just awesome!

    Excellent news concerning CPU Power Management: ASUS, MSI and ASROCK mainboards allow now for manually unlocking the MSR 0xE2 BIOS Register along their X299 mainboard series. The MSR 0xE2 BIOS Register of all Gigabyte mainboards is anyway unlocked by factory default. The manual unlocking of BIOS 1301 for the ASUS Prime Deluxe however still causes issues with respect to sleep/wake functionality and Skylake-X TSC. Therefore we have to enable the MSR lock in the BIOS settings but patch in advance the 1301 BIOS firmware by means of 3 patches provided by @interferenc. By this we achieve fully native HWP (Intel SpeedShift Technology) CPU Power Management for all Skylake-X processors on all mainboards with unlocked MSR 0xE2 BIOS Register, resulting in absolutely brilliant and top-end CPU performance (see Section E.1). With all unpatched mainboards we witness however some TSC desynchronisation of the Skylake-X threads at boot and wake from S3. Until further microcode updates are performed by the mainboard manufacturers, we therefore have to use the TSCAdjustRest.kext provided by @interferenc in this case.

    Outstanding historical Skylake-X/X299 iMac pro Benchmark Scores finally also depict the excellent overall build and and system performance:

    Geekbench i9-7980XE (4.8GHz) CPU Benchmark:
    • Multi-Core Sore: 65.348
    • Single-Core Sore: 5.910
    Cinebench i9-7980XE (4.8GHz) CPU Benchmark:
    • 4.618 CB
    Geekbench Gigabyte Nvidia GeForce GTX 1080 Ti WaterForce WB 11GB Xtreme Edition OpenGL and Metal2 Benchmark:
    • OpenGL Sore: 229.965
    • Metal 2 Sore: 242.393

    See Sections F.1) and F.2) for further details.

    All Skylake-X Systems harbouring a mainboard with unlocked MSR 0xE2 BIOS Register now also posses fully native forced and automated Sleep/Wake Functionality not only thanks too a fully developed SSDT implementation and respective ACPI replacements.

    Good new also for all users of C422 and XEON-W System. This guide seems also fully compatible with your systems, see post #2228.

    Before starting with all detailed instructions, please find a Table of Content that provides an overview of the individual topics addressed within this guide:

    Table of Contents

    A.) Hardware Overview
    Details about the build configuration that states the baseline of this guide.

    B.) Mainboard BIOS
    B1.) ASUS BIOS Configuration
    B2.) Gigabyte BIOS Configuration

    C.) Important General Note/Advice and Error Prevention
    Hardware and System Configuration recommendations. Make sure you've read all of this before complaining that something does not work.

    D.) iMac Pro macOS 10.13 High Sierra System Setup

    This chapter includes a general guideline how to perform the initial setup of your iMac Pro with macOS High Sierra 10.13.6 (17G65). Note that the macOS High Sierra 10.13.6 (17G65) full package installer apparently can be only successfully downloaded on non-iMacPro systems. For iMacPro systems, there we provide a sophisticated workaround that bases on pristine sources from Apple.
    D.1) iMac Pro EFI-Folder Preparation
    D.2) iMac Pro macOS High Sierra 10.13.6 (17G65) Installer Package Creation
    D.3) iMac Pro macOS High Sierra 10.13.6 (17G65) USB Flash Drive Installer Creation
    D.4) iMac Pro macOS High Sierra 10.13.6 (17G65) Clean Install on Skylake-X/X299
    D.5) Direct iMac Pro conversions of a functional Skylake-X/X299 system with a SMBIOS System Definition different from iMacPro1,1 and a standard macOS build implementation
    D.6) iMac Pro macOS High Sierra Build Update Procedure

    E.) Post Installation Process
    E.1) HWP (Intel SpeedShift Technology) CPU Power Management Configuration
    E.2) Graphics Configuration
    General ATI and Nvidia GPU advices including a detailed guideline for Nvidia Web Driver Installation and Black Screen Prevention
    E.3) Audio Configuration
    Use only one of the following, where E.3.1 is recommended by the author.
    E.3.1.) AppleALC Audio Implementation
    E.3.2) VoodooHDA Audio Implementation
    E.3.3) cloverALC Audio Implementation
    E.4) USB Configuration
    including some initial benchmarks
    E.5) ASUS Prime X299 Deluxe Thunderbolt EX3 PCIe Add-On Implementation
    E.6) NVMe compatibility
    E.7.) SSD/NVMe TRIM Support
    Extend the life of your SSD and maintained its normal speed
    E.8) Gbit and 10-Gbit Ethernet Implementations
    E.8.1) ASUS Prime X299 Deluxe on-board Gbit Ethernet Functionality
    E.8.2) 10-Gbit LAN Implementations
    E.8.2.1) ASUS XG-C100C Aquantia AQC107 10-Gbit NIC
    E.8.2.2) Intel X540-T1 10-Gbit NIC
    E.8.2.3) Small-Tree P2EI0G-2T 10-Gbit NIC
    E.8.2.4) NetGear ProSave XS508M 8-port 10-Gbit Switch
    E.8.2.5) QNAP TS-431X2 Quad-core 4-Bay NAS tower
    E.8.2.6) 10-GBit Ethernet Optimisation

    E.9) ASUS Prime X299 Deluxe PCI Device Implementation
    E.9.1) ACPI DSDT Replacement Implementation
    E.9.2) SSDT-X299-iMacPro.aml PCI Implementation
    E.9.2.1) - HDEF - onboard PCI Audio Controller PCI Implementation
    E.9.2.2) - GFX0, HDAU - Nvidia Graphics Card and HDMI/DP Audio PCI implementation
    E.9.2.3) - PMCR - onboard Power Management Controller (PMC) PCI Implementation
    E.9.2.4) - USBX - fixing XHCI USB Power errors during Boot
    E.9.2.5) - XHCI - onboard Extended Host Controller Interface (XHCI) PCI Implementation
    E.9.2.6) - XHC2,3,4 - ASMedia ASM3142 USB 3.1 Controller PCI Implementation
    E.9.2.7) - ANS1, ANS2 - Apple NVMe Controller PCI Implementation
    E.9.2.8) - SAT1 - Intel AHCI SATA Controller PCI Implementation
    E.9.2.9) XGBE - 10GBit NIC Implementation
    E.9.2.10) - ETH0/ETH1 - onboard LAN Controller PCI Implementation
    E.9.2.11) - ARPT - OSX WIFI Broadcom BCM94360CD 802.11 a/b/g/n/ac + Bluetooth 4.0 AirPort Controller PCI Implementation
    E.9.2.12) - DTGP Method
    E.9.2.13) - Debugging Sleep Issues
    E.9.3) SSDT-X299-TB3-iMacPro.aml PCI Implementation
    E.10) System Overview CPU Cosmetics
    E.11) iMac Pro Boot Splash Screen Cosmetics
    E.12) iMac Pro Desktop Background cosmetics
    E.13) Native Display Brightness Control / Native NightShift Functionality for Monitors with DCC/IC Support
    E.14) Logic-X and Audio Studio Software Functionality
    E.15) iStatMenus Hardware Monitoring

    F.) Benchmarking
    F.1) Sylake-X Intel I9-7980XE CPU Benchmarking
    F.2) Gigabyte AORUS GTX 1080 Ti Waterforce EB 11GB Extreme Edition Benchmarking

    G.) Summary and Conclusion

    Now enjoy and have have fun with the detailed guidelines below. Many thanks to @paulotex for committing the efforts in providing the Table of Contents detailed above.


    A.) Hardware Overview

    Tower-small.png

    build.png

    Mainboard: Asus Prime X299 Deluxe [380€]
    CPU: i9-7980XE (18 core, 4.4Ghz) [1.900€]
    RAM Memory: Tridentz DDR-4 3200 Mhz 128GB (8x16GB) Kit (F4-3200C14Q2-128GTZSW) [1.400€]
    GPU: Gigabyte Aorus GTX 1080 Ti Waterforce WB Extreme Edition 11GB [900€]
    System Disks: EVO 960 NVMe M.2 1TB (system disk macOS High Sierra 10.13.3) [450€]; EVO 960 NVMe M.2 1TB (system disk macOS Sierra 10.12.6 Sierra) [450€]
    Power Supply: Corsair AX1500i [450€]
    Monitor: LG 38UC99-W 38" curved 21:9 Ultra Wide QHD+ IPS Display (3840 pix x 1600 pix) [1.350€]
    WebCam: Logitech C930e [80€]
    Mouse: Apple Magic Mouse 2 [75€]
    Keyboard: Apple Magic Keyboard Wireless [99€]
    Bluetooth + Wifi: PC/HACKINTOSH - APPLE BROADCOM BCM94360CD - 802.11 A/B/G/N/AC + BLUETOOTH 4.0 [129€]
    Internal USB2.0 HUB: NZXT AC-IUSBH-M1T [20€]
    Case: Thermaltake Core X71 Tempered Glass Edition Full Tower Chassis [140€]

    10Gbit Ethernet
    components:
    - 1x ASUS XG-C100C AQC107 PCIe x4 10GBit LAN Adapter (for testing purposes)
    - 1x Intel X540-T1 single port 10GBit LAN PCIe Adapter (for testing purposes, now installed in my X99 rig)
    - 1x Small-Tree P2EI0G-2T 2-Port 10GBit LAN PCIe Adapter (now default configuration)
    - 1x NetGear ProSave XS508M 8-port 10GBit switch
    - 1x QNAP TS-431X2 Quad-core 4-Bay NAS tower with Built-in 10GbE SFP+ Port and 4x 12 TB Seagate IronWolf in RAID 0 configuration.

    Let me express once more my gratitude to @gxsolace at this place for providing me with 1x Intel X540-T1, 1x Small-tree P2EI0G-2T and 4x 12 TB Seagate IronWolf hardware.

    CPU/GPU Cooling: Water Cooling main components:
    - 1x EK-FB ASUS Prime X299 RGB Monoblock - Nickel [117€]
    - 1x EK-CoolStream PE 360 (Triple, 39 mm, Roof) [80€]
    - 1x EK-CoolStream Ce 280 (Dual, 45mm, Front) [90€]
    - 2x EK-CoolStream XE 360 (Triple, 60 mm, Cellar) [220€]
    - 1x XSPC Twin D5 Dual Bay Reservoir/Pump Combo [209€]
    - 15x Thermaltake Riing 12 High Static Pressure LED Radiator Fan (120mm) [210€]
    - 5x Thermaltake Riing 14 High Static Pressure LED Radiator Fan (140mm) [100€]
    - 3x Phantek PMW Fan Hub (up to 12 fans or 30W power consumption) [17€]
    - 1x Alphacool Eisflügel Flow Indicator Black G1/4 IG [16€]
    - 1x Phobya Temperatur Sensor G1/4 + C/F Display [22€]

    Watercooling-main.png

    Most of the components purchased at Amazon.de, Caseking.de, Mindfactory.de, Alernate.de

    Costs: 8904€

    Compared with:

    iMacPro.png

    B.) Mainboard BIOS

    On a real Mac with native OSX XCPM power management, the MSR 0xE2 register is unlocked and therefore writeable. However, on ASUS mobos this register was usually read only for ages. When the kernel tried to write to this locked register, it caused a kernel panic. This panic could happen very early in the boot process, with the result that the system freezes or reboots during the boot process. We could circumvent the MSR 0xE2 register write with a dedicated KernelToPatch entry in the config.plist, namely "xcpm_core_scope_msrs © Pike R. Alpha" and by enabling the "KernelPM" in the config.plist in Section "Kernel and Kext Patches" of the Clover Configurator.

    Thanks to recent modifications in CodeRush's Longsoft UEFIPatch distributions and thanks to three sophisticated MSR 0xE2 Register patches provided by @interferenc (partly former work of CodeRush, Pike Alpha and Adrian_dsl), we were able to successfully patch any ASUS X299 mainboard BIOS firmware distribution and unlock the MSR 0xE2 register. The patched ASUS mainboard BIOS firmware finally has been uploaded to the specific ASUS X299 mainboard by means of the ASUS EZ BIOS Flashback Procedure. This made the "xcpm_core_scope_msrs © Pike R. Alpha" KernelToPatch entry obsolete and allowed full native read/write MSR 0xE2 register access by the OSX kernel.

    Within ASUS Prime X299 Deluxe BIOS firmware 1301 and 1401, ASUS now allows upon my user request for the first time to manually unlock the MSR 0xE2 register within the most recent BIOS settings. This makes the ASUS BIOS firmware patching obsolete. MSI and ASRock X299 mainboards allowed the manual unlock of the MSR 0xE2 BIOS Register right from the beginning and the MSR 0xE2 BIOS Register of all Gigabyte mainboards is anyway unlocked by factory default. However, yet we witness some TSC desynchronisation of the Skylake-X threads at boot and wake from S3. Until further microcode updates are performed by the mainboard manufacturers, we therefore have to use the TSCAdjustRest.kext provided by @inteferenc (see error prevention C.4 of this guide) to circumvent this TSC desynchronisation issue.

    By this we achieve fully native HWP (Intel SpeedShift Technology) CPU Power Management for all Skylake-X processors on all X299 mainboards with unlocked MSR 0xE2 BIOS Register, resulting in absolutely brilliant and top-end CPU performance (see Section E.1).

    Before summarising all necessary ASUS and Gigabyte BIOS settings, let me provide X299D.CAP, the most recent ASUS Prime X299 Deluxe BIOS Firmware 1401 with an iMacPro Splash Screen Image (see Section E.11), which can be flashed by means of the well known ASUS EZ BIOS Flashback procedure.


    B1.) ASUS BIOS Configuration

    Before applying the specific settings, please provide your ASUS X299 Prime Deluxe with the most actual BIOS firmware 1301.

    ASUS-BIOS-Basic.png

    After Updating System time and System Date, enable X.M.P for your DDR4 modules. Don't forget to enable the EZ XMP Switch previously to this step on your ASUS Mainboard! Subsequently switch form the easy to the advanced ASUS BIOS Setup mode by pressing F7.

    ASUS-BIOS-Advanced.jpg

    I use all optimized BIOS settings (OoB, no OC yet) despite a few changes listed in detail below:

    1.) /AI Tweaker/
    a.) ASUS MultiCore Enhancement: Auto [optional "Disabled", see important notification below!]
    b.) AVX Instruction Core Ratio Negative Offset: "3" [optional "Auto", see important notification below!]
    c.) AVX-512 Instruction Core Ratio Negative Offset: "2" [optional "Auto", see important notification below!]
    d.) CPU Core Ratio: Sync All Cores [optional "Auto", see important notification below!]
    e.) CPU SVID Support: Enabled [fundamental for proper IPG CPU power consumption display]
    f.) DRAM Frequency: DDR4-3200MHz

    2.) /Advanced/CPU Configuration/
    a.) Hyper Threading [ALL]: Enabled
    b.) MSR Lock Control: Disabled

    3.) /Advanced/CPU Configuration/CPU Power Management Configuration/
    a.) Enhanced Intel Speed Step Technology (EIST): Enabled
    b.) Autonomous Core C-States: Enabled
    c.) Enhanced Halt State (C1E): Enabled
    d.) CPU C6 report: Enabled
    e.) Package C-State: C6(non retention) state
    f.) Intel SpeedShift Technology: Enabled (crucial for native HWP Intel SpeedShift Technology CPU Power Management)
    g.) MFC Mode Override: OS Native

    4.) /Advanced/Platform Misc Configuration/
    a.) PCI Express Native Power Management: Disabled
    b.) PCH DMI ASPM: Disabled
    d.) ASPM: Disabled
    e.) DMI Link ASPM Control: Disabled
    f.) PEG - ASMP: Disabled

    5.) /Advanced/System Agent Configuration/
    a.) Intel VT for Directed I/O (VT-d): Disabled (see VT-d notification below)

    6.) /Boot/
    a.) Fast Boot: Disabled
    b.) Above 4G Decoding: Off
    c.) Set your specific Boot Option Priorities

    7.) /Boot/Boot Configuration
    a.) Boot Logo Display: Auto (important for E.11 - ASUS Boot Splash Screen Cosmetics)
    b.) Boot up NumLock State: Disabled
    c.) Setup Mode: Advanced

    8.) /Boot/Compatibility Support Module/
    a.) Launch CSM: Disabled

    9.) /Boot/Secure Boot/
    a.) OS Type: Other OS

    With F7 and F10 you can save the modified BIOS settings.

    Important Notes:

    "ASUS MultiCore Enhancement": When set to "Auto", MCE allows you to maximise the overclocking performance optimised by the ASUS core ratio settings. When disabled, MCE allows to set to default core ratio settings.

    "CPU Core Ratio - Sync All Cores": Tremendous increase in CPU performance can be achieved with the CPU Core Ratio set to "Sync All Cores". In case of i9-7980XE stock settings (max. turbo 4.4 Ghz), the Geekbench score difference is approx. 51.000 (disabled) compared to 58.000 (enabled)! Note however, that Sync All Cores should be used only in case of the availability of an excellent and extremely sophisticated water cooling system! Otherwise, CPU Core Ratio should be set to "Auto". Further note that with CPU Core Ratio set to "Sync All Cores", the AVX Instruction Core Ratio Negative Offset must be set to "3" and the AVX-512 Instruction Core Ratio Negative Offset must be set to "2". Without the correct core ratio offsets, your system might become unstable with CPU Core Ratio set to "Sync All Cores"!

    VT-d Note: For compatibility with VM or parallels, VT-d can be also ENABLED... Verify however, in this case that in your config.plist the boot flag "dart=0" is checked under Arguments in the "Boot" Section of Clover Configurator! However, it might well be that the "dart=0" boot flag is already obsolete.

    Intel(R) Power Gadget (IPG) CPU Power Consumption note: for the proper display of the CPU Power Consumption in e.g. the Intel(R) Power Gadget it is absolutely mandatory to enable both /AI Tweaker/CPU SVID Support/.

    CPU Core Voltage Correction for ASUS X299 mainboard users: The ASUS Skylake-X BIOS microcode implementation has improved considerably. Former issues with "/AI Tweaker/CPU Core Voltage/" set to "Auto", where the assigned CPU Core Voltages have been too high by far, have been totally removed.

    CPU-Core-Voltage-Auto.png

    At least with the i9-7980XE it is not anymore necessary to fix the CPU Core Voltage in the ASUS mainboard BIOS to a minimum value that still provides flawless system boot and full system performance during CPU max. load conditions in line with significantly CPU core temperatures, as detailed below. However, for the sake of completeness I did not remove the respective description so far. With CPU max. load conditions, I refer to the max. turbo frequency (e.g. 4.4 Ghz for the i9-7980XE) applied to ALL cores!

    Iterative manual approach to derive minimal CPU Core Voltages:


    This iterative approach detailed assumes the BIOS settings described in Section B1) - point 1) to 10), however by considering the following else optional settings:

    i.) "ASUS MultiCore Enhancement" set to "Auto"
    ii.) "CPU Core Ratio" set to "Sync All Cores"
    iii.) "AVX Instruction Core Ratio Negative Offset" set to "3"
    iv.) "AVX-512 Instruction Core Ratio Negative Offset" set to "2"

    1.) Boot into Windows and launch ASUS CPU-Z as well as Cinebench.

    2.) Run Cinebench CPU benchmarks and watch the Core VID values in CPU-Z under CPU max.load conditions. These values will usually exceed 1.2V with "/AI Tweaker/CPU Core Voltage/" set to "Auto".

    cpu-z-cinebench.png

    3.) To optimise the "/AI Tweaker/CPU Core Voltage/" perform the following steps:

    a.) Enter the BIOS, go to "/AI Tweaker/CPU Core Voltage/" and change from "Auto" to "Manual"

    b.) Enter a slightly lower CPU Core Voltage Overrride (e.g. typically 0.01 V less) than originally observed with CPU-Z under Cinebench CPU benchmark max.load conditions in Windows, e.g. 1.190 V in the first iteration.

    CPU-Core-Voltage-Overrride.png

    c.) Reboot into windows and check if the Cinebench CPU benchmark scores are still in the expected range by also controlling the respective Core VID values during the Cinebench CPU benchmark max. load conditions

    d.) Repeat b.) and c.) until either your Cinebench CPU benchmarks scores start to significantly decrease or you start facing problems in booting your system.

    Given my personal experience with the i9-7980XE, a CPU Core Voltage Override of 1.120 V was optimal for a stock 4.4 GHz stock turbo frequency. In case of OC, the minimal CPU Core Voltage easily exceeded 1.2 V.

    Warning!

    Before performing the CPU Core Voltage Override Value Optimisation Approach, save your actual BIOS settings to a USB Drive. If during the iterative approach you are not able to successfully boot your system, perform a CMOS reset and restore your BIOS settings from the USB Drive, by subsequently entering the last successful CPU Core Voltage Override value!

    Too high voltages can severely damage your CPU! In any case, when performing OC, a sophisticated water block circuit is absolutely mandatory! Always watch also your CPU temps when performing the CPU Core Voltage Optimisation, which should not exceed 90 deg C under CPU max. load conditions!

    Many thanks to @DSM2 for all his comments, valuable input, and proposed solutions.


    B.2) - Gigabyte BIOS Configuration

    Please find below the BIOS settings for the Gigabyte Designare EX kindly provided by @jyavenard and @DSM2.

    Gigabyte.jpg

    1.) /M.I.T/Advanced Frequency Settings/
    a.) Extreme Memory Profile: (X.M.P): Profile1

    2.) /M.I.T/Advanced Frequency Settings/Advanced CPU Core Settings

    a.) Active Cores Control: Auto
    b.) Hyper-Threading Technology: Enabled
    c.) Intel Turbo Boost Max Technology 3.0 : Enabled
    d.) Intel Speed Shift Technology : Enabled
    e.) Enhanced Multi-Core Performance: enabled/disabled (optional; consider warning in Section B.2) - ASUS BIOS Settings)
    f.) CPU Enhanced Halt (C1E): Enabled
    g.) C6/C7 State Support: Enabled
    h.) Package C State limit: C6
    i.) CPU EIST Function: Enabled
    j.) Energy Efficient Turbo : Disabled

    3.) /M.I.T/Advanced Memory Settings/
    a.) Extreme Memory Profile (X.M.P): Profile1

    4.) /BIOS/
    a.) Boot Numlock State: Disabled/Enabled (optional)
    b.) Security option: Setup
    c.) Full Screen Logo Show: Enbabled
    d.) Fast Boot: Disabled
    e.) CSM Support: Disabled

    5.) /BIOS/Secure Boot/
    a.) Secure Boot Enable: Disabled

    6.) /Peripherals/USB Configuration/
    a.) XHCI Hand-off: Enabled

    7.) /Peripheral/Thunderbolt Configuration/ (Designare EX only)
    a.) Security Level : SL0 - No Security

    8.) /Chipset/
    a.) VT-d: Disabled/Enabled (optional, see VT-d notification in Section B.2) - ASUS BIOS settings )

    9.) /Save& Exit/
    a.) Save & Exit


    C.) Important General Note/Advice and Error Prevention

    Please note the following important General Note / Advice and Error Prevention, when setting up your Skylake-X/X299 System and implementing the latest macOS High Sierra distribution.

    1.) The /EFI/Clover/drivers64UEFI/-directory of EFI-X299-10.13.6-Release-iMacPro1,1-110718.zip contains by default AptioMemoryFix.efi thanks to @vit9696. Note that with Clover_v2.4k_r4392, AptioMemoryFix.efi has become an official Customization Option of Clover and can now be selected and therefore also just easily implemented in the frame of the Clover Boot Loader Installation.

    For native NVRAM implementation, Clover's RC Scripts have to be omitted during the clover boot loader installation. If already previously installed, remove Clover's RC Scripts from the /etc directory of your macOS USB Flash Drive Installer or System Disk:

    Code (Text):
    sudo rm -rf /etc/rc.boot.d
    sudo rm -rf /etc/rc.shutdown.d

    Also the "slide" boot flag needs to be disabled.

    2.a.) Most ATI GPUs, e.g. RX Vega 64, RX Vega Frontier, RX 580, RX 560 are natively implemented. However, it is commonly recommended not to use RX 560 and RX 580 GPUs due to the lacking iGPU implementation when using SMBIOS iMacPro1,1. Remaining HDMI/DP port errors, hot plug errors and flaws with multi-monitor or 5K display configurations when using ATI Vega GPUs can be fixed by means of VegaGraphicsFixup.kext, kindly provided by @jyavenard. Important comment for all Vega users with 4K monitors though: when connecting e.g. the Vega Frontier with e.g. the LG 38UC99-W (WUHD, 3840 pix x 1600 pix) via one of the Display Ports (DPs), the screen resolution is fine under both Windows 10 and macOS High Sierra but is totally at odd during boot (VGA like boot screen resolution). @DSM2 reported similar issues with his true 4K display and with both the ASUS Prime X299 Deluxe and the Gigabyte Designare EX. Thus the VEGA DP 4K boot screen resolution issue is neither related with the fact that the LG 38UC99-W is a ultra-wide (3840x1600) and not a true UHD (3840x2160) monitor nor related to any likely apparent issue with the ASUS Prime X299 Deluxe firmware. It is definitely a Vega firmware problem in combination with 4K displays, as the DP 4K boot screen resolution issue is totally absent with my Nvidia GPU and the problem also does not only affect the ASUS Splash Screen but also spreads over the entire boot process until the login screen is reached (Windows and macOS). Splash Screen, Apple logo or verbose boot messages are not stretched but rather have VGA like resolution. Any fix of the AMD vBIOS would be highly appreciated. It is more than disappointing to witness such issues with 1000$ GPUs... Fortunately, the 4K boot screen issue is restricted to the Vega DP ports and likely due to the fact that the LG 38UC99-W only supports DP 1.2. Solution: Connect your Vega and your 4K display via the HDMI port. Although, in the latter case the monitor frequency seems to be limited to 30 Hz, compared with the 60 Hz or 75 Hz under macOS Mojave obtained within a DP connection.

    b.) Also Nvidia Kepler Graphics Cards are natively implemented.

    c.) All Users with Maxwell and Pascal Nvidia Graphics Cards Users and SMBIOS MacPro1,1 can employ officially distributed Nvidia 10.13 Web Drivers for their Nvidia Pascal and Maxwell graphics cards! Upon my request from 7 January 2018, Nvidia officially released first WebDriver-387.10.10.10.25.105 for 10.13.2 (17C2120) and first WebDriver-387.10.10.10.25.106 for 10.13.2 SA (17C2205) - Supplemental Update on 11 January 2018. On 25 January 2018, Nvidia released a Web Driver 387.10.10.10.25.157 for 10.13.3 (17D2047), which worked flawless with Pascal GPUs (lagging issues have been reported for Maxwell GPUs). On 20 February 2018, Nvidia released a Web Diver 387.10.10.10.30.159 for 10.13.3 SA (17D2102). On 31 March 2018 and 18 April 2018, Nvidia also released Web Driver 387.10.10.10.30.103 and 387.10.10.10.30.106 for 10.13.4 (17E199). On 25 April 2018, Web Driver 387.10.10.10.30.107 has been released for 10.13.4 SU (17E202). On 02 June 2018, finally we Driver 387.10.10.10.35.106 followed for 10.13.5 (17F77). On 11 July 2018, Nvidia released final 10.13.6 (17G65) WebDriver-387.10.10.10.40.105 .

    3.) Avoid any MacOS assignments in KextToPatch and KernelToPatch entries implemented in the "Kernel and Kext Patches" Section of the Clover Configurator. If subsequently in my Guide you still find MatchOS assignments in respective figures or text, just ignore all likely yet persistent MatchOS assignments. In the config.plist of the EFI-Folder contained in EFI-X299-10.13.6-Release-iMacPro1,1-110718.zip, all MatchOS assignments have been definitely removed.

    4.) If you have the Thunderbolt EX3 or Gigabyte Alpine Ridge PCIe extension card already successfully connected with your mainboard and properly implemented in your system, disconnect any Thunderbolt device during the macOS installation/upgrade procedure. However, if any Thunderbolt PCIe extension card has not been properly configured and implemented yet in your system, remove the card for the macOS Upgrade or Clean Install procedure.

    5.) Note that on some systems it might be necessary to check the KernelPM Option in the "Kernel and Kext Patches Section" of the Clover Configurator to successfully boot the respective system. Note that in the config.plist of the EFI-Folder attached below, this option is unchecked, as it is not required in case of the ASUS Prime X299 Deluxe.

    6.) The /EFI/Clover/drivers64UEFI/-directory of all former EFI-Folder Distributions contained a patched version of the actual apfs.efi. The actual apfs.efi can be obtained by following the respective guideline detailed below:

    Right-click with your mouse on the "Install macOS High Sierra.app" and select "Show Package Contents" -> click with the mouse on "Contents" and subsequently on "Shared Support" -> double-click with the mouse on "BaseSystem.dmg" for mounting.

    Go to "usr" -> "standalone" -> "i386". Drop the apfs.efi to your Desktop.

    To patch the apfs.efi for non-verbose boot, follow THIS LINK. Credits to @PMheart and @ermac.

    Note however, that the entire apsf.efi approach detailed above recently has become totally obsolete.

    Thanks to the ApfsSupportPkgdeveloped by @acidenthera & Co. and thanks to it's recent implementation to Clover (thanks to @Slice, @Philip Petev & Co.) in form of ApsfDriverLoader.efi, there is no further need of the former apsf.efi in the /EFI/Clover/drivers64UEFI/ directory.

    Screenshot 2018-06-16 at 20.13.18.png

    The actual Clover distribution package including the ApsfDriverLoader.efi can by build by means of the Build_Clover.command available on Gitub. Since Version 4.8.8, the latter script also can be used with 10.14 and Xcode 10 + Xcode 10 Command Line Tools thanks to @vector sigma. By adding

    Code (Text):
    export PATH="/usr/local/bin:/usr/bin:/bin:/usr/sbin:/sbin" && buildclover
    upload_2018-6-16_20-46-24.gif to the script,

    Screenshot 2018-06-16 at 19.22.20.png

    the latter also can be used in case of Brew, QT5, UEFITool or MacPorts implementations like Latex, X11, gcc, etc. not yet fully compatible with 10.14 Mojave. Again thanks to @vector sigma for also providing/enabling this trick/possibility.

    7.) To avoid Skylake-X thread TSC desynchronisation errors during boot and wake from S3 with X299 mainboards, likely induced by yet erroneous Skylake-X BIOS microcode implementations, we need to use TSCAdjustReset.kext provided by @interferenc in the /EFI/CLOVER/kexts/Other/ directory of both USB Flash Drive and System Disk.

    To access TSCAdjustRest.kext, download primarily its source distribution from Github with the following terminal command:

    Code (Text):
    git clone https://github.com/interferenc/TSCAdjustReset
    Subsequently copy the TSCAdjustRest source distribution to your Desktop using the following terminal command:

    Code (Text):
    mv /TSCAdjustReset ~/Desktop


    Now change in the terminal to the TSCAdjustReset source distribution on your Desktop with the following terminal command:

    Code (Text):
    cd ~/Desktop/TSCAdjustReset/
    Now compile the source distribution with Xcode by using the following terminal command:

    Code (Text):
    xcodebuild
    After successful compilation, you will find the TSCAdjustRest.kext in ~/Desktop/TSCAdjustReset/build/Release/

    Please note that the TSCAdjustRest.kext by default is configured for a 8-core CPU (16 threads) like the i7-7820X. To adopt the kext for Skylake-X processers with more or less cores than 8 cores, apply the following approach:

    a.) Right-click with the mouse on the TSCAdjustRest.kext file and select "Show Packet Contents".

    b.) Double-click with the mouse on /contents/ . After a right-click on the "Info.plist" file, select "Open with /Other". Select the TextEdit.app and edit the "Info.plist" file.

    c.) Use the "find"-function of TextEdit.app and search for the term "IOCPUNumber"

    d.) Note that the adequate IOCPUNumber for your particular Skylake-X processor is the number of its threads -1, by always keeping in mind that the number of it's threads is always 2x the number of it's cores.

    Thus in case of the 8 core i7-7820X, the IOCPUNumber is 15 (16 threads - 1).

    Code (Text):
    <key>IOCPUNumber</key>
    <integer>15</integer>
    By following this methodology, the correct IOCPUNumber for the 10-core i9-7900X would be 19 (20 threads -1)

    Code (Text):
    <key>IOCPUNumber</key>
    <integer>19</integer>
    and the IOCPUNumber for the 18-core i9-7980XE would result in 35 (36 threads -1).

    Code (Text):
    <key>IOCPUNumber</key>
    <integer>35</integer>
    e.) After adopting the IOCPUNumber for your particular Skylake-X processor, save the info.plist file and copy the modified TSCAdjustRest.kext to the /EFI/CLOVER/kexts/Other/ - directories of both USB Flash Drive Installer and System Disk and you are save and all done!


    8.) Already during the first Beta Versions of macOS 10.13 High Sierra, Apple forced the beta users to use the new Apple file system APFS in case of a Clean Install/update of MacOS High Sierra 10.13. Also within macOS High Sierra 10.13.6 (17G65) this is the case. Most APSF incompatibilities with available system related software apparently have been already removed. All recent versions of Carbon Copy Cloner (CCC) support the direct cloning of APFS system disks and provide the previously missing option for APFS system backups. Until Boot-Loader Distribution Clover_v2.4k_r4210, it was also impossible to install the Clover Boot-Loader in the EFI-Partition of an APFS System Disk by means of the Clover Boot-Loader Installer Package (the Clover Boot-Loader files had to be added manually). However, all recent Clover Boot-Loader Distributions work absolutely flawless with APFS System Disks.

    In any case, with @Brumbear's UnSolid.kext in the /EFI/Clover/kexts/Other/ directory, OSX is forced to remain with the HFS+ file format when installing or updating to the most recent macOS 10.13 distribution.

    Note that there is no way to convert an APFS disk back to HFS+ without the loss of all data, but one can easily reformat an APFS formatted disk to HFS+ under OSX by using either Apple's Disk Utility App or "diskutil" commands. All you need to do is to previously unmount the APFS volume before erasing it with a journaled HFS+ file system and a GRUB Partition Table (GTP). If you want to maintain the disk's content, perform a backup before erasing the disk with a HFS+ format.

    The application of Apple's Disk utility is straight forward. The "diskutil" equivalent is detailed below:

    In the Terminal app, type:

    Code (Text):
    diskutil list
    In the output which you can read by scrolling back, you will find all internal disks named /dev/disk0, /dev/disk1, depending upon how many physical disks are present in your system.

    Make a note of the disk identifier for the disk you intend to format (you can eliminate risk by removing all disks but the intended target).

    In the Terminal app, type:

    Code (Text):
    diskutil unmount /dev/diskX
    where diskX is a place holder for the disk to be unmounted.

    Now delete the APFS container of diskX:

    Code (Text):
    diskutil apfs deleteContainer /dev/diskX
    Subsequently, you can erase the entire disk with HFS+ and a GPT by typing the following terminal command:

    Code (Text):
    diskutil partitionDisk /dev/diskX 1 GPT jhfs+ "iMacPro" R
    where /dev/diskX is again a place holder for disk to be erased and iMacPro would be the label for the single partition created. The remaining 1 GPT jhfs+ and R arguments tell diskutil to create a single partition, within a GUID partition table, formatted as Journaled HFS+ and using the entire disk, respectively.

    Alternatively one can also use the following terminal command:

    Code (Text):
    diskutil partitionDisk /dev/diskX GPT JHFS+ iMacPro 0b
    where /dev/diskX is again a place holder for disk to be erased and iMacPro is again the label for the disk partition created. The GPT HFFS+ and 0b arguments again tell diskutil to create a single partition, within a GUID partition table, formatted as Journaled HFS+ and covering the entire disk, respectively.

    In the Terminal app, type now:

    Code (Text):
    diskutil mount /dev/diskX
    where diskX is again a place holder for the disk to be remounted.

    Note, that by means of the "diskutil approach", brand new unformatted or not compatibly formatted system NVMe, SSD and HDD system drives can be also directly formatted within the macOS Clean Install procedure. When presented with the initial install screen where you are presented options to Restore From Backup or Install, select Terminal from the Utilities menu bar item;

    The "diskutil" terminal approach is also able to convert a HFS+ macOS High Sierra 10.13 System Disk to APFS. To do so enter the following terminal command:

    Code (Text):
    diskutil apfs convert /dev/diskX
    where diskX is again a place holder for the HFS+ disk to be converted to APFS. The same procedure again can also be directly performed by means of Apple's Disk Utility.

    If you opt for an APFS System Disk implementation, please note that all other disks on your system also should be formatted with APFS. On systems with APFS disks and non-APFS disks, the boot duration will increase, as apsf.efi will perform a fsck check of non-AFPS disks (like HFS+ or Fat32) during boot. However, dual boot APFS Systems with an NTFS Windows System Disk are not effected by the apsf.efi issue, as OSX does not know how to properly deal with NTFS.

    9.) All ASUS Prime X299 Deluxe users, who enabled the second LAN controller in the ASUS Prime X299 Deluxe BIOS, are advised to download, unzip and copy the SmallTree-Intel-211-AT-PCIe-GBE.kext to the EFI-Folders of both USB Flash Drive Installer and 10.13 System Disk, or to disable the second LAN port in the BIOS during the MacOS Installation.

    10.) Lilu and Lilu Plugin distribution remarks:

    To access, download and compile most actual but not yet officially released Lilu and Lilu plugin distributions, follow these links:

    a.) Lilu Source distribution
    b.) AppleALC Source Distribution
    c.) NvidiaGraphicsFixup
    d.) Whatevergreen

    To successfully compile the AppleALC, NvidiaGraphicsFixup and Whatevergreen source code distributions with Xcode 9.4 under macOS High Sierra 10.13.6 (17G65), download, unzip and copy the respective actual Lilu DEBUG distribution to the AppleALC, NvidiaGraphicsFixup and Whatevergreen source code distribution directories. To compile the respective Lilu, AppleALC, and NvidiaGraphicsFixup source code distributions just execute the terminal command "xcodebuild" after changing to the respective source code distribution with the "cd" terminal command. The resulting compiled kexts can be always found in the respective /build/Release/ sub-directories of the respective source code distribution directories.

    Further details to the topic can be accessed by following THIS LINK.

    11.) To clearly get kernel panic images with a call trace in case of kernel panics, I implemented (checked) boot flags "debug=0x100" and "keepsyms=1" in the config.plist of EFI-X299-10.13.6-Release-iMacPro1,1-110718.zip in the "Boot" Section of Clover Configurator under "Arguments".

    12.) Note that in the current EFI-X299-10.13.6-Release-iMacPro1,1-110718.zip distributions, I also removed CsmVideoDxe-64.efi from /EFI/CLOVER/drivers64UEFI, as the latter file is only required for proper Legacy screen resolution purposes with CSM enabled, which is definitely not our case.

    13.) All Gigabite mainboard users need to add the "npci=0x2000" boot flag to their config.plist by checking the latter in Section "Boot" of Clover Configurator under "Arguments".

    D.) iMac Pro macOS 10.13 High Sierra System Setup

    Below, one finds a detailed description for the Clean Install of macOS High Sierra 10.13.6 (17G65) - special iMacPro build (D.4). This also includes the iMacPro EFI-Folder Preparation (D.1) as well as the macOS High Sierra 10.13.6 (17G65) Installer Package (D.2) and macOS macOS High Sierra 10.13.6 (17G65) USB Flash Drive Installer Creation (D.3). One also finds instructions for a direct iMac Pro conversion of a functional Skylake-X/X299 system with a SMBIOS System Definition different from iMacPro1,1 and a standard macOS build implementation (D.5), as well as for the subsequent iMac Pro macOS High Sierra Update Procedure.


    D.1) iMac Pro EFI-Folder Preparation

    In order to successfully boot a macOS USB Flash Drive Installer or System Disk on a Hackintosh system, both drives must be equipped with an EFI-Folder in their EFI partitions. In this Section we will prepare a fully equipped EFI-Folder with SMBIOS iMacPro1,1 System definition.

    1.) Download and unzip EFI-X299-10.13.6-Release-iMacPro1,1-110718.zip attached at the bottom of this originating post/guide and copy the therein contained EFI-Folder to your Desktop.

    2.) Open the config.plist in /EFI/Clover/ with the latest version of Clover Configurator (>/= v.4.60.0), proceed to the "SMBIOS" Section and complete the SMBIOS iMacPro1,1 Serial Number, Board Serial Number and SMUUID entries. These details are mandatory to successfully run iMessage and FaceTime on your iMac Pro System. Note that all other iMacPro1,1 SMBIOS Details are already implemented in the config.plist of EFI-X299-10.13.6-Release-iMacPro1,1-110718.zip.

    Press several times the "Generate New" Button next to serial number text field.

    Open a terminal, enter repeatedly the command "uuidgen", and copy the output value to the SMUUID field in the "SMBIOS" Section of the Clover Configurator.

    Users of mainboards with locked MSR Register (disabled MSR OSX Kernel write access) have to enable the xcpm_pkg_scope_msrs © Pike R. Alpha Kernel patch in their config.plist under "KernelToPatch" in Section "Kernel and Kext Patches" of Clover Configurator.

    Enable "PluginType" in your config.plist under SSDT/Generate Options/ in Section ACPI of Clover Configurator for a fully working XCPM implementation. Note that by this, Pike Alpha's former ssdt.aml XCPM implementation becomes totally obsolete.

    PluginType.png

    Finally save the modified config.plist.

    3.) Copy the appropriate TSCAdjustRest.kext, which has been modified in error prevention C.7), to the /EFI/CLOVER/kexts/Other/ directory of the EFI-Folder.

    You know have a fully equipped EFI-Folder for subsequent implementations as detailed below.


    D.2) iMac Pro macOS High Sierra 10.13.6 (17G65) Installer Package Creation

    If you are not able to successfully download the macOS High Sierra 10.13.6 (17G65) full package installer (5.22 GB) from the Appstore, follow the individual steps detailed below:

    1.) Open a terminal and create a "091-94326" directory on your Desktop. Subsequently change to the newly created directory. All this can be done with the following terminal commands:

    Code (Text):

    mkdir ~/Desktop/091-94326/
    cd ~/Desktop/091-94326/
     
    2.) Download the following files from the Apple server (public links) to your ~/Desktop/091-86775/ directory by a copy & paste of the following terminal commands:

    Code (Text):

    curl https://swdist.apple.com/content/downloads/29/03/091-94326/45lbgwa82gbgt7zbgeqlaurw2t9zxl8ku7/091-94326.English.dist -o 091-94326.English.dist
    curl https://swdist.apple.com/content/downloads/29/03/091-94326/45lbgwa82gbgt7zbgeqlaurw2t9zxl8ku7/RecoveryHDMetaDmg.pkm -o RecoveryHDMetaDmg.pkm
    curl http://swcdn.apple.com/content/downloads/29/03/091-94326/45lbgwa82gbgt7zbgeqlaurw2t9zxl8ku7/RecoveryHDMetaDmg.pkg -o RecoveryHDMetaDmg.pkg
    curl http://swcdn.apple.com/content/downloads/29/03/091-94326/45lbgwa82gbgt7zbgeqlaurw2t9zxl8ku7/OSInstall.mpkg -o OSInstall.mpkg
    curl https://swdist.apple.com/content/downloads/29/03/091-94326/45lbgwa82gbgt7zbgeqlaurw2t9zxl8ku7/InstallAssistantAuto.pkm -o InstallAssistantAuto.pkm
    curl http://swcdn.apple.com/content/downloads/29/03/091-94326/45lbgwa82gbgt7zbgeqlaurw2t9zxl8ku7/InstallAssistantAuto.pkg -o InstallAssistantAuto.pkg
    curl http://swcdn.apple.com/content/downloads/29/03/091-94326/45lbgwa82gbgt7zbgeqlaurw2t9zxl8ku7/BaseSystem.dmg -o BaseSystem.dmg
    curl https://swdist.apple.com/content/downloads/29/03/091-94326/45lbgwa82gbgt7zbgeqlaurw2t9zxl8ku7/InstallESDDmg.pkm -o InstallESDDmg.pkm
    curl http://swcdn.apple.com/content/downloads/29/03/091-94326/45lbgwa82gbgt7zbgeqlaurw2t9zxl8ku7/InstallESDDmg.pkg -o InstallESDDmg.pkg
    curl http://swcdn.apple.com/content/downloads/29/03/091-94326/45lbgwa82gbgt7zbgeqlaurw2t9zxl8ku7/BaseSystem.chunklist -o BaseSystem.chunklist
    curl http://swcdn.apple.com/content/downloads/29/03/091-94326/45lbgwa82gbgt7zbgeqlaurw2t9zxl8ku7/InstallESDDmg.chunklist -o InstallESDDmg.chunklist
    curl http://swcdn.apple.com/content/downloads/29/03/091-94326/45lbgwa82gbgt7zbgeqlaurw2t9zxl8ku7/InstallInfo.plist -o InstallInfo.plist
    curl http://swcdn.apple.com/content/downloads/29/03/091-94326/45lbgwa82gbgt7zbgeqlaurw2t9zxl8ku7/AppleDiagnostics.chunklist -o AppleDiagnostics.chunklist
    curl http://swcdn.apple.com/content/downloads/29/03/091-94326/45lbgwa82gbgt7zbgeqlaurw2t9zxl8ku7/AppleDiagnostics.dmg -o AppleDiagnostics.dmg
    curl https://swdist.apple.com/content/downloads/29/03/091-94326/45lbgwa82gbgt7zbgeqlaurw2t9zxl8ku7/MajorOSInfo.pkm -o MajorOSInfo.pkm
    curl http://swcdn.apple.com/content/downloads/29/03/091-94326/45lbgwa82gbgt7zbgeqlaurw2t9zxl8ku7/MajorOSInfo.pkg -o MajorOSInfo.pkg
    curl http://swcdn.apple.com/content/downloads/29/03/091-94326/45lbgwa82gbgt7zbgeqlaurw2t9zxl8ku7/InstallAssistantAuto.smd -o InstallAssistantAuto.smd
     
    The full list of package files can be found within the following catalog URL, searching for key "45lbgwa82gbgt7zbgeqlaurw2t9zxl8ku7":

    https://swscan.apple.com/content/ca...ion-snowleopard-leopard.merged-1.sucatalog.gz


    3.) Create the installer.pkg on your Desktop with the following terminal command:

    Code (Text):

    cd ..
    productbuild --distribution ./091-94326/091-94326.English.dist --package-path ./091-94326/ installer.pkg
     

    4.) Create the "Install MacOS High Sierra.app" in the /Applications folder of your System Disk with the following terminal command:

    Code (Text):
    sudo /usr/sbin/installer -pkg installer.pkg -target /
    In case that you receive an error message, ignore the latter and proceed with 5.)

    5.) Now add the following files to your "Install High Sierra.app" with the following terminal commands:

    Code (Text):

    sudo cp ./091-94326/InstallESDDmg.pkg /Applications/Install\ macOS\ High\ Sierra.app/Contents/SharedSupport/InstallESD.dmg
    sudo cp ./091-94326/AppleDiagnostics.dmg /Applications/Install\ macOS\ High\ Sierra.app/Contents/SharedSupport/
    sudo cp ./091-94326/AppleDiagnostics.chunklist /Applications/Install\ macOS\ High\ Sierra.app/Contents/SharedSupport/
    sudo cp ./091-94326/BaseSystem.dmg /Applications/Install\ macOS\ High\ Sierra.app/Contents/SharedSupport/
    sudo cp ./091-94326/BaseSystem.chunklist /Applications/Install\ macOS\ High\ Sierra.app/Contents/SharedSupport/
     
    Verify your "Install High Sierra.app" for completeness. You should now have a complete macOS High Sierra 10.13.6 (17G65) Installer package in your /Applications Folder.

    The entire iMac Pro macOS Installer Package Creation Approach detailed above has been verified and approved by Motbod and is fully in line with the actual board rules.

    Many thanks to @macandrea for his substantial and extensive contributions. He even now automatised the entire "Install High Sierra.app" creation procedure detailed above within one single script:

    createInstaller.sh will automatically create on any MacOS System the "Install High Sierra.app" for macOS High Sierra 10.13.6 (17G65) in the /Applications folder.

    Just download und unzip createInstaller.sh.zip and run the following terminal commands:

    Code (Text):

    cd ~/Downloads
    chmod +x createInstaller.sh
    ./createInstaller.sh
     
    Absolutely brilliant, gorgeous and genius job man!


    D.3) iMac Pro macOS High Sierra 10.13.6 (17G65) USB Flash Drive Installer Creation

    Follow the individual steps detailed below to successfully create a bootable iMac Pro macOS High Sierra macOS High Sierra 10.13.6 (17G65) USB Flash Drive Installer.

    1.) Format a USB Flash Drive of your choice (source, named USB) with HFS+ [(Mac OS Extended (Journaled)] and a GUID partition table by means of Apple's Disk Utility on any other Hackintosh or Mac of your choice. This will create an empty HFS+ Partition and a yet empty EFI-partition on your iMac Pro macOS USB Flash Drive Installer.

    2.) With the macOS High Sierra 10.13.6 (17G65) Installer Package in your /Application Folder, connect your USB Flash Drive (named USB) and run the following terminal command:

    Code (Text):
    sudo /Applications/Install\ macOS\ High\ Sierra.app/Contents/Resources/createinstallmedia --volume /Volumes/USB --applicationpath /Applications/Install\ macOS\ High\ Sierra.app --nointeraction
    Alternatively, one can create the iMac Pro macOS USB Flash Drive Installer also by means of the Install Disk Creator.app.

    3.) For successfully booting your iMac Pro macOS USB Flash Drive Installer, the latter must however also contain a valid EFI- Folder with an SMBIOS iMacPro1,1 system definition. Thus, copy the EFI-Folder you prepared in Section D.1) to the yet empty EFI Partition of your iMac Pro macOS USB Flash Drive Installer.

    You now have a fully functional and bootable iMac Pro macOS High Sierra 10.13.6 (17G65) USB Flash Drive Installer.

    Many thanks to @macandrea for his substantial and extensive contributions.


    D.4) iMac Pro macOS High Sierra 10.13.6 (17G65) Clean Install on Skylake-X/X299

    clean-install.png

    Follow the individual steps detailed below to successfully setup macOS High Sierra 10.13.6 (17G65) on a virgin system drive of your choice (NVMe, SSD or HDD).

    1.) In order to perform a clean install of macOS High Sierra 10.13.6 (17G65), prepare a virgin NVMe, SDD or HDD destination drive for the iMac Pro macOS installation by formatting the drive with HFS+ [(Mac OS Extended (Journaled)] and a GUID partition table by means of Apple's Disk Utility on any other Hackintosh or Mac of your choice. This will create an empty HFS+ Partition and a yet empty EFI-partition on the drive.

    2.) Copy the EFI-Folder you prepared in Section D.1) to the yet empty EFI Partition.

    3.) Now connect the Destination Drive to your Hackintosh System and boot the latter with the plugged iMac Pro macOS High Sierra 10.13.6 (17G65) USB Flash Drive Installer, your created in Section D.2)

    4.) While booting your system, press the F8 button to enter the BIOS boot menu. Select to boot from your iMac Pro macOS USB Flash Drive Installer.

    5.) Subsequently, click on the USB Flash Drive Installer Icon in the clover boot menu to boot the respective macOS Installer partition on your iMac Pro macOS USB Flash Drive Installer

    6.) After successful boot, pass the individual steps of the macOS high Sierra 10.13 installation menu and finally select the destination drive of your macOS High Sierra 10.13 Installation, which should be logically the system disk you successfully configured above. In the next step, the Installer will create a macOS High Sierra 10.13 Installer Partition on the system disk and subsequently reboot your system.

    7.) During system reboot, just press again the F8 button to enter the BIOS boot menu. Select again to boot from your USB Flash Drive. In contrary to 6.), click this time on the "Install MacOS.." Icon in the clover boot screen to boot the newly created macOS High Sierra 10.13 Installer Partition on your system disk.

    8.) After successful boot, you will enter now the macOS High Sierra 10.13 Installer Screen with a progress bar starting at 34 minutes.

    9.) After another reboot, press again the F8 button to enter the BIOS boot menu. Select to boot with your System Disk EFI-folder. Click on the "MacOS High Sierra" icon in the clover boot screen to boot the updated macOS High Sierra 10.13 partition on your system disk.

    10.) After successful boot you will enter again the macOS High Sierra 10.13 Installer Screen with a progress bar starting at 18 minutes. After successfully registration at iCloud at the end of the macOS installation, you now have your first iMac Pro macOS High Sierra 10.13.6 (17G65) build.

    Proceed with Section D.6) - iMac Pro macOS High Sierra Build Updates (if necessary) or E.) - Post Installation Process.


    D.5) Direct iMac Pro conversions of a functional Skylake-X/X299 system with a SMBIOS System Definition different from iMacPro1,1 and a standard macOS build implementation

    upgrade-1.png

    1.) Replace the EFI-Folder of your System Disk by the EFI-Folder you created in Section D.1)

    2.) Copy /System/Library/CoreServices/PlatformSupport.plist to your Desktop, add BoardID "Mac-7BA5B2D9E42DDD94"
    under SupportedBoardIDs by means of Xcode as suggested by user Griven from the German Hackintosh-Forum and copy back the modified PlatformSupport.plist to System/Library/CoreServices/.

    3.) If not already in your /Applications folder after performing Section D.2), copy the iMac Pro macOS Installer Package ("Install High Sierra.app") to your /Applications folder. Alternatively to D.2) and the macOS Full Package Installer, it is also sufficient to just download the original unmodified macOS High Sierra 10.13.6 (17G65) BaseSystem.dmg distribution from the Apple Server to your Desktop with the following terminal commands:

    Code (Text):
    cd ~/Desktop/
    curl http://swcdn.apple.com/content/downloads/51/08/091-86775/1fn3s8c48wk0u34dyujciitmn0nx3ul3dc/BaseSystem.dmg -o BaseSystem.dmg
    4.) Double click on the "Install High Sierra.app" in the /Applications Folder to start the macOS High Sierra 10.13.6 (17G65) installation. Alternatively, double click on the BaseSystem.dmg to mount the macOS installer and double click on the therein contained "Install macOS High Sierra.app" to start the macOS High Sierra 10.13.6 (17G65) installation.

    5.) After reboot, click on the "Install MacOS.." Icon in the clover boot screen to boot the newly created macOS High Sierra 10.13 Installer Partition on your system disk.

    6.) After successful boot, you will enter now the macOS High Sierra 10.13 Installer Screen with a progress bar starting at 43
    minutes.

    7.) After another reboot, click on the "MacOS High Sierra" icon in the clover boot screen to boot the updated macOS High Sierra 10.13 partition on your system disk.

    8.) After successful boot you will enter again the macOS High Sierra 10.13 Installer Screen with a progress bar starting at 18 minutes. After successfully registration at iCloud at the end of the macOS installation, you now have your first iMac Pro macOS High Sierra 10.13.6 (17G65) build.

    Proceed with Section D.6) - iMac Pro macOS High Sierra Build Updates (if necessary) or Section E.) - Post Installation Process.


    D.6) iMac Pro macOS High Sierra Update Procedure

    After the successful clean install or conversion you are be able to update your iMac Pro macOS High Sierra 10.13.6 (17G65) build to macOS Mojave Public Betas directly via the Appstore. For further details see my macOS 10.14 X299 Build and Desktop Guide. For macOS beta builds it is recommended to clone your macOS High Sierra System Disk with Carbon Copy Cloner (CCC) to a test drive and to update to the Public Beta on the latter.


    E.) Post Installation Process

    post-installation.png

    E.1) HWP (Intel SpeedShift Technology) CPU Power Management Configuration

    power-management.png

    On Skylake-X/X299 Systems with unlocked mainboard BIOS MSR 0xE2 BIOS register and SMBIOS iMacPro1,1 we gain fully native HWP (IntelSpeedShift) Power Management after disabling the last remaining XCPM KernelToPatch entry "xcpm_core_scope_msrs" in the config.plist under Section "Kernel and Kext Patches" of Clover Configurator, which by default is still implemented but disabled in the config.plist of the distributed EFI-Folder EFI-X299-10.13.6-Release-iMacPro1,1-110718.zip.

    Users with locked mainboard BIOS MSR 0xE2 register, still have to use the "xcpm_core_scope_msrs" XCPM KernelToPatch entry to successfully boot their systems. Otherwise the OSX Kernel will write to that BIOS register and cause KP at boot!

    XCPM-Kernel-Paches.png

    HWP is a way for the processor itself to manage the power consumption, with minor input from OSX on what it thinks it needs. In contrary, XCPM is the OSX power management part. It directly controls older hardware like Broadwell-E/EP or Haswell-E/EP and enables HWP on newer hardware like Skylake-X. It also sets some HWP variables, like the desired frequency at the maximum.

    XCPM is enabled by default.

    For it's complete configuration, XCPM still requires the CPU "plugin-type" injection to properly load the required XCPM frequency vectors from the iMacPro.plist, which can be directly achieved within the config.plist by checking "PluginType" in Section "ACPI" of Clover Configurator.

    PluginType.png

    How to verify a working xcpm configuration?

    a.) Typically the command "sysctl machdep.xcpm.mode" reveals 1, which means that XCPM is active.

    b.) Verify that in the IORegistryExplorer you have now under CP00@0 the following entry:

    Code (Text):
    Property:         Type:         Value:
    plugin-type       Number        0x1
    c.) Also verify with the terminal command:

    Code (Text):
    kextstat|grep -y x86plat
    that the "X86PlatformPlugin.kext" is now loaded. If the command returns something like

    Code (Text):
    112    1 0xffffff7f822bc000 0x17000    0x17000    com.apple.driver.X86PlatformPlugin (1.0.0) FD88AF70-3E2C-3935-99E4-C48669EC274B <111 19 18 13 11 7 6 5 4 3 1>
    146    1 0xffffff7f822d3000 0x7000     0x7000     com.apple.driver.X86PlatformShim (1.0.0) DCEA94A4-3547-3129-A888-E9D5C77B275E <112 111 13 7 4 3>
    d.) Verify with the following terminal command:

    Code (Text):
    kextstat|grep -y appleintelcpu
    that you got rid of the Apple Intel CPU power management. If the result is empty you are fine.

    e.) Verify the following terminal command:

    Code (Text):
    sysctl -n machdep.xcpm.vectors_loaded_count
    If this command returns "1", the XCPM FrequencyVectors are properly loaded and you are all set.


    E.2) Graphics Configuration:

    Graphics.png

    Most ATI GPUs, e.g. RX Vega 64, RX Vega Frontier, RX 580, RX 560 are natively implemented. However, it is commonly recommended not to use RX 560 and RX 580 GPUs due to the lacking iGPU implementation when using SMBIOS iMacPro1,1. Remaining HDMI/DP port errors, hot plug errors and flaws with multi-monitor or 5K display configurations when using ATI Vega GPUs can be fixed by means of VegaGraphicsFixup.kext, kindly provided by @jyavenard. Important comment for all Vega users with 4K monitors though: when connecting e.g. the Vega Frontier with e.g. the LG 38UC99-W (WUHD, 3840 pix x 1600 pix) via one of the Display Ports (DPs), the screen resolution is fine under both Windows 10 and macOS High Sierra but is totally at odd during boot (VGA like boot screen resolution). @DSM2 reported similar issues with his true 4K display and with both the ASUS Prime X299 Deluxe and the Gigabyte Designare EX. Thus the VEGA DP 4K boot screen resolution issue is neither related with the fact that the LG 38UC99-W is a ultra-wide (3840x1600) and not a true UHD (3840x2160) monitor nor related to any likely apparent issue with the ASUS Prime X299 Deluxe firmware. It is definitely a Vega firmware problem in combination with 4K displays, as the DP 4K boot screen resolution issue is totally absent with my Nvidia GPU and the problem also does not only affect the ASUS Splash Screen but also spreads over the entire boot process until the login screen is reached (Windows and macOS). Splash Screen, Apple logo or verbose boot messages are not stretched but rather have VGA like resolution. Any fix of the AMD vBIOS would be highly appreciated. It is more than disappointing to witness such issues with 1000$ GPUs... Fortunately, the 4K boot screen issue is restricted to the Vega DP ports and likely due to the fact that the LG 38UC99-W only supports DP 1.2. Solution: Connect your Vega and your 4K display via the HDMI port. Although, in the latter case the monitor frequency seems to be limited to 30 Hz, compared with the 60 Hz or 75 Hz under macOS Mojave obtained within a DP connection.

    Also Nvidia Kepler Graphics Cards are natively implemented.

    All Users with
    Maxwell and Pascal Nvidia Graphics Cards on SMBIOS iMacPro1,1 can employ officially distributed Nvidia 10.13 Web Drivers for their Nvidia Pascal and Maxwell graphics cards! Upon my request from 7 January 2018, Nvidia officially released first WebDriver-387.10.10.10.25.105 for 10.13.2 (17C2120) and first WebDriver-387.10.10.10.25.106 for 10.13.2 SA (17C2205) - Supplemental Update on 11 January 2018. On 25 January 2018, Nvidia released a Web Driver 387.10.10.10.25.157 for 10.13.3 (17D2047), which worked flawless with Pascal GPUs (lagging issues have been reported for Maxwell GPUs). On 20 February 2018, Nvidia released a Web Diver 387.10.10.10.30.159 for 10.13.3 SA (17D2102). On 31 March 2018 and 18 April 2018, Nvidia also released Web Driver 387.10.10.10.30.103 and 387.10.10.10.30.106 for 10.13.4 (17E199). On 25 April 2018, Web Driver 387.10.10.10.30.107 has been released for 10.13.4 SU (17E202). On 02 June 2018, Web Driver 387.10.10.10.35.106 followed for 10.13.5 (17F77). On 11 July 2018, Nvidia released final 10.13.6 (17G65) WebDriver-387.10.10.10.40.105 .

    Nvidia Black Screen Prevention:

    Apparently with SMBIOS iMacPro1,1, the Nvidia Black Screen Prevention has become obsolete. Thanks to @fabiosun from InsanelyMac for this finding. Thus, NvidiaGraphicsFixup.kext, subverting AppleMobileFileIntegrity banning the driver can be theoretically removed from the /EFI/CLOVER/kexts/Other/ directory of your macOS Flash Drive Installer and 10.13 System Disk. However, the most actual releases of NvidiaGraphicsFixup.kext v.1.2.7 and Lilu.kext v1.2.4 apparently help in fixing the Nvidia HDAU implementation and sporadic black screen issues while wake from sleep. Thus, the latter kext combination might still represent potential workarounds for few likely remaining system issues.

    E.3) Audio Configuration:

    audio.jpg

    Note that opposite to my previous EFI-Folder distributions, EFI-X299-10.13.6-Release-iMacPro1,1-110718.zip does not contain any default audio configuration. You have to implement the audio approach of your choice during the Post Installation process! Please select between one out of three possible audio implementations detailed below. To avoid the loss of analogue onboard audio (S1220A in case of the ASUS Prime X299 Deluxe) on Wake from Sleep, please download, unzip and copy the latest CodecCommander.kext distribution of @RehabMan from bitbucket.org to the /EFI/Clover/kexts/Other directory in the EFI-Folder of your System Disk: https://bitbucket.org/RehabMan/os-x-eapd-codec-commander/downloads/.


    E.3.1.) AppleALC Audio Implementation


    The actual AppleALC audio implementation traces back to the extensive efforts and brilliant work of @vit9696 and @apfelnico . This new AppleALC audio approach bases on AppleALC.kext v1.2.7, which further requires the Lilu.kext v1.2.3 in the /EFI/CLOVER/kexts/Other/ directory of your System Disk.

    Provided that you use the EFI-Folder contained in EFI-X299-10.13.6-Release-iMacPro1,1-110718.zip, you need to open the config.plist in the /EFI/CLOVER/ directory of your System Disk with the Clover Configurator and add the CAVS -> HDEF ACPI replacement patch in Clover Configurator Section "ACPI" under "DSDT Patches".

    Code (Text):

    Comment:          Find*[Hex]     Replace [Hex]
    CAVS -> HDEF      43415653       48444546
     
    When implementing the SSDT in Section 9.2), we will perform the CAVS -> HDEF ACPI replacement directly within the SSDT. We then have to remove again the CAVS -> HDEF ACPI replacement from the config.plist!

    Note that opposite to the alternative VoodooHDA and CLoverALC approach detailed below, the AppleALC audio implementation requires an Audio ID in injection of "7" instead of "1". Implement the latter Audio ID in the config.plist of your System Disk under "Audio" and "Injection" in the Section "Devices" of the Clover Configurator.

    The correct HDAU HDMI/DP digital Audio PCI implementation will be detailed in Section E.9) in line with the HDEF and GPU PCI device implementation.

    To remove the AppleALC Audio Approach Implementation perform the following steps:

    1.) Remove AppleALC.kext v1.2.6 from the /EFI/CLOVER/kexts/Other/ directory of your System Disk.

    2.) Disable in the config. plist the CAVS -> HDEF DSDT Replacement Patch in Clover Configurator Section "ACPI" under "DSDT Patches".

    3.) Adopt the Audio ID Injection in your respective config.plist in Clover Configurator Section "Devices" for the alternative audio approach you intent to use.

    4.) Reboot

    E.3.2) VoodooHDA Audio Implementation

    1.) Provided that you use the EFI-Folder contained in EFI-X299-10.13.6-Release-iMacPro1,1-110718.zipp, you need to open the config.plist in the /EFI/CLOVER/ directory of your System Disk with the Clover Configurator and add the CAVS -> HDEF ACPI Replacement Patch in Clover Configurator Section "ACPI" under "DSDT Patches".

    Code (Text):
    Comment                         Find*[HEX]      Replace*[HEX]
    Rename CAVS to HDEF      43415653        48444546
    When implementing the SSDT in Section 9.2), we will perform the CAVS -> HDEF ACPI replacement directly within the SSDT. We then have to remove again the CAVS -> HDEF ACPI replacement from the config.plist!


    2.) Download VoodooHDA.kext v2.9.0d10 to your Desktop. Mouse Right-Click on VoodooHDA.kext -> select "Show Package Contents" -> click on "Contents" -> Right-Click on "Info.plist" -> "Open With" -> "Other" -> select "TextEdit.app"

    3.) a.) In the TextEdit.app select in the menu "Edit" -> "Find" -> "Find..." -> search for "IOPCIClassMatch" and

    replace

    Code (Text):
    <key>IOPCIClassMatch</key>
    <string>0x04020000&amp;0xfffe0000</string>


    with

    Code (Text):
    <key>IOPCIPrimaryMatch</key>
    <string>0x43831002</string>


    b.) Download, unzip and run the IORegistryExplorer.app attached at the end of this originating post/guide.

    Search for HDEF and write down the "IOName"-entry under e.g. PC00@0/AppleACPIPCI/HDEF@1F,3 which can slightly deviate on mainboards different from the ASUS Prime X299 Deluxe.

    HDEF.png

    The HDEF-IOName on the ASUS Prime X299 Deluxe is "pci8086,a2f0"

    Concert the IOName as shown below in case of the HDEF-IOName of the ASUS Prime X299 Deluxe:

    "0xa2f08086"

    c.) Now replace in the "Info.plist" of "VoodooHDA.kext"

    "0x43831002"

    by

    "0xa2f08086"

    and save the "Info.plist".

    d.) Copy the modified "VoodooHDA.kext" to the /EFI/Clover/kexts/Other/ - directory of your System Disk.

    4.) Download and copy the
    VoodooHDA.prefPane v1.2 attached below to ~/Library/PreferencePanes/

    5.) Note that the VoodooHDA audio approach requires an Audio ID in injection of "1". The corresponding modification of the config.plist has to be implemented by means of the Clover Configurator by modifying the respective entry in Section "Devices".

    6.) Reboot

    To remove the VoodooHDA audio implementation, perform the following steps:

    1.) Disable in the config. plist the CAVS -> HDEF ACPI Replacement Patch in Clover Configurator Section "ACPI" under "DSDT
    Patches".

    2.) Remove VoodooHDA.kext from the /EFI/CLOVER/kexts/Other/ directory of your System Disk.

    3.) Remove VoodooHDA.prefPane from ~/Library/PreferencePanes/

    4.) Adopt the Audio ID Injection in your config.plist in Section "Devices" of the Clover Configurator for the alternative audio approach you intent to use

    5.) Reboot

    E.3.3) cloverALC Audio Implementation

    @toleda 's cloverALC audio approach has been implemented thanks to the respective advices and help of user @Ramalama. Note that in contrary to the AppleALC and VoodooHDA approaches, the cloverALC audio approach detailed below will patch the native vanilla AppleHDA.kext in the /S/L/E directory of your System Disk! This before implementing the cloverALC audio approach, backup your native vanilla AppleHDA.kext from the /S/L/E directory on your System Disk! You will have to reinstall the native vanilla AppleHDA.kext from the /S/L/E directory on your System Disk with the appropriate permissions during a removal of the cloverALC Audio Implementation! Thus you need a backup of the latter native vanilla kext in any case!

    CloverALC audio approach installation:

    1.) Provided that you use the EFI-Folder contained in EFI-X299-10.13.6-Release-iMacPro1,1-110718.zip you need to open the config.plist in the /EFI/CLOVER/ directory of your System Disk with the Clover Configurator and add the CAVS -> HDEF ACPI Replacement Patch in Clover Configurator Section "ACPI" under "DSDT Patches".

    Code (Text):
    Comment                  Find*[Hex]    Replace[Hex]
    Rename CAVS to HDEF      43415653      48444546
    When implementing the SSDT in Section 9.2), we will perform the CAVS -> HDEF ACPI replacement directly within the SSDT. We then have to remove again the CAVS -> HDEF ACPI replacement from the config.plist!


    2.) Change the Audio ID Injection in the config.plist on your System Disk in Section "Devices" under "Audio" and "Inject" to "1".

    3.) Add the following cloverALC related KextToPatch entries to your config.plist on your System Disk in section "Kerneland Kext Patches" of Clover Configurator in the "KextsToPatch" listing:

    Code (Text):
    Name*         Find*[Hex]         Replace* [Hex]    Comment
    AppleHDA      8a19d411           00000000          t1-10.12-AppleHDA/Realtek ALC...
    AppleHDA      8b19d411           2012ec10          t1-10.12-AppleHDA/RealtekALC1220
    AppleHDA      786d6c2e 7a6c      7a6d6c2e 7a6c     t1-AppleHDA/Resources/xml>zml


    4.) Download, unzip and copy the realtekALC.kext v2.8 to the /EFI/CLOVER/kexts/Other/ directory on your System Disk

    5.) Download and execute audio_cloverALC-130.sh, which will patch the native vanilla AppleHDA.kext in the /S/L/Edirectory of your System Disk

    6.) Reboot

    To remove the cloverALC audio implementation, perform the following steps:

    1.) Remove realtekALC.kext from the /EFI/CLOVER/kexts/Other/ directory on your System Disk

    2.) Remove all cloverALC related KextToPatch entries from the config.plist on your System Disk in the "Kernel andKext Patches" section of Clover Configurator.

    3.) Disable in the config. plist the CAVS -> HDEF ACPI Replacement Patch in Clover Configurator Section "ACPI" under"DSDT Patches".

    4.) Delete the patched AppleHDA.kext in the /S/L/E/ Directory on your System Disk

    5.) Reinstall the original vanilla AppleHDA.kext with the appropriate permission in the /S/L/E/ directory on yourSystem Disk using Kext Utility

    6.) Adopt the Audio ID Injection in your config.plist in Section "Devices" of the Clover Configurator for the alternative audioapproach you intent to use

    7.) Reboot


    E.4) USB Configuration:

    USB.png


    Since 10.13 SU and with AppleIntelPCHPMC, Apple now implements IOPCIPrimaryMatchID "a2af8068" and AppleUSBXHCISPT on the ASUS Prime X299 Deluxe. All external and internal XHC USB 3.0 (USB 3.1 Gen 1 Type-A) and USB 2.0 (USB 2.0 Gen 1 Type-A) ports should work at expected data transfer rates on all X299 mainboards. All external and internal USB 3.1 (USB 3.1 Gen 2 Type-A and Type-C) ports are anyway natively implemented on different controllers than XHC.

    All ASUS Prime X299 Deluxe users, not content with the current OSX XHC USB implementation, can download, unzip and use my board-specific XHC USB Kext KGP-iMacPro-XHCI.kext in /EFI/Clover/kexts/Other/. All users of mainboards different from the ASUS Prime X299 Deluxe, can create their own board specific XHC USB kext by following my XHC USB Kext Creation guide line https://www.tonymacx86.com/threads/macos-high-sierra-10-13-xhc-usb-kext-creation-guideline.242999/.

    Note that in addition one needs to implement the XHC USB port limit patch in the config.plist under "KextsToPatch" in Section "Kernel and Kext Patches" of Clover Configurator, as else not all available XHC USB ports will be implemented.

    Code (Text):
    Name*          Find*[Hex]                Replace* [Hex]            Comment
    AppleUSBXHCI   837D880F 0F83A704 0000   837D880F 90909090 9090   10.13.6 USB Port Limit Patch
    Many thanks to @PMheart from InsanelyMac for providing the respective XHC USB port limit patches.


    USB 2.0 and USB 3.0 Benchmark Results

    usb.png


    USB 3.1 Type-A and Type-C Benchmark Results

    For the individual USB 3.1 Type-A and Type-C Connectors Benchmark, I used the external Lacie Rugged Thunderbolt / USB Type-A and Type-C HDD.

    USB3.1 Type-A-Type-C.png


    E.5) ASUS Prime X299 Deluxe Thunderbolt EX3 PCIe Add-On Implementation

    ASUS_ThunderboltEX_3_Card__Schnittstellenkarte@@gzzar9.png

    For the successful implementation of the Thunderbolt EX3 PCIe Add-On Adapter, a fully working Dual Boot System with an UEFI Windows Implementation is unfortunately absolutely mandatory. You will not be able to configure your Thunderbolt EX3 PCIe Add-On Adapter in the mainboard BIOS, until the Adapter has been successfully recognised and initialised by the UEFI Windows System. Fortunately legal and official License Keys for the actual Windows 10 Pro distribution can be purchased with a little bit of temporal effort on Google for an actual price of 20 $ or even below! Thus, the installation of a dual boot system with Windows will require some additional temporal user effort but will not noticeably further affect the users's budget.

    Please note that I especially emphasize the term UEFI, when speaking about the parallel Windows implementation. Don't use or perform a Legacy Implementation of Windows! In order to properly implement your Windows partition later-on in the Clover Bootloader and to comply with the actual Mainbaord-BIOS settings requirements, it is absolutely mandatory to run or perform an UEFI Windows implementation!

    So if not already implemented, how to achieve a fully working UEFI Windows Implementation and Dual boot System with Windows?

    1.) Important Note! For the implementation of the UEFI Windows Distribution disconnect all usually plugged macOSDrives from your rig! The Windows installer will implement a Windows Boot Loader! If you have any macOS Drive connected during installation, the latter Windows Boot Loader might overwrite and destroy your current Clover Boot Loader. This is the last thing you want! Thus for the windows installation just connect the destination drive for the installation and the Windows USB Flash Drive Installer your will create in the subsequent step below!

    2.) This Tutorial explains in all necessary detail how to download an actual Windows 10 Creator distribution, and how tosubsequently create a bootable USB Flash Drive Installer for a subsequent UEFI Windows 10 installation by means RUFUS! Don't put emphasis on alternative optional methods and always take care that you just follow the instructions for a successful subsequent UEFI Windows Installation!

    Rufus.png

    3.) This Tutorial explains in all necessary detail how to properly perform the actual Windows 10 Pro Creator UEFIInstallation, subsequent to the a bootable Windows USB Flash Drive Installer realisation detailed in 2.) above.

    windows-inst-jpg.275752.png

    4.) This Tutorial explains in all necessary detail, how to migrate/clone/backup your Windows 10 UEFI System Disk afterinstallation for future maintenance and safety.

    aomei-partition-assistant-server-edition-6-free-download-jpeg.275754.png

    5.) After successfully performing the UEFI Windows 10 Pro Creator Implementation, you can reconnect your macOS driveto your rig. The newly created UEFI Windows 10 Pro Creator Partition will automatically appear as a further boot option in both BIOS Boot Option Menu (F8) and Clover Boot Menu! No additional or further actions or measurements have to be taken!

    clover_dualboot_w10-png.275753.png

    6.) Once your Windows 10 Pro Creator Partition is fully operational, install all drivers and programs implemented on theASUS Prime X299 Series DVD attached to your mainboard. This will further allow you to properly adjust the desired AURA Mainboard Settings and offer many other mainboard configuration options.

    dvd-1-jpg.275756.png

    7.) Now switch of your rig and start with the installation of the Thunderbolt EX3 PCIe Add-On Adapter

    a.) I recommend to install the adapter in third PCIe Slot from the bottom which is PCIEX_3

    Prime.png

    b.) For full TB hot plug functionality skip or remove the THB_C cable between the TBEX 3 and the respective mainboard connector.

    8.) Reboot into windows and install the ASUS ThunderboltEX 3 DVD accompanying your ASUS Prime X299 Deluxe mainboard.

    dvd-2-jpg.275764.png

    9.) Reboot and enter the Mainboard BIOS (F2)

    a.) Go to /Advanced/ Thunderbolt(TM) Configuration/ and apply the following BIOS Settings detailed below:

    /Advanced/ Thunderbolt(TM) Configuration/

    Code (Text):
    TBT Root por Selector                               PCIE16_3
    Thunderbolt USB Support                             Enabled
    Thunderbolt Boot Support                            Enabled
    Wake From Thunderbolt(TM Devices)                   Off
    Thunderbolt(TM) PCIe Cache-line Size                128
    GPIO3 Force Pwr                                     On
    Wait time in ms after applying Force Pwr            200
    Skip PCI OptionRom                                  Enabled
    Security Level                                      SL0-No Security
    Reserve mem per phy slot                            32
    Reserve P mem per phy slot                          32
    Reserve IO per phy slot                             20
    Delay before SX Exit                                300
    GPIO Filter                                         Enabled
    Enable CLK REQ                                      Disabled
    Enable ASPM                                         Enabled
    Enable LTR                                          Disabled
    Extra Bus Reserved                                  65
    Reserved Memory                                     386
    Memory Alignment                                    26
    Reserved PMemory                                    960
    PMemory Alignment                                   28
    Reserved I/O                                        0
    Alpine Ridge XHCI WA                                Disabled
    b.) Verify in /Boot/ that
    Above 4G Decoding is Off

    /Boot/

    Code (Text):
    Above 4G Decoding              Off


    10.) Shut down your rig, connect the Thunderbolt Device with the Thunderbolt EX3 Adaptor and boot

    11.) You are done! Your Thunderbolt EX3 PCIe Adapter and connected devices should be now fully implemented and functional.

    12.) We will add TB XHC USB and TB Hot Plug functionality by means of the SSDT-X299-TB3-iMacPro.aml described in Section E.9.3) of this guide.


    Thunderbolt Benchmark

    For the sake fo completeness and for testing the overall Thunderbolt Functionality and Performance, I benchmarked the the data rates of an external Thunderbolt Drive connected via Apple's Thunderbolt-3 to Thunderbolt-2 Adapter. As External Thunderbolt Drive, I once more used the Lacie Rugged Thunderbolt / USB Type-A and Type-C HDD.

    Thunderbolt EX3 PCIe _ Lacie.png


    E.6) NVMe compatibility

    evo.png

    In contrary to macOS Sierra 10.12, in macOS High Sierra 10.13 there is native support of non-4Kn NVMe SSDs, like my Samsung EVO 960 M.2 NVME. All patches applied under macOS Sierra 10.12 are therefore obsolete. The native support of non-4Kn NVMe SSDs enables the unique opportunity to directly perform a clean-install of macOS High Sierra 10.13 on M.2 NVMEs like the Samsung EVO 960.


    E.7.) SSD/NVMe TRIM Support:

    Macs only enable TRIM for Apple-provided solid-state drives they come with. If you upgrade a Mac with an aftermarket SSD/NVMe, the Mac won’t use TRIM with it. The same applies for SSDs/NVMes used by a Hackintosh. When an operating system uses TRIM with a solid-state drive, it sends a signal to the SSD/NVMe every time you delete a file. The SSD/NVMe knows that the file is deleted and it can erase the file’s data from its flash storage. With flash memory, it’s faster to write to empty memory — to write to full memory, the memory must first be erased and then written to. This causes your SSD/NVMe to slow down over time unless TRIM is enabled. TRIM ensures the physical NAND memory locations containing deleted files are erased before you need to write to them. The SSD/NVMe can then manage its available storage more intelligently.

    Note that the config.plist in the EFI-folder of EFI-X299-10.13.6-Release-iMacPro1,1-110718.zip attached towards the end of this guide, contains an SSD/NVMe "TRIM Enabler" KextsToPatch entry, which can be found in the " Kernel and Kext Patches" Section of the Clover Configurator.

    SSD-Trim.png

    Code (Text):
    Name*                   Find*[HEX]                  Replace*[HEX]               Comment
    IOAHCIBlockStorage      4150504c 45205353 4400      00000000 00000000 0000      Trim Enabler


    With this KextToPatch entry, SSD/NVMe TRIM should be fully enabled on your 10.13 System, see Apple's System Report below.

    SSD-TRIM-2.png

    NVMe and SSD Benchmark

    For the sake of completeness please find below the Benchmark of connected NVMe and SDD Drives.

    diskspeed.png

    E.8) Gbit and 10-Gbit Ethernet Implementations

    Section E.8.1) and and E.8.2.) below, describe in the necessary detail how to gain full Gbit and 10-Gbit LAN functionality on Skylake-X/X299 systems.

    E.8.1) ASUS Prime X299 Deluxe on-board Gbit Ethernet Functionality


    ehternet-png.276091.png

    Thanks to the SmallTree-Intel-211-AT-PCIe-GBE.kext, also the Intel I211_AT Gigabit on-board LAN controller of the ASUS Prime X299 Deluxe will be correctly implemented and fully functional, in addition to the Intel I219-V Gigabyte on-board LAN controller of the ASUS Prime X299 Deluxe implemented by means of IntelMausiEthernet.kext (already part of my EFI-Folder distributions). Thus, both ethernet ports on the ASUS Prime X299 Deluxe should now be fully operational..

    Just download , unzip and copy the SmallTree-Intel-211-AT-PCIe-GBE.kex attached below to the /EFI/Clover/kexts/Other/, reboot and you should be done.

    E.8.2) 10-GBit Lan Implementations ASUS Prime X299 Deluxe on-board Gbit Ethernet Functionality

    E.8.2.1)
    ASUS XG-C100C Aquantia AQC107 10-Gbit NIC

    Starting with 10.13.2 there is native support for Aquantia based 10GBit network cards, which are implemented by means of a Apple Vanilla kext called "AppleEthernetAquantiaAqtion.kext", which is further part of "IONetworkingFamily.kext/Contents/PlugIns/" placed in /System/Library/Extensions/ (credits to @mikeboss). First success with the ASUS XG-C100C under MacOS 10.13.3 has been reported by @d5aqoep. @Mieze finally came up with a AppleEthernetAquantiaAqtion KextPatch for the use of the ASUS XG-C100C also under 10.13.4 and and later macOS versions.
    For further information and discussion see https://www.tonymacx86.com/threads/high-sierra-native-support-for-10gb-ethernet.239690/ or https://www.insanelymac.com/forum/t...7-10-gbe-native-support-in-high-sierra-10132/.

    How to successfully implement the ASUS XG-C100C AQC107 PCIe x4 10GBit Ethernet Adapter:

    1.) A temporal macOS High Sierra 10.13.3 (17D2047 in case of the iMac Pro) installation is absolutely mandatory at first place. Only within the latter macOS High Sierra build, the ASUS XG-C100C will receive the proper AQC107 Apple firmware to be recognised and fully implemented by OSX. The firmware update will be performed during system boot. Several boot intents might be necessary until the firmware update finally succeeds. Only subsequently, the ASUS XG-C100C will be natively implemented in macOS High Sierra 10.13.3 and fully functional.

    2.) To finally use the ASUS XG-C100C with macOS builds >10.13.4, one has to implement the following AppleEthernetAquantiaAqtion KextPatch provided by @Mieze:

    Code (Text):
    Name*                            Find*[HEX]         Replace*[HEX]      Comment
    AppleEthernetAquantiaAqtion      0F84C003 0000      90909090 9090      Aquantia patch ©Mieze
    3.) The proper XGBE ASUS XG-C100C PCI SSDT implementation is detailed in Section E.9.2)

    4.) Note that after the firmware update under macOS High Sierra 10.13.3, the ASUS XG-C100C will refuse the official Windows Lan drivers provided by ASUS and will only work with Apple's customised Aquantia64v2.0.015.0 boot camp drivers attached below.

    E.8.2.2) Intel X540-T1 10-Gbit NIC

    Thanks to some Ubuntu EEPROM modding, I also achieved the successful implementation of the Intel X540-T1 single port 10GB LAN PCIe Adapter by means of the Small-Tree 10GB macOS 10.13 driver.

    Some additional notes to the EEPROM modding guideline provided by the above link.

    1.) When creating your Ubuntu USB Flash Drive, use RUFUS 3.0 and select the GPT option to obtain a Ubuntu USB boot drive, fully compatible with your UEFI BIOS implementation!

    2.) To install "net-tools", enter the following terminal command
    Code (Text):
    sudo apt install net-tools
    3.) To install "ethtool" enter the following terminal command:
    Code (Text):
    sudo apt-get install ethtool
    4.) Within the latest Ubuntu distributions, ETH0, ETH1, etc. have been replaced by some weird "enp" port-nomenclature, thus the command "ifconfig" would reveal something like the following:

    ifconfig.jpeg

    My Intel X540-T1 was assigned to enp225s0.

    5.) With the command "lspci -nn -vvv | grep Ethernet" you have to use in 6.) the Vendor/Device-ID entry highlighted by the green rectangle.

    Vendor-ID.png

    6.) By running the "sudo ethtool -e enp225s0 | less" command and eyeballing the offsets, be aware that the latter can be distributed over two lines:

    offsets.png


    You have to count from left to right 0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f for each pair of digits for each offset.

    Thus, the commands I had to run to mod the Intel X540-T1 EEPROM were:
    Code (Text):
    sudo ethtool -E enp225s0 magic 0x15288086 offset 0x48e value 0x0a

    sudo ethtool -E enp225s0 magic 0x15288086 offset 0x48f value 0x00
    Note that the "magic" value implemented in this command has been taken from the "lspci -nn -vvv | grep Ethernet" command output, again encircled by a green rectangle:

    Vendor-ID 2.png

    The rest is as described in the EEPROM modding guideline linked above.

    The proper Intel X540-T1 PCI SSDT implementation is detailed in Section E.9.2)

    Actually, I am now currently using this adaptor in my X99 system configuration.

    E.8.2.3) Small-Tree P2EI0G-2T 10-Gbit NIC

    The Small-Tree P2EI0G-2T 2-Port 10GB LAN PCIe Adapter constitutes the actual base line in my X299 10Gbit LAN configuration. It works OoB with the Small-Tree 10GB macOS 10.13 driver.

    The proper Small-Tree P2EI0G-2T PCI SSDT implementation is detailed in Section E.9.2)

    E.8.2.4) NetGear ProSave XS508M 8-port 10-Gbit Switch

    As already mentioned above, the NetGear ProSave XS508M 8-port 10GBit switch constitutes the turntable of my 10-GBit Ethernet Network. It further connects with a QNAP TS-431X2 Quad-core 4-Bay NAS tower with Built-in 10GbE SFP+ Port.

    E.8.2.5) QNAP TS-431X2 Quad-core 4-Bay NAS tower

    The QNAP TS-431X2 Quad-core 4-Bay NAS tower finally harbours 4x 12 TB Seagate IronWolf drives in RAID 0 configuration (as I rather opt for read/write speed than redundancy).

    E.8.2.6) 10-GBit Ethernet Optimisation

    1.) Use SMB 3.0 instead of AFS for your Ethernet communication.
    2.) Enable Jumbo Frames on your NAS and macOS network settings.
    3.) The service order in your macOS network settings should have your 10-Gbit NIC at first position.
    4.) You can turn off the SMB packet signing of the client and server in a secure network.

    Incoming SMB
    Enter the following terminal commands:
    Code (Text):
    sudo -s

    echo "[default]" >> /etc/nsmb.conf
    
echo "signing_required=no" >> /etc/nsmb.conf
    
exit
    Outgoing SMB:

    Enter the following terminal commands:

    Code (Text):
    smbutil statshares -a

    sudo defaults write /Library/Preferences/SystemConfiguration/com.apple.smb.server SigningRequired 0

    E.9) ASUS Prime X299 Deluxe PCI Device Implementation

    In order to properly implement all PCI device drivers on his/her system and build, one needs adequate ACPI DSDT Replacements and a sophisticated SSDT. Both requirements have been originally successfully implemented for the ASUS Prime X299 Deluxe by our gorgeous @apfelnico with partial contributions of @TheOfficialGypsy. Many thanks for the extensive efforts and extremely fruitful and brilliant work! Subsequently, I adopted the ACPI DSDT Replacement Patches and SSDT in concordance with SMBIOS iMacPro1,1. The actual ACPI DSDT Replacements are part of the config.plist contained in EFI-X299-10.13.6-Release-iMacPro1,1-110718.zip. The SSDT-X299-iMacPro.aml and SSDT-X299-TB3-iMacPro.aml further developed with @apfelnico and @nmano are attached at the bottom of this originating post/guide.

    Note that the ACPI DSDT Replacements, SSDT-X299-iMacPro.aml and SSDT-X299-TB3-iMacPro.aml can be build and PCIe slot population dependend and have to be verified and likely adopted or modified for all mainboards different from the ASUS Prime X299 Deluxe and builds or PCIe slot populations different from the one that constitutes the baseline of this guide.

    For the ASUS Prime X299 Deluxe I will use in the following the PCIe Slot nomenclature depicted below:

    ASUSPrimeX299Deluxe-PCI-Slot-Nomenclature.png

    The verification and likely adaptation/modification can be performed by the help of IORegistryExplorer.

    How to adopted or modify the ACPI DSDT Replacement Patches and SSDT-X299-iMacPro.aml is detailed in post #4852 by means of the OSXWIFI PCIe Adaptor implementation in PCIe Slot-3. I hope that by this specific example it rapidly becomes evident that the correct PCI Device implementation cannot be outlined for each individual "build-in" or "slot-specific" PCI device within this guide. The complexity and effort would just exceed by far all available capacities and indeed require the implementation of a separate guide and thread in addition. I therefore hope on your skills and flexibility to extend and apply the approach and methodology detailed above to any other "build-in" or "slot-specific" PCI device yet to be adopted or implemented.

    Important Note: It is strongly recommend to perform a stepwise PCI Device implementation by means of a minimalistic starter SSDT-X299-iMacPro.aml, which just contains the Definition Block and Device Implementation for one single specific device. Once this PCI device has been successfully implemented, other PCI Device definitions can be added to the SSDT-X299-iMacPro.aml. In case that subsequently the implementation of a specific PCI Device would be erroneous and fail, also all other already successfully implemented PCI devices would disappear from Section "PCI" of Apple's System report and the entire "PCI" Device implementation would fail. Thus a stepwise PCI device implementation/adaptation is highly recommended and sometimes deemed necessary!

    Also keep always in mind to modify/adopt the ACPI replacements in your config.plist in parallel when ever necessary!


    Note once more that the ACPI DSDT Replacements, SSDT-X299-iMacPro.aml and SSDT-X299-TB3-iMacPro.aml detailed below require SMBIOS iMacPro1,1.


    E.9.1) ACPI DSDT Replacement Implementation

    Note once more that all required ACPI DSDT Replacements are already implemented in the config.plist in the /EFI/CLOVER/ directory of the EFI-Folder contained in EFI-X299-10.13.6-Release-iMacPro1,1-110718.zip or are directly part of the SSDT-X299-iMacPro.aml and SSDT-X299-TB3-iMacPro.aml. In the config.plist, the ACPI DSDT Replacements are disabled by default, thus we will now open the config.plist in the /EFI/CLOVER/ directory of your 10.13 System Disk EFI-Folder with Clover Configurator and stepwise adopt (if necessary) and enable the different required DSDT replacement patches in Clover Configurator Section "ACPI" under "DSDT patches", by also discussing their respective function and impact.

    a.) The PC00 -> PCI0 ACPI DSDT replacement patch has the main aim to achieve a SMBIOS iMacPro1,1specific PCI implementation. Note that under SMBIOS iMacPro1,1 all other PC0x definitions remain unchanged.

    Please enable now the PC0x -> PCIx ACPI DSDT replacement patch.

    Code (Text):

    Comment:            Find*[Hex]     Replace [Hex]
    PC00 -> PCI0        50433030       50434930
     

    b.) OSI -> XOSI, EC0_ -> EC__ and H_EC -> EC__ are once more ACPI DSDT replacement patches to achieveconsistency with the SMBIOS iMacPro1,1 variable naming.

    i.) XOSI functionality is required as explained by @RehabMan (just follow this LINK forfurther details).

    The ACPI code can use the_OSI method (implemented by the ACPI host) to check which Windows version is running. Most DSDT implementations will vary the USB configuration depending on the active Windows version. When running OS X, none of the DSDT _OSI("Windows <version>") checks will return "true" as there is only response from "Darwin". This issue can be solved by implementing the "OS Check Fix" family of DSDT patches in the SSDT. By DSDT patching we can simulate a certain version of Windows although running Darwin and we can obtain a system behaviour similar to a windows version specific environment.

    ii.) On the Asus X299 Prime Deluxe and most likely on all other X299 mobos we have the EC0 and H_EC controllers,which have to be renamed to 'EC' for proper USB power management. Thus once more investigate your mainboard specific IOREG entry and enable both EC0_ -> EC__ or and H_EC -> EC__ DSDT Replacement Patches.

    Code (Text):

    Comment:             Find*[Hex]      Replace [Hex]
    OSI -> XOSI          5f4f5349        584f5349
    EC0_ -> EC__         4543305f        45435f5f
    H_EC  -> EC__        485f4543        45435f5f
     

    c.) The HEC1 -> IMEI and IDER->MEID ACPI DSDT Replacement patches are Intel Management Engine Interface relatedand are vital as MacOS requires the variable names "IMEI" and "MEID" to load the 'AppleIntelMEIDriver'. The latter functionality solves the 'iTunes/Apple Store Content Access Problem' which is discussed here.

    Please enable now both ACPI DSDT Replacement patches independent from your mainboard.

    Code (Text):

    Comment:             Find*[Hex]       Replace [Hex]
    HEC1 -> IMEI         48454331         494d4549
    IDER->MEID          49444552         4d454944
     

    d.) The LPC0 -> LPCB ACPI DSDT Replacement Patch is AppleLPC and SMBus related and is applied for consistency withthe variable naming on a real Mac. Note that LPCB injects AppleLPC, which however is not required in the X299 environment. X299 Systems seem to have sleep problems with the SMBus properties injected. Thus, the LPCB functionality will be disabled within the SSDT-X299-iMacPro.aml.

    Please enable now this ACPI DSDT replacement patch independent from your mainboard.

    Code (Text):

    Comment:             Find*[Hex]         Replace [Hex]
    LPC0 -> LPCB         4c504330           4c504342
     

    e.) FPU_->MATH, TMR_->TIMR, PIC_->IPIC are all ACPI DSDT Replacement Patches for consistency with the variablenaming on a real Mac. The variables are however functionless on either our X299 boards or real Macs.

    Please enable now all three ACPI DSDT Replacement Patches independent from your mainboard.

    Code (Text):

    Comment:             Find*[Hex]        Replace [Hex]
    FPU_ -> MATH         4650555f          4d415448
    TMR_ -> TIMR         544d525f          54494d52
    PIC_ -> IPIC         5049435f          49504943
     
    f.) The SMBS._ADR -> XSBU.XADR Replacement frees SBUS two show up in IOREG. In principle we have two devices with the same address, one called SMBS and the other one called SBUS. SBUS will never show up in IOREG as long SMBS exists. But SBUS is exactly the variable we need in concordance with the IOREG from the iMacPro Dump.

    Please enable now this ACPI DSDT replacement patch independent from your mainboard.

    Code (Text):

    Comment:                       Find*[Hex]                     Replace [Hex]
    SMBS._ADR -> XSBU.XADR         534d4253 085f4144 52           58534255 08584144 52
     
    g.) The DSM -> XDSM DSDT replacement patch is vital for loading the SSDT-X299-iMacPro.aml, as all DSM methods used in theoriginal DSDT do have a not compatible structure totally different from the real Mac environment. Without any fix, all DSM methods would be simply ignored. Note that one single device can have only one DSM method, which can assign additional properties to the respective device.

    Thus please enable the latter DSDT replacement patch completely independent from your mainboard!

    Code (Text):

    Comment:             Find*[Hex]         Replace [Hex]
    _DSM -> XDSM         5f44534d            5844534d
     
    h.) The 56 CPxx -> PRxx replacements are i9-7980XE specific and result in a proper CPU core reordering as well as in a iMac Pro specific CPU core variable naming.

    All i9-7980XE users can now enable all 56 CPxx -> PRxx replacements. All users of CPUs different from the i9-7980XE have to adopt/modify the 56 CPxx -> PRxx replacements in concordance with their original IOREG CPU core values.

    Code (Text):

    Comment:             Find*[Hex]        Replace [Hex]
    CP00 -> PR00         43503030          50523030
    CP01 -> PR01         43503031          50523031
    CP02 -> PR02         43503032          50523032
    CP03 -> PR03         43503033          50523033
    CP04 -> PR04         43503034          50523034
    CP05 -> PR05         43503035          50523035
    CP06 -> PR06         43503036          50523036
    CP07 -> PR07         43503037          50523037
    CP08 -> PR08         43503038          50523038
    CP09 -> PR09         43503039          50523039
    CP0E -> PR10         43503045          50523130
    CP0F -> PR11         43503046          50523131
    CP10 -> PR12         43503130          50523132
    CP11 -> PR13         43503131          50523133
    CP12 -> PR14         43503132          50523134
    CP13 -> PR15         43503133          50523135
    CP14 -> PR16         43503134          50523136
    CP15 -> PR17         43503135          50523137
    CP1C -> PR18         43503143          50523138
    CP1D -> PR19         43503144          50523139
    CP1E -> PR20         43503145          50523230
    CP1F -> PR21         43503146          50523231
    CP20 -> PR22         43503230          50523232
    CP21 -> PR23         43503231          50523233
    CP22 -> PR24         43503232          50523234
    CP23 -> PR25         43503233          50523235
    CP24 -> PR26         43503234          50523236
    CP25 -> PR27         43503235          50523237
    CP2A -> PR28         43503241          50523238
    CP2B -> PR29         43503242          50523239
    CP2C -> PR30         43503243          50523330
    CP2D -> PR31         43503244          50523331
    CP2E -> PR32         43503245          50523332
    CP2F -> PR33         43503246          50523333
    CP30 -> PR34         43503330          50523334
    CP31 -> PR35         43503331          50523335
    CP0A -> PR36         43503041          50523336
    CP0B -> PR37         43503042          50523337
    CP0C -> PR38         43503043          50523338
    CP0D -> PR39         43503044          50523339
    CP16 -> PR40         43503136          50523430
    CP17 -> PR41         43503137          50523431
    CP18 -> PR42         43503138          50523432
    CP19 -> PR43         43503139          50523433
    CP1A -> PR44         43503141          50523434
    CP1B -> PR45         43503142          50523435
    CP26 -> PR46         43503236          50523436
    CP27 -> PR47         43503237          50523437
    CP28 -> PR48         43503238          50523438
    CP29 -> PR49         43503239          50523439
    CP32 -> PR50         43503332          50523530
    CP33 -> PR51         43503333          50523531
    CP34 -> PR52         43503334          50523532
    CP35 -> PR53         43503335          50523533
    CP36 -> PR54         43503336          50523534
    CP37 -> PR55         43503337          50523535
     
    Resulting CPU Core Implementation:

    CPU-core-implementation.png


    E.9.2) SSDT-X299-iMacPro.aml PCI Implementation

    PCI-Device-Implementation.png

    For the proper PCI device driver implementation (detailed in the Figure above), which is mostly directly related with the PCI device functionality, we now have to revise and likely adopt or modify the attached SSDT-X299-iMacPro.aml with MaciASL.app to our specific build and system configuration with the help of the IORegistryExplorer.

    Note that for each device, the SSDT-X299-iMacPro.aml contains a DefinitionBlock entry and the underlying PCI device implementation. In case of necessary modifications/adaptations, don't forget to also modify/adapt the respective DefinitionBlock entries in concordance with your IOREG entries. The entire SSDT structure is module like. Each module can be independently added, changed or removed in dependence of your specific build, needs and requirements. A stepwise implementation of the individual PCI devices is recommended!

    E.9.2.1) - HDEF - onboard PCI Audio Controller PCI Implementation:

    DefintionBlock entry:

    Code (Text):

    External (_SB_.PCI0.CAVS, DeviceObj)    // (from opcode)
     
    PCI Device Implementation:

    Code (Text):

        Scope (\_SB.PCI0)
        {
            Scope (CAVS)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Device (HDEF)
            {
                Name (_ADR, 0x001F0003)  // _ADR: Address
                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                {
                    Store (Package (0x16)
                        {
                            "AAPL,slot-name",
                            Buffer (0x09)
                            {
                                "Built In"
                            },

                            "model",
                            Buffer (0x1C)
                            {
                                "Realtek ALC S1220A HD Audio"
                            },

                            "name",
                            Buffer (0x27)
                            {
                                "Realtek ALC S1220A HD Audio Controller"
                            },

                            "hda-gfx",
                            Buffer (0x0A)
                            {
                                "onboard-1"
                            },

                            "device_type",
                            Buffer (0x14)
                            {
                                "HD-Audio-Controller"
                            },

                            "device-id",
                            Buffer (0x04)
                            {
                                 0xF0, 0xA2, 0x00, 0x00
                            },

                            "compatible",
                            Buffer (0x0D)
                            {
                                "pci8086,0C0C"
                            },

                            "MaximumBootBeepVolume",
                            Buffer (One)
                            {
                                 0xEE
                            },

                            "MaximumBootBeepVolumeAlt",
                            Buffer (One)
                            {
                                 0xEE
                            },

                            "layout-id",
                            Buffer (0x04)
                            {
                                 0x07, 0x00, 0x00, 0x00
                            },

                            "PinConfigurations",
                            Buffer (Zero) {}
                        }, Local0)
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                    Return (Local0)
                }
            }
        }

     
    The HDEF PCI device implementation is valid for the ASUS Prime X299 Deluxe and likely for all other mainboards with the Realtek ALC S1220A Audio Controller chipset. It is a build-in device and does not have any slot specific dependency. Note the CAVS -> HDEF replacement directly performed within the SSDT!


    E.9.2.2) - GFX0, HDAU - Nvidia Graphics Card and HDMI/DP Audio PCI implementation

    DefintionBlock entry:

    Code (Text):

    External (_SB_.PC02.BR2A, DeviceObj)    // (from opcode)
    External (_SB_.PC02.BR2A.SL05, DeviceObj)    // (from opcode)
    External (_SB_.PC02.BR2A.PEGP, DeviceObj)    // (from opcode)
    External (DTGP, MethodObj)    // 5 Arguments (from opcode)
     
    PCI Device Implementation:

    Code (Text):

        Scope (_SB.PC02.BR2A)
        {
            Scope (SL05)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Scope (PEGP)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Device (GFX0)
            {
                Name (_ADR, Zero)  // _ADR: Address
                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                {
                    Store (Package (0x14)
                        {
                            "built-in",
                            Buffer (One)
                            {
                                 0x00
                            },

                            "device-id",
                            Buffer (0x04)
                            {
                                 0x06, 0x1B, 0x00, 0x00
                            },

                            "hda-gfx",
                            Buffer (0x0A)
                            {
                                "onboard-2"
                            },

                            "AAPL,slot-name",
                            Buffer (0x07)
                            {
                                "Slot-1"
                            },

                            "@0,connector-type",
                            Buffer (0x04)
                            {
                                 0x00, 0x08, 0x00, 0x00
                            },

                            "@1,connector-type",
                            Buffer (0x04)
                            {
                                 0x00, 0x08, 0x00, 0x00
                            },

                            "@2,connector-type",
                            Buffer (0x04)
                            {
                                 0x00, 0x08, 0x00, 0x00
                            },

                            "@3,connector-type",
                            Buffer (0x04)
                            {
                                 0x00, 0x08, 0x00, 0x00
                            },

                            "@4,connector-type",
                            Buffer (0x04)
                            {
                                 0x00, 0x08, 0x00, 0x00
                            },

                            "@5,connector-type",
                            Buffer (0x04)
                            {
                                 0x00, 0x08, 0x00, 0x00
                            }
                        }, Local0)
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                    Return (Local0)
                }
            }

            Device (HDAU)
            {
                Name (_ADR, One)  // _ADR: Address
                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                {
                    Store (Package (0x0C)
                        {
                            "built-in",
                            Buffer (One)
                            {
                                 0x00
                            },

                            "device-id",
                            Buffer (0x04)
                            {
                                 0xEF, 0x10, 0x00, 0x00
                            },

                            "AAPL,slot-name",
                            Buffer (0x07)
                            {
                                "Slot-1"
                            },

                            "device_type",
                            Buffer (0x16)
                            {
                                "Multimedia Controller"
                            },

                            "name",
                            Buffer (0x1D)
                            {
                                "NVIDIA High Definition Audio"
                            },

                            "hda-gfx",
                            Buffer (0x0A)
                            {
                                "onboard-2"
                            }
                        }, Local0)
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                    Return (Local0)
                }
            }
        }
     
    The actual GFX0 and HDAU PCI device implementation is valid for SMBIOS iMacPro1,1 (GFX0), the ASUS Prime X299 Deluxe and any Nvidia Graphics Card implemented in PCIe Slot 1.

    It is a build and PCIe slot population dependent device implementation. Nvidia Graphics Card users with more than one graphics card, or with an Nvidia graphics card in a PCIe slot different from PCIe Slot 1, will have to adopt the respective device path entries PC02.BR2A, PCIe Slot definitions and PCI device properties following their respective IOREG entries. Note the SL05 -> PEGP and PEGP -> GFX0 ACPI replacements directly performed within the SSDT.

    Also note that with 10.13.4, Apple changed the com.apple.driver.AppleHDAController implementation. To make the NVIDIA HDAU PCI device driver work for e.g. a GeForce GTX 1080, one needs to add the following KextToPatch entry in Section "Kernel and kext Patches" of Clover Configurator, as already implemented in the config.plist contained in EFI-X299-10.13.6-Release-iMacPro1,1-110718.zip:

    Code (Text):
    Name*                                 Find* [HEX]         Replace* [HEX]        Comment
    com.apple.driver.AppleHDAController   DE100B0E            DE10EF10              FredWst DP/HDMI patch
    Credits to @FreedWst and thanks to @fabiosun for pointing me to this solution. The KextToPatch entry might defer for Nvidia GPUs different from the Geforce GTX 1080.

    Users of NvidiaGraphicsfixup.kext v1.2.6 and above might be able to drop this KextToPatch entry, as the latter kext already properly implements the Nvidia HDAU PCI driver.


    Below one finds an example of @apfelnico for a GFX and HDAU PCI implementation of 1x Radeon Vega Frontier in PCIe Slot 1:

    DefintionBlock entry:

    Code (Text):

        External (_SB_.PC02.BR2A, DeviceObj)    // (from opcode)
        External (_SB_.PC02.BR2A.PEGP, DeviceObj)    // (from opcode)
        External (_SB_.PC02.BR2A.SL05, DeviceObj)    // (from opcode)
        External (DTGP, MethodObj)    // 5 Arguments (from opcode)
     
    PCI Device Implementation:

    Code (Text):

        Scope (\_SB.PC02.BR2A)
        {
            Scope (SL05)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Scope (PEGP)
            {
                Device (EGP0)
                {
                    Name (_ADR, Zero)  // _ADR: Address
                    Device (GFX0)
                    {
                        Name (_ADR, Zero)  // _ADR: Address
                        Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                        {
                            Store (Package (0x18)
                                {
                                    "built-in",
                                    Buffer (One)
                                    {
                                         0x00                            
                                    },

                                    "AAPL,slot-name",
                                    Buffer (0x07)
                                    {
                                        "Slot-1"
                                    },

                                    "model",
                                    Buffer (0x16)
                                    {
                                        "Vega Frontier Edition"
                                    },

                                    "name",
                                    Buffer (0x08)
                                    {
                                        "ATY_GPU"
                                    },

                                    "@0,connector-type",
                                    Buffer (0x04)
                                    {
                                         0x00, 0x04, 0x00, 0x00          
                                    },

                                    "@1,connector-type",
                                    Buffer (0x04)
                                    {
                                         0x00, 0x04, 0x00, 0x00          
                                    },

                                    "@2,connector-type",
                                    Buffer (0x04)
                                    {
                                         0x00, 0x04, 0x00, 0x00          
                                    },

                                    "@3,connector-type",
                                    Buffer (0x04)
                                    {
                                         0x00, 0x08, 0x00, 0x00          
                                    },

                                    "@0,name",
                                    Buffer (0x0D)
                                    {
                                        "ATY,Kamarang"
                                    },

                                    "@1,name",
                                    Buffer (0x0D)
                                    {
                                        "ATY,Kamarang"
                                    },

                                    "@2,name",
                                    Buffer (0x0D)
                                    {
                                        "ATY,Kamarang"
                                    },

                                    "@3,name",
                                    Buffer (0x0D)
                                    {
                                        "ATY,Kamarang"
                                    }
                                }, Local0)
                            DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                            Return (Local0)
                        }
                    }

                    Device (HDAU)
                    {
                        Name (_ADR, One)  // _ADR: Address
                        Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                        {
                            Store (Package (0x0A)
                                {
                                    "built-in",
                                    Buffer (One)
                                    {
                                         0x00                            
                                    },

                                    "AAPL,slot-name",
                                    Buffer (0x07)
                                    {
                                        "Slot-1"
                                    },

                                    "name",
                                    Buffer (0x1F)
                                    {
                                        "Vega Frontier Edition HD-Audio"
                                    },

                                    "model",
                                    Buffer (0x1F)
                                    {
                                        "Vega Frontier Edition HD-Audio"
                                    },

                                    "hda-gfx",
                                    Buffer (0x0A)
                                    {
                                        "onboard-2"
                                    }
                                }, Local0)
                            DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                            Return (Local0)
                        }
                    }
                }
            }
        }
     
    as well as one example of @apfelnico for the GFX and HDAU PCI implementation of 1x Radeon Vega 64 in PCIe Slot 1, pimped to 1442 Mhz:

    DefintionBlock entry:

    Code (Text):

        External (_SB_.PC02.BR2A, DeviceObj)    // (from opcode)
        External (_SB_.PC02.BR2A.PEGP, DeviceObj)    // (from opcode)
        External (_SB_.PC02.BR2A.SL05, DeviceObj)    // (from opcode)
        External (DTGP, MethodObj)    // 5 Arguments (from opcode)
     
    PCI Device Implementation:

    Code (Text):

      Scope (\_SB.PC02.BR2A)
        {
            Scope (SL05)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Scope (PEGP)
            {
                Device (EGP0)
                {
                    Name (_ADR, Zero)  // _ADR: Address
                    Device (GFX0)
                    {
                        Name (_ADR, Zero)  // _ADR: Address
                        Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                        {
                            Store (Package (0x20)
                                {
                                    "built-in",
                                    Buffer (One)
                                    {
                                         0x00                              
                                    },

                                    "AAPL,slot-name",
                                    Buffer (0x07)
                                    {
                                        "Slot-1"
                                    },

                                    "model",
                                    Buffer (0x12)
                                    {
                                        "Radeon RX Vega 64"
                                    },

                                    "name",
                                    Buffer (0x08)
                                    {
                                        "ATY_GPU"
                                    },

                                    "@0,connector-type",
                                    Buffer (0x04)
                                    {
                                         0x00, 0x04, 0x00, 0x00            
                                    },

                                    "@1,connector-type",
                                    Buffer (0x04)
                                    {
                                         0x00, 0x04, 0x00, 0x00            
                                    },

                                    "@2,connector-type",
                                    Buffer (0x04)
                                    {
                                         0x00, 0x04, 0x00, 0x00            
                                    },

                                    "@3,connector-type",
                                    Buffer (0x04)
                                    {
                                         0x00, 0x08, 0x00, 0x00            
                                    },

                                    "@0,name",
                                    Buffer (0x0D)
                                    {
                                        "ATY,Kamarang"
                                    },

                                    "@1,name",
                                    Buffer (0x0D)
                                    {
                                        "ATY,Kamarang"
                                    },

                                    "@2,name",
                                    Buffer (0x0D)
                                    {
                                        "ATY,Kamarang"
                                    },

                                    "@3,name",
                                    Buffer (0x0D)
                                    {
                                        "ATY,Kamarang"
                                    },

                                    "PP_PhmSoftPowerPlayTable",
                                    Buffer (One)
                                    {
                                        /* 0000 */  0xB6, 0x02, 0x08, 0x01, 0x00, 0x5C, 0x00, 0xE1,
                                        /* 0008 */  0x06, 0x00, 0x00, 0xEE, 0x2B, 0x00, 0x00, 0x1B,
                                        /* 0010 */  0x00, 0x48, 0x00, 0x00, 0x00, 0x80, 0xA9, 0x03,
                                        /* 0018 */  0x00, 0xF0, 0x49, 0x02, 0x00, 0x8E, 0x00, 0x08,
                                        /* 0020 */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                        /* 0028 */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x01,
                                        /* 0030 */  0x5C, 0x00, 0x4F, 0x02, 0x46, 0x02, 0x94, 0x00,
                                        /* 0038 */  0x9E, 0x01, 0xBE, 0x00, 0x28, 0x01, 0x7A, 0x00,
                                        /* 0040 */  0x8C, 0x00, 0xBC, 0x01, 0x00, 0x00, 0x00, 0x00,
                                        /* 0048 */  0x72, 0x02, 0x00, 0x00, 0x90, 0x00, 0xA8, 0x02,
                                        /* 0050 */  0x6D, 0x01, 0x43, 0x01, 0x97, 0x01, 0xF0, 0x49,
                                        /* 0058 */  0x02, 0x00, 0x71, 0x02, 0x02, 0x02, 0x00, 0x00,
                                        /* 0060 */  0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
                                        /* 0068 */  0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x07, 0x00,
                                        /* 0070 */  0x03, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
                                        /* 0078 */  0x00, 0x00, 0x01, 0x08, 0x84, 0x03, 0x84, 0x03,
                                        /* 0080 */  0xB6, 0x03, 0xE8, 0x03, 0x1A, 0x04, 0x4C, 0x04,
                                        /* 0088 */  0x60, 0x04, 0x7E, 0x04, 0x01, 0x01, 0x33, 0x04,
                                        /* 0090 */  0x01, 0x01, 0x84, 0x03, 0x00, 0x08, 0x60, 0xEA,
                                        /* 0098 */  0x00, 0x00, 0x00, 0x40, 0x19, 0x01, 0x00, 0x01,
                                        /* 00A0 */  0x80, 0x38, 0x01, 0x00, 0x02, 0xDC, 0x4A, 0x01,
                                        /* 00A8 */  0x00, 0x03, 0x90, 0x5F, 0x01, 0x00, 0x04, 0x00,
                                        /* 00B0 */  0x77, 0x01, 0x00, 0x05, 0x90, 0x91, 0x01, 0x00,
                                        /* 00B8 */  0x06, 0x50, 0xBD, 0x01, 0x00, 0x07, 0x01, 0x08,
                                        /* 00C0 */  0xD0, 0x4C, 0x01, 0x00, 0x00, 0x00, 0x80, 0x00,
                                        /* 00C8 */  0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x8D, 0x01,
                                        /* 00D0 */  0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                        /* 00D8 */  0x00, 0x00, 0xDC, 0xC7, 0x01, 0x00, 0x02, 0x00,
                                        /* 00E0 */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98,
                                        /* 00E8 */  0xFC, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00,
                                        /* 00F0 */  0x00, 0x00, 0x00, 0x00, 0xD8, 0x1B, 0x02, 0x00,
                                        /* 00F8 */  0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                        /* 0100 */  0x00, 0xF4, 0x40, 0x02, 0x00, 0x05, 0x00, 0x00,
                                        /* 0108 */  0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1C, 0x64,
                                        /* 0110 */  0x02, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x01,
                                        /* 0118 */  0x00, 0x00, 0x00, 0x68, 0x81, 0x02, 0x00, 0x07,
                                        /* 0120 */  0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
                                        /* 0128 */  0x00, 0x05, 0x60, 0xEA, 0x00, 0x00, 0x00, 0x40,
                                        /* 0130 */  0x19, 0x01, 0x00, 0x00, 0x80, 0x38, 0x01, 0x00,
                                        /* 0138 */  0x00, 0xDC, 0x4A, 0x01, 0x00, 0x00, 0x90, 0x5F,
                                        /* 0140 */  0x01, 0x00, 0x00, 0x00, 0x08, 0x28, 0x6E, 0x00,
                                        /* 0148 */  0x00, 0x00, 0x2C, 0xC9, 0x00, 0x00, 0x01, 0xF8,
                                        /* 0150 */  0x0B, 0x01, 0x00, 0x02, 0x80, 0x38, 0x01, 0x00,
                                        /* 0158 */  0x03, 0x90, 0x5F, 0x01, 0x00, 0x04, 0xF4, 0x91,
                                        /* 0160 */  0x01, 0x00, 0x05, 0xD0, 0xB0, 0x01, 0x00, 0x06,
                                        /* 0168 */  0x38, 0xC1, 0x01, 0x00, 0x07, 0x00, 0x08, 0x6C,
                                        /* 0170 */  0x39, 0x00, 0x00, 0x00, 0x24, 0x5E, 0x00, 0x00,
                                        /* 0178 */  0x01, 0xFC, 0x85, 0x00, 0x00, 0x02, 0xAC, 0xBC,
                                        /* 0180 */  0x00, 0x00, 0x03, 0x34, 0xD0, 0x00, 0x00, 0x04,
                                        /* 0188 */  0x68, 0x6E, 0x01, 0x00, 0x05, 0x08, 0x97, 0x01,
                                        /* 0190 */  0x00, 0x06, 0xB0, 0xAD, 0x01, 0x00, 0x07, 0x00,
                                        /* 0198 */  0x01, 0x68, 0x3C, 0x01, 0x00, 0x00, 0x01, 0x04,
                                        /* 01A0 */  0x3C, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50,
                                        /* 01A8 */  0xC3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x38,
                                        /* 01B0 */  0x01, 0x00, 0x02, 0x00, 0x00, 0x34, 0x98, 0x01,
                                        /* 01B8 */  0x00, 0x04, 0x00, 0x00, 0x01, 0x08, 0x00, 0x98,
                                        /* 01C0 */  0x85, 0x00, 0x00, 0x40, 0xB5, 0x00, 0x00, 0x60,
                                        /* 01C8 */  0xEA, 0x00, 0x00, 0x50, 0xC3, 0x00, 0x00, 0x01,
                                        /* 01D0 */  0x80, 0xBB, 0x00, 0x00, 0x60, 0xEA, 0x00, 0x00,
                                        /* 01D8 */  0x94, 0x0B, 0x01, 0x00, 0x50, 0xC3, 0x00, 0x00,
                                        /* 01E0 */  0x02, 0x00, 0xE1, 0x00, 0x00, 0x94, 0x0B, 0x01,
                                        /* 01E8 */  0x00, 0x40, 0x19, 0x01, 0x00, 0x50, 0xC3, 0x00,
                                        /* 01F0 */  0x00, 0x03, 0x78, 0xFF, 0x00, 0x00, 0x40, 0x19,
                                        /* 01F8 */  0x01, 0x00, 0x88, 0x26, 0x01, 0x00, 0x50, 0xC3,
                                        /* 0200 */  0x00, 0x00, 0x04, 0x40, 0x19, 0x01, 0x00, 0x80,
                                        /* 0208 */  0x38, 0x01, 0x00, 0x80, 0x38, 0x01, 0x00, 0x50,
                                        /* 0210 */  0xC3, 0x00, 0x00, 0x05, 0x80, 0x38, 0x01, 0x00,
                                        /* 0218 */  0xDC, 0x4A, 0x01, 0x00, 0xDC, 0x4A, 0x01, 0x00,
                                        /* 0220 */  0x50, 0xC3, 0x00, 0x00, 0x06, 0x00, 0x77, 0x01,
                                        /* 0228 */  0x00, 0x00, 0x77, 0x01, 0x00, 0x90, 0x5F, 0x01,
                                        /* 0230 */  0x00, 0x50, 0xC3, 0x00, 0x00, 0x07, 0x90, 0x91,
                                        /* 0238 */  0x01, 0x00, 0x90, 0x91, 0x01, 0x00, 0x00, 0x77,
                                        /* 0240 */  0x01, 0x00, 0x50, 0xC3, 0x00, 0x00, 0x01, 0x18,
                                        /* 0248 */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B,
                                        /* 0250 */  0x00, 0x00, 0xBC, 0x02, 0x48, 0x26, 0x46, 0x00,
                                        /* 0258 */  0x0A, 0x00, 0x54, 0x03, 0x90, 0x01, 0x90, 0x01,
                                        /* 0260 */  0x90, 0x01, 0x90, 0x01, 0x90, 0x01, 0x90, 0x01,
                                        /* 0268 */  0x90, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
                                        /* 0270 */  0x04, 0x31, 0x07, 0x90, 0x01, 0x90, 0x01, 0x90,
                                        /* 0278 */  0x01, 0x90, 0x01, 0x00, 0x00, 0x59, 0x00, 0x69,
                                        /* 0280 */  0x00, 0x4A, 0x00, 0x4A, 0x00, 0x5F, 0x00, 0x73,
                                        /* 0288 */  0x00, 0x73, 0x00, 0x64, 0x00, 0x40, 0x00, 0x90,
                                        /* 0290 */  0x92, 0x97, 0x60, 0x96, 0x00, 0x90, 0x55, 0x00,
                                        /* 0298 */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                        /* 02A0 */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                        /* 02A8 */  0x02, 0x02, 0xD4, 0x30, 0x00, 0x00, 0x02, 0x10,
                                        /* 02B0 */  0x60, 0xEA, 0x00, 0x00, 0x02, 0x10
                                    },

                                    "hda-gfx",
                                    Buffer (0x0A)
                                    {
                                        "onboard-2"
                                    },

                                    "PP_DisablePowerContainment",
                                    Buffer (One)
                                    {
                                         0x01                              
                                    },

                                    "PP_FuzzyFanControl",
                                    Buffer (One)
                                    {
                                         0x00                              
                                    }
                                }, Local0)
                            DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                            Return (Local0)
                        }
                    }

                    Device (HDAU)
                    {
                        Name (_ADR, One)  // _ADR: Address
                        Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                        {
                            Store (Package (0x0A)
                                {
                                    "built-in",
                                    Buffer (One)
                                    {
                                         0x00                              
                                    },

                                    "AAPL,slot-name",
                                    Buffer (0x07)
                                    {
                                        "Slot-1"
                                    },

                                    "name",
                                    Buffer (0x14)
                                    {
                                        "Radeon RX  HD-Audio"
                                    },

                                    "model",
                                    Buffer (0x14)
                                    {
                                        "Radeon RX  HD-Audio"
                                    },

                                    "hda-gfx",
                                    Buffer (0x0A)
                                    {
                                        "onboard-2"
                                    }
                                }, Local0)
                            DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                            Return (Local0)
                        }
                    }
                }
            }
     
    E.9.2.3) - PMCR - onboard Power Management Controller (PMC) PCI Implementation:

    DefintionBlock entry:

    Code (Text):

    External (_SB_.PCI0.PMC1, DeviceObj)    // (from opcode)
    External (_SB_.PCI0.PMCR, DeviceObj)    // (from opcode)
    External (DTGP, MethodObj)    // 5 Arguments (from opcode)
     
    PCI Device Implementation:

    Code (Text):

        Scope (\_SB.PCI0)
        {
            Scope (PMC1)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Device (PMCR)
            {
                Name (_ADR, 0x001F0002)  // _ADR: Address
                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                {
                    Store (Package (0x0E)
                        {
                            "AAPL,slot-name",
                            Buffer (0x09)
                            {
                                "Built In"
                            },

                            "model",
                            Buffer (0x1E)
                            {
                                "Intel X299 Series Chipset PMC"
                            },

                            "name",
                            Buffer (0x0A)
                            {
                                "Intel PMC"
                            },

                            "device-id",
                            Buffer (0x04)
                            {
                                 0xA1, 0xA2, 0x00, 0x00
                            },

                            "device_type",
                            Buffer (0x0F)
                            {
                                "PMC-Controller"
                            },

                            "built-in",
                            Buffer (One)
                            {
                                 0x00
                            },

                            "compatible",
                            Buffer (0x0D)
                            {
                                "pci8086,a2a1"
                            }
                        }, Local0)
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                    Return (Local0)
                }
            }
        }
     
    The PMCR PCI device implementation should be valid for all X299 mainboards and should not require any build specific adaptation/modification. Note the PMC1 -> PMCR ACPI replacement directly performed within the SDDT.

    E.9.2.4) - USBX:

    PCI Device Implementation:


    Code (Text):

       Device (_SB.USBX)
        {
            Name (_ADR, Zero)  // _ADR: Address
            Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
            {
                If (LNot (Arg2))
                {
                    Return (Buffer (One)
                    {
                         0x03
                    })
                }

                Return (Package (0x08)
                {
                    "kUSBSleepPortCurrentLimit",
                    0x0834,
                    "kUSBSleepPowerSupply",
                    0x13EC,
                    "kUSBWakePortCurrentLimit",
                    0x0834,
                    "kUSBWakePowerSupply",
                    0x13EC
                })
            }
        }
    When using the XHCI device name for USB (see the XHCI PCI Device Implementation below), one observes a bunch of USB Power Errors when booting the system. The USBX PCI device implementation fixes this errors.


    E.9.2.5) - XHCI - onboard Extended Host Controller Interface (XHCI) PCI Implementation:

    DefintionBlock entry:

    Code (Text):

    External (_SB_.PCI0.XHCI, DeviceObj)    // (from opcode)
    External (DTGP, MethodObj)    // 5 Arguments (from opcode)
     
    PCI Device Implementation:

    Code (Text):

    Scope (\_SB.PCI0.XHCI)
        {
            Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
            {
                Store (Package (0x1B)
                    {
                        "AAPL,slot-name",
                        Buffer (0x09)
                        {
                            "Built In"
                        },

                        "built-in",
                        Buffer (One)
                        {
                             0x00
                        },

                        "device-id",
                        Buffer (0x04)
                        {
                             0xAF, 0xA2, 0x00, 0x00
                        },

                        "name",
                        Buffer (0x34)
                        {
                            "ASMedia / Intel X299 Series Chipset XHCI Controller"
                        },

                        "model",
                        Buffer (0x34)
                        {
                            "ASMedia ASM1074 / Intel X299 Series Chipset USB 3.0"
                        },

                        "AAPL,current-available",
                        0x0834,
                        "AAPL,current-extra",
                        0x0A8C,
                        "AAPL,current-in-sleep",
                        0x0A8C,
                        "AAPL,max-port-current-in-sleep",
                        0x0834,
                        "AAPL,device-internal",
                        Zero,
                        "AAPL,clock-id",
                        Buffer (One)
                        {
                             0x01
                        },

                        "AAPL,root-hub-depth",
                        0x1A,
                        "AAPL,XHC-clock-id",
                        One,
                        Buffer (One)
                        {
                             0x00
                        }
                    }, Local0)
                DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                Return (Local0)
            }
        }
     
    The XHCI USB3.0 ASMedia ASM1074 / Intel X299 Series Chipset PCI device implementation is valid for the ASUS Prime X299 Deluxe and for all other X299 mainboards with the same XHC controller chipset. Verify and adopt/modify if necessary device path "PCI0.XHCI" and PCI device implementations by means of IOREG.

    E.9.2.6) - XHC2,3,4 - ASMedia ASM3142 USB 3.1 Controller PCI Implementation:

    DefintionBlock entry:

    Code (Text):

    External (_SB_.PCI0.RP01, DeviceObj)    // (from opcode)
    External (_SB_.PCI0.RP01.PXSX, DeviceObj)    // (from opcode)
    External (_SB_.PCI0.RP05, DeviceObj)    // (from opcode)
    External (_SB_.PCI0.RP05.PXSX, DeviceObj)    // (from opcode)
    External (_SB_.PCI0.RP07, DeviceObj)    // (from opcode)
    External (_SB_.PCI0.RP07.PXSX, DeviceObj)    // (from opcode)
    External (DTGP, MethodObj)    // 5 Arguments (from opcode)
     
    PCI Device Implementation:

    Code (Text):

        Scope (\_SB.PCI0.RP01)
        {
            Scope (PXSX)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Device (XHC2)
            {
                Name (_ADR, Zero)  // _ADR: Address
                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                {
                    If (LEqual (Arg2, Zero))
                    {
                        Return (Buffer (One)
                        {
                             0x03
                        })
                    }

                    Store (Package (0x1B)
                        {
                            "AAPL,slot-name",
                            Buffer (0x09)
                            {
                                "Built In"
                            },

                            "built-in",
                            Buffer (One)
                            {
                                 0x00
                            },

                            "device-id",
                            Buffer (0x04)
                            {
                                 0x42, 0x21, 0x00, 0x00
                            },

                            "name",
                            Buffer (0x17)
                            {
                                "ASMedia XHC Controller"
                            },

                            "model",
                            Buffer (0x2F)
                            {
                                "ASMedia ASM3142 #1 1x USB 3.1 Type-C Internal "
                            },

                            "AAPL,current-available",
                            0x0834,
                            "AAPL,current-extra",
                            0x0A8C,
                            "AAPL,current-in-sleep",
                            0x0A8C,
                            "AAPL,max-port-current-in-sleep",
                            0x0834,
                            "AAPL,device-internal",
                            Zero,
                            "AAPL,clock-id",
                            Buffer (One)
                            {
                                 0x01
                            },

                            "AAPL,root-hub-depth",
                            0x1A,
                            "AAPL,XHC-clock-id",
                            One,
                            Buffer (One)
                            {
                                 0x00
                            }
                        }, Local0)
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                    Return (Local0)
                }
            }
        }

        Scope (\_SB.PCI0.RP05)
        {
            Scope (PXSX)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Device (XHC3)
            {
                Name (_ADR, Zero)  // _ADR: Address
                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                {
                    If (LEqual (Arg2, Zero))
                    {
                        Return (Buffer (One)
                        {
                             0x03
                        })
                    }

                    Store (Package (0x1B)
                        {
                            "AAPL,slot-name",
                            Buffer (0x09)
                            {
                                "Built In"
                            },

                            "built-in",
                            Buffer (One)
                            {
                                 0x00
                            },

                            "device-id",
                            Buffer (0x04)
                            {
                                 0x42, 0x21, 0x00, 0x00
                            },

                            "name",
                            Buffer (0x17)
                            {
                                "ASMedia XHC Controller"
                            },

                            "model",
                            Buffer (0x2E)
                            {
                                "ASMedia ASM3142 #2 2x USB 3.1 Type-A External"
                            },

                            "AAPL,current-available",
                            0x0834,
                            "AAPL,current-extra",
                            0x0A8C,
                            "AAPL,current-in-sleep",
                            0x0A8C,
                            "AAPL,max-port-current-in-sleep",
                            0x0834,
                            "AAPL,device-internal",
                            Zero,
                            "AAPL,clock-id",
                            Buffer (One)
                            {
                                 0x01
                            },

                            "AAPL,root-hub-depth",
                            0x1A,
                            "AAPL,XHC-clock-id",
                            One,
                            Buffer (One)
                            {
                                 0x00
                            }
                        }, Local0)
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                    Return (Local0)
                }
            }
        }

        Scope (\_SB.PCI0.RP07)
        {
            Scope (PXSX)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Device (XHC4)
            {
                Name (_ADR, Zero)  // _ADR: Address
                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                {
                    If (LEqual (Arg2, 0x00020000))
                    {
                        Return (Buffer (One)
                        {
                             0x03
                        })
                    }

                    Store (Package (0x1B)
                        {
                            "AAPL,slot-name",
                            Buffer (0x09)
                            {
                                "Built In"
                            },

                            "built-in",
                            Buffer (One)
                            {
                                 0x00
                            },

                            "device-id",
                            Buffer (0x04)
                            {
                                 0x42, 0x21, 0x00, 0x00
                            },

                            "name",
                            Buffer (0x17)
                            {
                                "ASMedia XHC Controller"
                            },

                            "model",
                            Buffer (0x4A)
                            {
                                "ASMedia ASM3142 #3 1x USB 3.1 Type-A / ASM1543 1x USB 3.1 Type-C External"
                            },

                            "AAPL,current-available",
                            0x0834,
                            "AAPL,current-extra",
                            0x0A8C,
                            "AAPL,current-in-sleep",
                            0x0A8C,
                            "AAPL,max-port-current-in-sleep",
                            0x0834,
                            "AAPL,device-internal",
                            Zero,
                            "AAPL,clock-id",
                            Buffer (One)
                            {
                                 0x01
                            },

                            "AAPL,root-hub-depth",
                            0x1A,
                            "AAPL,XHC-clock-id",
                            One,
                            Buffer (One)
                            {
                                 0x00
                            }
                        }, Local0)
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                    Return (Local0)
                }
            }
        }

     
    The XHC2,XHC3,XHC4 ASMedia ASM3142/ASM1543 USB 3.1 onboard Intel XHCI controller PCI device implementation is valid for the ASUS Prime X299 Deluxe and for all other X299 mainboards with the same XHC USB3.1 controller ASMedia ASM3142 chipset configuration. Note that this SSDT-X299-iMacPro.aml device implementation also performs the following ACPI Replacements

    PCI0.RP01.PXSX -> PCI0.RP01.XHC2
    PCI0.RP05.PXSX -> PCI0.RP01.XHC3
    PCI0.RP07.PXSX -> PCI0.RP01.XHC4

    in concordance with the respective SMBIOS iMacPro1,1 variable naming. Verify and adopt/modify if necessary the corresponding "PCI0.RP01.XHC2", "PCI0.RP05.XHC3", "PCI0.RP07.XHC4" PCI device implementations by means of IOREG.

    E.9.2.7) ANS1, ANS2 - Apple NVMe Controller PCI Implementation:

    DefintionBlock entry:

    Code (Text):

        External (_SB_.PCI0.RP09, DeviceObj)    // (from opcode)
        External (_SB_.PCI0.RP09.PXSX, DeviceObj)    // (from opcode)
        External (_SB_.PCI0.RP21, DeviceObj)    // (from opcode)
        External (_SB_.PCI0.RP21.PXSX, DeviceObj)    // (from opcode)
        External (DTGP, MethodObj)    // 5 Arguments (from opcode)
     

    PCI Device Implementation:


    Code (Text):

        Scope (\_SB.PCI0.RP09)
        {
            Scope (PXSX)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Device (ANS1)
            {
                Name (_ADR, Zero)  // _ADR: Address
                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                {
                    If (LEqual (Arg2, Zero))
                    {
                        Return (Buffer (One)
                        {
                             0x03
                        })
                    }

                    Store (Package (0x08)
                        {
                            "AAPL,slot-name",
                            Buffer (0x09)
                            {
                                "Built In"
                            },

                            "built-in",
                            Buffer (One)
                            {
                                 0x00
                            },

                            "name",
                            Buffer (0x17)
                            {
                                "Apple SSD Controller I"
                            },

                            "model",
                            Buffer (0x14)
                            {
                                "Apple SSD AP1024M I"
                            }
                        }, Local0)
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                    Return (Local0)
                }
            }
        }

        Scope (\_SB.PCI0.RP21)
        {
            Scope (PXSX)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Device (ANS2)
            {
                Name (_ADR, Zero)  // _ADR: Address
                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                {
                    If (LEqual (Arg2, Zero))
                    {
                        Return (Buffer (One)
                        {
                             0x03
                        })
                    }

                    Store (Package (0x08)
                        {
                            "AAPL,slot-name",
                            Buffer (0x09)
                            {
                                "Built In"
                            },

                            "built-in",
                            Buffer (One)
                            {
                                 0x00
                            },

                            "name",
                            Buffer (0x18)
                            {
                                "Apple SSD Controller II"
                            },

                            "model",
                            Buffer (0x15)
                            {
                                "Apple SSD AP1024M II"
                            }
                        }, Local0)
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                    Return (Local0)
                }
            }
        }

     
    The current ANS2 Apple NVMe Controller PCI implementation is of purely cosmetic nature and is valid for the ASUS Prime X299 Deluxe. Note that this SSDT-X299-iMacPro.aml device implementation also performs the following ACPI Replacements

    PCI0.RP09.PXSX -> PCI0.RP09.ANS1
    PCI0.RP21.PXSX -> PCI0.RP21.ANS2

    in concordance with the respective SMBIOS iMacPro1,1 variable naming.

    Verify and adopt/modify if necessary the "PCI0.RP09.ANS2" PCI device implementations by means of IOREG.


    E.9.2.8) - SAT1 - Intel AHCI SATA Controller PCI Implementation:

    DefintionBlock entry:

    Code (Text):

    External (_SB_.PCI0, DeviceObj)    // (from opcode)
    External (_SB_.PCI0.SAT1, DeviceObj)    // (from opcode)
    External (DTGP, MethodObj)    // 5 Arguments (from opcode)
     
    PCI Device Implementation:

    Code (Text):

        Scope (\_SB.PCI0)
        {
            Scope (SAT1)
            {
                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                {
                    Store (Package (0x0C)
                        {
                            "AAPL,slot-name",
                            Buffer (0x09)
                            {
                                "Built In"
                            },

                            "built-in",
                            Buffer (One)
                            {
                                 0x00
                            },

                            "name",
                            Buffer (0x16)
                            {
                                "Intel AHCI Controller"
                            },

                            "model",
                            Buffer (0x1F)
                            {
                                "Intel X299 Series Chipset SATA"
                            },

                            "device_type",
                            Buffer (0x15)
                            {
                                "AHCI SATA Controller"
                            },

                            "device-id",
                            Buffer (0x04)
                            {
                                 0x82, 0xA2, 0x00, 0x00
                            }
                        }, Local0)
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                    Return (Local0)
                }
            }
        }
     
    The SAT1 onboard Intel AHCI SATA controller PCI device implementation is valid for the ASUS Prime X299 Deluxe and for all other X299 mainboards with the same AHCI SATA controller chipset. Verify and adopt/modify if necessary device path "PCI0.SAT1" and PCI device implementations by means of IOREG.

    E.9.2.9) XGBE - 10GBit NIC Implementation:

    DefintionBlock entry:

    Code (Text):

    External (_SB_.PC03.BR3A, DeviceObj)    // (from opcode)
    External (_SB_.PC03.BR3A.PEGP, DeviceObj)    // (from opcode)
    External (_SB_.PC03.BR3A.SL09, DeviceObj)    // (from opcode)
    External (DTGP, MethodObj)    // 5 Arguments (from opcode)
     

    ASUS XG-C100C AQC107 PCI Device Implementation:


    Code (Text):
    Scope (\_SB.PC03.BR3A)
        {
            Scope (SL09)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Scope (PEGP)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Device (XGBE)
            {
                Name (_ADR, Zero)  // _ADR: Address
                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                {
                    If (LEqual (Arg2, Zero))
                    {
                        Return (Buffer (One)
                        {
                             0x03
                        })
                    }

                    Store (Package (0x10)
                        {
                            "AAPL,slot-name",
                            Buffer (0x07)
                            {
                                "Slot-6"
                            },

                            "built-in",
                            Buffer (One)
                            {
                                 0x00
                            },

                            "name",
                            Buffer (0x33)
                            {
                                "ASUS XG-C100C Aquantia AQC107 10-Gigabit Ethernet"
                            },

                            "model",
                            Buffer (0x11)
                            {
                                "Apple AQC107-AFW"
                            },

                            "location",
                            Buffer (0x02)
                            {
                                "1"
                            },

                            "subsystem-id",
                            Buffer (0x04)
                            {
                                 0x87, 0x01, 0x00, 0x00
                            },

                            "device-id",
                            Buffer (0x04)
                            {
                                 0xB1, 0x07, 0x00, 0x00
                            },

                            "subsystem-vendor-id",
                            Buffer (0x04)
                            {
                                 0x6B, 0x10, 0x00, 0x00
                            }
                        }, Local0)
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                    Return (Local0)
                }
            }
        }
    Intel X540-T1 PCI Device Implementation:

    Code (Text):
    Scope (\_SB.PC03.BR3A)
        {
            Scope (SL09)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Scope (PEGP)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Device (XGBE)
            {
                Name (_ADR, Zero)  // _ADR: Address
                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                {
                    If (LEqual (Arg2, Zero))
                    {
                        Return (Buffer (One)
                        {
                             0x03
                        })
                    }

                    Store (Package (0x10)
                        {
                            "AAPL,slot-name",
                            Buffer (0x07)
                            {
                                "Slot-6"
                            },

                            "built-in",
                            Buffer (One)
                            {
                                 0x00
                            },

                            "name",
                            Buffer (0x22)
                            {
                                "Intel X540-T1 10-Gigabit Ethernet"
                            },

                            "model",
                            Buffer (0x22)
                            {
                                "Intel X540-T1 10-Gigabit Ethernet"
                            },

                            "location",
                            Buffer (0x02)
                            {
                                "1"
                            },

                            "subsystem-id",
                            Buffer (0x04)
                            {
                                 0x0A, 0x00, 0x00, 0x00
                            },

                            "device-id",
                            Buffer (0x04)
                            {
                                 0x28, 0x15, 0x00, 0x00
                            },

                            "subsystem-vendor-id",
                            Buffer (0x04)
                            {
                                 0x86, 0x80, 0x00, 0x00
                            }
                        }, Local0)
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                    Return (Local0)
                }
            }
        }

    Small-Tree P2EI0G-2T PCI Device Implementation:

    Code (Text):
    Scope (\_SB.PC03.BR3A)
        {
            Scope (SL09)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Scope (PEGP)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Device (XGBE)
            {
                Name (_ADR, Zero)  // _ADR: Address
                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                {
                    If (LEqual (Arg2, Zero))
                    {
                        Return (Buffer (One)
                        {
                             0x03
                        })
                    }

                    Store (Package (0x10)
                        {
                            "AAPL,slot-name",
                            Buffer (0x07)
                            {
                                "Slot-6"
                            },

                            "built-in",
                            Buffer (One)
                            {
                                 0x00
                            },

                            "name",
                            Buffer (0x30)
                            {
                                "Small-Tree P2EI0G-2T 10-Gigabit Ethernet Port 1"
                            },

                            "model",
                            Buffer (0x29)
                            {
                                "Small-Tree P2EI0G-2T 10-Gigabit Ethernet"
                            },

                            "location",
                            Buffer (0x02)
                            {
                                "1"
                            },

                            "subsystem-id",
                            Buffer (0x04)
                            {
                                 0x0A, 0x00, 0x00, 0x00
                            },

                            "device-id",
                            Buffer (0x04)
                            {
                                 0x28, 0x15, 0x00, 0x00
                            },

                            "subsystem-vendor-id",
                            Buffer (0x04)
                            {
                                 0x86, 0x80, 0x00, 0x00
                            }
                        }, Local0)
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                    Return (Local0)
                }
            }

            Device (XGBF)
            {
                Name (_ADR, One)  // _ADR: Address
                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                {
                    If (LEqual (Arg2, Zero))
                    {
                        Return (Buffer (One)
                        {
                             0x03
                        })
                    }

                    Store (Package (0x10)
                        {
                            "AAPL,slot-name",
                            Buffer (0x07)
                            {
                                "Slot-6"
                            },

                            "built-in",
                            Buffer (One)
                            {
                                 0x00
                            },

                            "name",
                            Buffer (0x30)
                            {
                                "Small-Tree P2EI0G-2T 10-Gigabit Ethernet Port 2"
                            },

                            "model",
                            Buffer (0x29)
                            {
                                "Small-Tree P2EI0G-2T 10-Gigabit Ethernet"
                            },

                            "location",
                            Buffer (0x02)
                            {
                                "1"
                            },

                            "subsystem-id",
                            Buffer (0x04)
                            {
                                 0x0A, 0x00, 0x00, 0x00
                            },

                            "device-id",
                            Buffer (0x04)
                            {
                                 0x28, 0x15, 0x00, 0x00
                            },

                            "subsystem-vendor-id",
                            Buffer (0x04)
                            {
                                 0x86, 0x80, 0x00, 0x00
                            }
                        }, Local0)
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                    Return (Local0)
                }
            }
        }
     
    The 10-Gigabit NIC XGBE PCI implementation is mainly of cosmetic nature. For each PCIe Adapter and for different slot populations the XGBE PCI device implementation needs to be adopted/modified (see details above). This also states for the respective ACPI path entries "PC03", "BR3A" and respective SL09 -> PEGP and PEGP -> XGBE ACPI Replacements (in compliance with the iMac Pro 10GB ACPI variable nomenclature), directly performed within the SSDT-X299-iMacPro.aml. Those not employing any 10-GBit NIC in their system, can simply remove the corresponding SSDT PCI device implementation.

    E.9.2.10) - ETH0/ETH1 - onboard LAN Controller PCI Implementation:

    DefintionBlock entry:

    Code (Text):

    External (_SB_.PCI0, DeviceObj)    // (from opcode)
    External (_SB_.PCI0.GBE1, DeviceObj)    // (from opcode)
    External (_SB_.PCI0.RP02, DeviceObj)    // (from opcode)
    External (_SB_.PCI0.RP02.D0A4, DeviceObj)    // (from opcode)
    External (_SB_.PCI0.RP02.PXSX, DeviceObj)    // (from opcode)
    External (DTGP, MethodObj)    // 5 Arguments (from opcode)
     
    PCI Device Implementation:

    Code (Text):

        Scope (\_SB.PCI0)
        {
            Scope (GBE1)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Device (ETH0)
            {
                Name (_ADR, 0x001F0006)  // _ADR: Address
                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                {
                    Store (Package (0x10)
                        {
                            "AAPL,slot-name",
                            Buffer (0x09)
                            {
                                "Built In"
                            },

                            "built-in",
                            Buffer (One)
                            {
                                 0x00
                            },

                            "name",
                            Buffer (0x16)
                            {
                                "Intel I219V2 Ethernet"
                            },

                            "model",
                            Buffer (0x2A)
                            {
                                "Intel I219V2 PCI Express Gigabit Ethernet"
                            },

                            "location",
                            Buffer (0x02)
                            {
                                "2"
                            },

                            "subsystem-id",
                            Buffer (0x04)
                            {
                                 0x72, 0x86, 0x00, 0x00
                            },

                            "device-id",
                            Buffer (0x04)
                            {
                                 0xB8, 0x15, 0x00, 0x00
                            },

                            "subsystem-vendor-id",
                            Buffer (0x04)
                            {
                                 0x43, 0x10, 0x00, 0x00
                            }
                        }, Local0)
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                    Return (Local0)
                }
            }
        }

        Scope (\_SB.PCI0.RP02)
        {
            Scope (D0A4)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Scope (PXSX)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Device (ETH1)
            {
                Name (_ADR, Zero)  // _ADR: Address
                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                {
                    Store (Package (0x10)
                        {
                            "AAPL,slot-name",
                            Buffer (0x09)
                            {
                                "Built In"
                            },

                            "built-in",
                            Buffer (One)
                            {
                                 0x00
                            },

                            "name",
                            Buffer (0x16)
                            {
                                "Intel I211VA Ethernet"
                            },

                            "model",
                            Buffer (0x2A)
                            {
                                "Intel I211VA PCI Express Gigabit Ethernet"
                            },

                            "location",
                            Buffer (0x02)
                            {
                                "2"
                            },

                            "subsystem-id",
                            Buffer (0x04)
                            {
                                 0xF0, 0x85, 0x00, 0x00
                            },

                            "device-id",
                            Buffer (0x04)
                            {
                                 0x39, 0x15, 0x00, 0x00
                            },

                            "subsystem-vendor-id",
                            Buffer (0x04)
                            {
                                 0x43, 0x10, 0x00, 0x00
                            }
                        }, Local0)
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                    Return (Local0)
                }
            }
        }
     
    Note that the ETH0/ETH1 Intel I219V2 PCI Express Gigabit Ethernet and Intel I211VA PCI Express Gigabit Ethernet onboard LAN controller PCI implementations are of pure cosmetic nature and only valid for ASUS Prime X299 Deluxe or X299 mainboards with the same LAN Controller configuration. Owners of different X299 mainboards have to verify and adopt/modify if necessary the device these PCI device implementations by means of IOREG. Note the PCI0.GBE1 -> PCI0.ETH0, PCI0.RP02.D0A4 -> PCI0.RP02.PXSX and PCI0.RP02.PXSX -> PCI0.RP02.ETH1 ACPI replacements directly performed within the DSDT.

    E.9.2.11) - ARPT - OSX WIFI Broadcom BCM94360CD 802.11 a/b/g/n/ac + Bluetooth 4.0 AirPort Controller PCI Implementation:

    DefintionBlock entry:

    Code (Text):

    External (_SB_.PC03.BR3D, DeviceObj)    // (from opcode)
    External (_SB_.PC03.BR3D.PEGP, DeviceObj)    // (from opcode)
    External (_SB_.PC03.BR3D.SL0C, DeviceObj)    // (from opcode)
    External (DTGP, MethodObj)    // 5 Arguments (from opcode)
     
    PCI Device Implementation:

    Code (Text):

        Scope (_SB.PC03.BR3D)
        {
            Scope (SL0C)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Scope (PEGP)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Device (ARPT)
            {
                Name (_ADR, Zero)  // _ADR: Address
                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                {
                    Store (Package (0x0E)
                        {
                            "built-in",
                            Buffer (One)
                            {
                                 0x00
                            },

                            "device-id",
                            Buffer (0x04)
                            {
                                 0xA0, 0x43, 0x00, 0x00
                            },

                            "AAPL,slot-name",
                            Buffer (0x07)
                            {
                                "Slot-3"
                            },

                            "device_type",
                            Buffer (0x13)
                            {
                                "AirPort Controller"
                            },

                            "model",
                            Buffer (0x4A)
                            {
                                "OSX WIFI Broadcom BCM94360CD 802.11 a/b/g/n/ac + Bluetooth 4.0 Controller"
                            },

                            "compatible",
                            Buffer (0x0D)
                            {
                                "pci14e4,43a0"
                            },

                            "name",
                            Buffer (0x10)
                            {
                                "AirPort Extreme"
                            }
                        }, Local0)
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                    Return (Local0)
                }
            }
        }
     
    The ARPT OSX WIFI Broadcom BCM94360CD 802.11 a/b/g/n/ac + Bluetooth 4.0 AirPort Controller PCI device implementation is of pure cosmetic nature and only valid for users of the latter WIFI/Bluetooth PCIe Adapter in PCIe Slot 3. Users of this PCIe Adapter within a PCIe slot population different from PCIe Slot 3 have to adapt/modify the respective device path "PC03","BR3D","ARPT" and likely also the respective ACPI Replacements PC03.BR3D.SL0C -> PC03.BR3D.PEGP and PC03.BR3D.PEGP -> PC03.BR3D.ARPT, directly performed within the SSDT. Users of the Asus Prime X299 Deluxe onboard Bluetooth chipset controller or with a completely different WIFI/Bluetooth configuration have to adopt the entire Airport PCI implementation by means of IOREG.

    E.9.2.12) - DTGP Method:

    Code (Text):
    Method (DTGP, 5, NotSerialized)
        {
            If (LEqual (Arg0, ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")))
            {
                If (LEqual (Arg1, One))
                {
                    If (LEqual (Arg2, Zero))
                    {
                        Store (Buffer (One)
                            {
                                 0x03
                            }, Arg4)
                        Return (One)
                    }

                    If (LEqual (Arg2, One))
                    {
                        Return (One)
                    }
                }
            }

            Store (Buffer (One)
                {
                     0x00
                }, Arg4)
            Return (Zero)
        }
    }
    The DTG Method Implementation is required for SSDT functionality and has not to be modified or adopted in any case.

    E.9.2.13) - Debugging Sleep Issues:

    For debugging sleep issues as proposed by Pike Alpha, one can add SSDT-SLEEP.aml to /EFI/CLOVER/ACPI/patched and follow Pike's comment and advices provided at https://pikeralpha.wordpress.com/2017/01/12/debugging-sleep-issues/


    E.9.3) SSDT-X299-TB3-iMacPro.aml PCI Implementation

    The Thunderbolt PCI device implementation was formerly part of the SSDT-X299-iMacPro.aml. Due to it's exponentially growing complexity and length, this latter PCI device implementation has now been outsourced from SSDT-X299-iMacPro.aml and newly realised within it's proper and mostly independent aml-file, namely SSDT-X299-TB3-iMacPro.aml.

    The current Thunderbolt PCI device implementation is kept has close as possible to SSDT-9.aml of @TheOfficialGypsy 's iMac Pro dumb. It also contains implementations mainly developed by @apfelnico and @nmano, but also @mork vom Ork, @Matthew82, @maleorderbride and @TheRacerMaster.

    It is valid for both, the ASUS TBEX 3 and Gigabyte Alpine Ridge and allows for TB and XHC USB sleep/wake functionality with the THB_C cable plugged/unplugged to the thunderbolt onboard header of the ASUS Prime X299 Deluxe. While XHC USB hot plug seems to work fine within this configuration, TB hot plug seems to require the removal of the THB_C cable. Thank's to @crismac2013 and @LeleTuratti for their findings!

    >>> https://youtu.be/Jakp5dCoFvY <<<


    Users of this PCIe Adapter within a PCIe slot population different from PCIe Slot 4 have to adapt/modify the respective ACPI path entries "PC01", "BR1A" and respective SL01 -> PEGP and PEGP -> UPSB ACPI Replacements, directly performed within the SSDT.

    DefintionBlock entry:

    Code (Text):

        External (_SB_.PC01, DeviceObj)    // (from opcode)
        External (_SB_.PC01.BR1A, DeviceObj)    // (from opcode)
        External (_SB_.PC01.BR1A.PEGP, DeviceObj)    // (from opcode)
        External (_SB_.PC01.BR1A.SL01, DeviceObj)    // (from opcode)
        External (AG16, MethodObj)    // 0 Arguments (from opcode)
        External (DTGP, MethodObj)    // 5 Arguments (from opcode)
        External (IO80, UnknownObj)    // (from opcode)
        External (PG16, MethodObj)    // 0 Arguments (from opcode)
        External (PICM, MethodObj)    // 0 Arguments (from opcode)
     
    PCI Device Implementation:

    Code (Text):

        OperationRegion (GNVS, SystemMemory, 0x4FEE6918, 0x0403)
        Field (GNVS, AnyAcc, Lock, Preserve)
        {
            OSYS,   16
        }

        Method (OSDW, 0, NotSerialized)
        {
            If (LEqual (OSYS, 0x2710))
            {
                Return (One)
            }
            Else
            {
                Return (Zero)
            }
        }

        Method (PINI, 0, NotSerialized)
        {
            Store (0x07DC, OSYS)
            If (XOSI ("Darwin"))
            {
                Store (0x2710, OSYS)
            }
            ElseIf (XOSI ("Linux"))
            {
                Store (0x03E8, OSYS)
            }
            ElseIf (XOSI ("Windows 2009"))
            {
                Store (0x07D9, OSYS)
            }
            ElseIf (XOSI ("Windows 2012"))
            {
                Store (0x07DC, OSYS)
            }
            Else
            {
                Store (0x07DC, OSYS)
            }
        }

        Method (XOSI, 1, NotSerialized)
        {
            Store (Package (0x0E)
                {
                    "Darwin",
                    "Linux",
                    "Windows",
                    "Windows 2001",
                    "Windows 2001 SP2",
                    "Windows 2001.1",
                    "Windows 2001.1 SP1",
                    "Windows 2006",
                    "Windows 2006 SP1",
                    "Windows 2006.1",
                    "Windows 2009",
                    "Windows 2012",
                    "Windows 2013",
                    "Windows 2015"
                }, Local0)
            Return (LNotEqual (Ones, Match (Local0, MEQ, Arg0, MTR, Zero, Zero)))
        }

        Scope (_SB.PC01.BR1A)
        {
            Scope (SL01)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Scope (PEGP)
            {
                Name (_STA, Zero)  // _STA: Status
            }

            Device (UPSB)
            {
                Name (_ADR, Zero)  // _ADR: Address
                OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                Field (A1E0, ByteAcc, NoLock, Preserve)
                {
                    AVND,   32,
                    BMIE,   3,
                    Offset (0x18),
                    PRIB,   8,
                    SECB,   8,
                    SUBB,   8,
                    Offset (0x1E),
                        ,   13,
                    MABT,   1
                }

                OperationRegion (A1E1, PCI_Config, 0xC0, 0x40)
                Field (A1E1, ByteAcc, NoLock, Preserve)
                {
                    Offset (0x01),
                    Offset (0x02),
                    Offset (0x04),
                    Offset (0x08),
                    Offset (0x0A),
                        ,   5,
                    TPEN,   1,
                    Offset (0x0C),
                    SSPD,   4,
                        ,   16,
                    LACR,   1,
                    Offset (0x10),
                        ,   4,
                    LDIS,   1,
                    LRTN,   1,
                    Offset (0x12),
                    CSPD,   4,
                    CWDT,   6,
                        ,   1,
                    LTRN,   1,
                        ,   1,
                    LACT,   1,
                    Offset (0x14),
                    Offset (0x30),
                    TSPD,   4
                }

                OperationRegion (A1E2, PCI_Config, 0x80, 0x08)
                Field (A1E2, ByteAcc, NoLock, Preserve)
                {
                    Offset (0x01),
                    Offset (0x02),
                    Offset (0x04),
                    PSTA,   2
                }

                Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                {
                    Return (SECB)
                }

                Method (_STA, 0, NotSerialized)  // _STA: Status
                {
                    Return (0x0F)
                }

                Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                {
                    Return (One)
                }

                Device (DSB0)
                {
                    Name (_ADR, Zero)  // _ADR: Address
                    Name (_SUN, 0x04)  // _SUN: Slot User Number
                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                    Field (A1E0, ByteAcc, NoLock, Preserve)
                    {
                        AVND,   32,
                        BMIE,   3,
                        Offset (0x18),
                        PRIB,   8,
                        SECB,   8,
                        SUBB,   8,
                        Offset (0x1E),
                            ,   13,
                        MABT,   1
                    }

                    OperationRegion (A1E1, PCI_Config, 0xC0, 0x40)
                    Field (A1E1, ByteAcc, NoLock, Preserve)
                    {
                        Offset (0x01),
                        Offset (0x02),
                        Offset (0x04),
                        Offset (0x08),
                        Offset (0x0A),
                            ,   5,
                        TPEN,   1,
                        Offset (0x0C),
                        SSPD,   4,
                            ,   16,
                        LACR,   1,
                        Offset (0x10),
                            ,   4,
                        LDIS,   1,
                        LRTN,   1,
                        Offset (0x12),
                        CSPD,   4,
                        CWDT,   6,
                            ,   1,
                        LTRN,   1,
                            ,   1,
                        LACT,   1,
                        Offset (0x14),
                        Offset (0x30),
                        TSPD,   4
                    }

                    OperationRegion (A1E2, PCI_Config, 0x80, 0x08)
                    Field (A1E2, ByteAcc, NoLock, Preserve)
                    {
                        Offset (0x01),
                        Offset (0x02),
                        Offset (0x04),
                        PSTA,   2
                    }

                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                    {
                        Return (SECB)
                    }

                    Method (_STA, 0, NotSerialized)  // _STA: Status
                    {
                        Return (0x0F)
                    }

                    Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                    {
                        Return (One)
                    }

                    Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                    {
                        If (LNot (Arg2))
                        {
                            Return (Buffer (One)
                            {
                                 0x03                                        
                            })
                        }

                        Return (Package (0x02)
                        {
                            "PCIHotplugCapable",
                            One
                        })
                    }

                    Device (NHI0)
                    {
                        Name (_ADR, Zero)  // _ADR: Address
                        Name (_STR, Unicode ("Thunderbolt"))  // _STR: Description String
                        Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                        {
                            Return (Zero)
                        }

                        OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                        Field (A1E0, ByteAcc, NoLock, Preserve)
                        {
                            AVND,   32,
                            BMIE,   3,
                            Offset (0x18),
                            PRIB,   8,
                            SECB,   8,
                            SUBB,   8,
                            Offset (0x1E),
                                ,   13,
                            MABT,   1
                        }

                        Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                        {
                            If (LEqual (Arg2, Zero))
                            {
                                Return (Buffer (One)
                                {
                                     0x03                                        
                                })
                            }

                            Store (Package (0x13)
                                {
                                    "AAPL,slot-name",
                                    Buffer (0x07)
                                    {
                                        "Slot-4"
                                    },

                                    "built-in",
                                    Buffer (One)
                                    {
                                         0x00                                        
                                    },

                                    "device_type",
                                    Buffer (0x19)
                                    {
                                        "Thunderbolt 3 Controller"
                                    },

                                    "model",
                                    Buffer (0x20)
                                    {
                                        "Intel DSL6540 Thunderbolt 3 NHI"
                                    },

                                    "name",
                                    Buffer (0x25)
                                    {
                                        "Intel DSL6540 Thunderbolt Controller"
                                    },

                                    "pathcr",
                                    Buffer (One)
                                    {
                                        /* 0000 */  0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                        /* 0008 */  0x00, 0x00, 0x07, 0x00, 0x10, 0x00, 0x10, 0x00,
                                        /* 0010 */  0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                        /* 0018 */  0x00, 0x00, 0x07, 0x00, 0x10, 0x00, 0x10, 0x00,
                                        /* 0020 */  0x01, 0x00, 0x00, 0x00, 0x05, 0x00, 0x0E, 0x00,
                                        /* 0028 */  0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                        /* 0030 */  0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                        /* 0038 */  0x00, 0x00, 0x02, 0x00, 0x02, 0x00, 0x01, 0x00,
                                        /* 0040 */  0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                        /* 0048 */  0x00, 0x00, 0x07, 0x00, 0x02, 0x00, 0x01, 0x00
                                    },

                                    "ThunderboltDROM",
                                    Buffer (One)
                                    {
                                        /* 0000 */  0x6D, 0x01, 0xC5, 0x49, 0xD5, 0x3E, 0x21, 0x01,
                                        /* 0008 */  0x00, 0x04, 0xCE, 0x8D, 0x61, 0x01, 0x5E, 0x00,
                                        /* 0010 */  0x01, 0x00, 0x0C, 0x00, 0x01, 0x00, 0x08, 0x81,
                                        /* 0018 */  0x81, 0x02, 0x81, 0x00, 0x00, 0x00, 0x08, 0x82,
                                        /* 0020 */  0x91, 0x01, 0x81, 0x00, 0x00, 0x00, 0x08, 0x83,
                                        /* 0028 */  0x81, 0x04, 0x81, 0x01, 0x00, 0x00, 0x08, 0x84,
                                        /* 0030 */  0x91, 0x03, 0x81, 0x01, 0x00, 0x00, 0x08, 0x85,
                                        /* 0038 */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x86,
                                        /* 0040 */  0x20, 0x03, 0x87, 0x80, 0x02, 0xC8, 0x05, 0x89,
                                        /* 0048 */  0x50, 0x00, 0x00, 0x05, 0x8A, 0x50, 0x00, 0x00,
                                        /* 0050 */  0x02, 0xCB, 0x0D, 0x01, 0x41, 0x70, 0x70, 0x6C,
                                        /* 0058 */  0x65, 0x20, 0x49, 0x6E, 0x63, 0x2E, 0x00, 0x0C,
                                        /* 0060 */  0x02, 0x4D, 0x61, 0x63, 0x69, 0x6E, 0x74, 0x6F,
                                        /* 0068 */  0x73, 0x68, 0x00                            
                                    },

                                    "ThunderboltConfig",
                                    Buffer (One)
                                    {
                                        /* 0000 */  0x01, 0x02, 0xFF, 0xFF, 0x04, 0x00, 0x03, 0x01,
                                        /* 0008 */  0x01, 0x00, 0x04, 0x00, 0x05, 0x01, 0x02, 0x00,
                                        /* 0010 */  0x03, 0x00, 0x03, 0x01, 0x01, 0x00, 0x01, 0x00,
                                        /* 0018 */  0x03, 0x01, 0x02, 0x00, 0x04, 0x00, 0x03, 0x00
                                    },

                                    "power-save",
                                    One,
                                    Buffer (One)
                                    {
                                         0x00                                        
                                    }
                                }, Local0)
                            DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                            Return (Local0)
                        }

                        Return (Zero)
                    }
                }

                Device (DSB1)
                {
                    Name (_ADR, 0x00010000)  // _ADR: Address
                    Name (_SUN, 0x04)  // _SUN: Slot User Number
                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                    Field (A1E0, ByteAcc, NoLock, Preserve)
                    {
                        AVND,   32,
                        BMIE,   3,
                        Offset (0x18),
                        PRIB,   8,
                        SECB,   8,
                        SUBB,   8,
                        Offset (0x1E),
                            ,   13,
                        MABT,   1
                    }

                    OperationRegion (A1E1, PCI_Config, 0xC0, 0x40)
                    Field (A1E1, ByteAcc, NoLock, Preserve)
                    {
                        Offset (0x01),
                        Offset (0x02),
                        Offset (0x04),
                        Offset (0x08),
                        Offset (0x0A),
                            ,   5,
                        TPEN,   1,
                        Offset (0x0C),
                        SSPD,   4,
                            ,   16,
                        LACR,   1,
                        Offset (0x10),
                            ,   4,
                        LDIS,   1,
                        LRTN,   1,
                        Offset (0x12),
                        CSPD,   4,
                        CWDT,   6,
                            ,   1,
                        LTRN,   1,
                            ,   1,
                        LACT,   1,
                        Offset (0x14),
                        Offset (0x30),
                        TSPD,   4
                    }

                    OperationRegion (A1E2, PCI_Config, 0x80, 0x08)
                    Field (A1E2, ByteAcc, NoLock, Preserve)
                    {
                        Offset (0x01),
                        Offset (0x02),
                        Offset (0x04),
                        PSTA,   2
                    }

                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                    {
                        Return (SECB)
                    }

                    Method (_STA, 0, NotSerialized)  // _STA: Status
                    {
                        Return (0x0F)
                    }

                    Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                    {
                        Return (Zero)
                    }

                    Device (UPS0)
                    {
                        Name (_ADR, Zero)  // _ADR: Address
                        OperationRegion (ARE0, PCI_Config, Zero, 0x04)
                        Field (ARE0, ByteAcc, NoLock, Preserve)
                        {
                            AVND,   16
                        }

                        Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                        {
                            If (OSDW ())
                            {
                                Return (One)
                            }

                            Return (Zero)
                        }

                        Device (DSB0)
                        {
                            Name (_ADR, Zero)  // _ADR: Address
                            OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                            Field (A1E0, ByteAcc, NoLock, Preserve)
                            {
                                AVND,   32,
                                BMIE,   3,
                                Offset (0x18),
                                PRIB,   8,
                                SECB,   8,
                                SUBB,   8,
                                Offset (0x1E),
                                    ,   13,
                                MABT,   1,
                                Offset (0x3E),
                                    ,   6,
                                SBRS,   1
                            }

                            Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                            {
                                Return (SECB)
                            }

                            Method (_STA, 0, NotSerialized)  // _STA: Status
                            {
                                Return (0x0F)
                            }

                            Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                            {
                                If (OSDW ())
                                {
                                    Return (One)
                                }

                                Return (Zero)
                            }

                            Device (DEV0)
                            {
                                Name (_ADR, Zero)  // _ADR: Address
                                Method (_STA, 0, NotSerialized)  // _STA: Status
                                {
                                    Return (0x0F)
                                }

                                Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                {
                                    If (OSDW ())
                                    {
                                        Return (One)
                                    }

                                    Return (Zero)
                                }
                            }
                        }

                        Device (DSB3)
                        {
                            Name (_ADR, 0x00030000)  // _ADR: Address
                            OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                            Field (A1E0, ByteAcc, NoLock, Preserve)
                            {
                                AVND,   32,
                                BMIE,   3,
                                Offset (0x18),
                                PRIB,   8,
                                SECB,   8,
                                SUBB,   8,
                                Offset (0x1E),
                                    ,   13,
                                MABT,   1
                            }

                            Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                            {
                                Return (SECB)
                            }

                            Method (_STA, 0, NotSerialized)  // _STA: Status
                            {
                                Return (0x0F)
                            }

                            Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                            {
                                If (OSDW ())
                                {
                                    Return (One)
                                }

                                Return (Zero)
                            }

                            Device (UPS0)
                            {
                                Name (_ADR, Zero)  // _ADR: Address
                                OperationRegion (ARE0, PCI_Config, Zero, 0x04)
                                Field (ARE0, ByteAcc, NoLock, Preserve)
                                {
                                    AVND,   16
                                }

                                Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                {
                                    If (OSDW ())
                                    {
                                        Return (One)
                                    }

                                    Return (Zero)
                                }

                                Device (DSB0)
                                {
                                    Name (_ADR, Zero)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1,
                                        Offset (0x3E),
                                            ,   6,
                                        SBRS,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Device (DEV0)
                                    {
                                        Name (_ADR, Zero)  // _ADR: Address
                                        Method (_STA, 0, NotSerialized)  // _STA: Status
                                        {
                                            Return (0x0F)
                                        }
                                    }
                                }

                                Device (DSB3)
                                {
                                    Name (_ADR, 0x00030000)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                    {
                                        If (OSDW ())
                                        {
                                            Return (One)
                                        }

                                        Return (Zero)
                                    }

                                    Device (DEV0)
                                    {
                                        Name (_ADR, Zero)  // _ADR: Address
                                        Method (_STA, 0, NotSerialized)  // _STA: Status
                                        {
                                            Return (0x0F)
                                        }

                                        Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                        {
                                            If (OSDW ())
                                            {
                                                Return (One)
                                            }

                                            Return (Zero)
                                        }
                                    }
                                }

                                Device (DSB4)
                                {
                                    Name (_ADR, 0x00040000)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                    {
                                        If (OSDW ())
                                        {
                                            Return (One)
                                        }

                                        Return (Zero)
                                    }

                                    Device (DEV0)
                                    {
                                        Name (_ADR, Zero)  // _ADR: Address
                                        Method (_STA, 0, NotSerialized)  // _STA: Status
                                        {
                                            Return (0x0F)
                                        }

                                        Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                        {
                                            If (OSDW ())
                                            {
                                                Return (One)
                                            }

                                            Return (Zero)
                                        }
                                    }
                                }

                                Device (DSB5)
                                {
                                    Name (_ADR, 0x00050000)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                    {
                                        If (OSDW ())
                                        {
                                            Return (One)
                                        }

                                        Return (Zero)
                                    }
                                }

                                Device (DSB6)
                                {
                                    Name (_ADR, 0x00060000)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                    {
                                        If (OSDW ())
                                        {
                                            Return (One)
                                        }

                                        Return (Zero)
                                    }
                                }
                            }
                        }

                        Device (DSB4)
                        {
                            Name (_ADR, 0x00040000)  // _ADR: Address
                            OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                            Field (A1E0, ByteAcc, NoLock, Preserve)
                            {
                                AVND,   32,
                                BMIE,   3,
                                Offset (0x18),
                                PRIB,   8,
                                SECB,   8,
                                SUBB,   8,
                                Offset (0x1E),
                                    ,   13,
                                MABT,   1
                            }

                            Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                            {
                                Return (SECB)
                            }

                            Method (_STA, 0, NotSerialized)  // _STA: Status
                            {
                                Return (0x0F)
                            }

                            Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                            {
                                If (OSDW ())
                                {
                                    Return (One)
                                }

                                Return (Zero)
                            }

                            Device (UPS0)
                            {
                                Name (_ADR, Zero)  // _ADR: Address
                                OperationRegion (ARE0, PCI_Config, Zero, 0x04)
                                Field (ARE0, ByteAcc, NoLock, Preserve)
                                {
                                    AVND,   16
                                }

                                Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                {
                                    If (OSDW ())
                                    {
                                        Return (One)
                                    }

                                    Return (Zero)
                                }

                                Device (DSB0)
                                {
                                    Name (_ADR, Zero)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1,
                                        Offset (0x3E),
                                            ,   6,
                                        SBRS,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Device (DEV0)
                                    {
                                        Name (_ADR, Zero)  // _ADR: Address
                                        Method (_STA, 0, NotSerialized)  // _STA: Status
                                        {
                                            Return (0x0F)
                                        }

                                        Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                        {
                                            If (OSDW ())
                                            {
                                                Return (One)
                                            }

                                            Return (Zero)
                                        }
                                    }
                                }

                                Device (DSB3)
                                {
                                    Name (_ADR, 0x00030000)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                    {
                                        If (OSDW ())
                                        {
                                            Return (One)
                                        }

                                        Return (Zero)
                                    }

                                    Device (DEV0)
                                    {
                                        Name (_ADR, Zero)  // _ADR: Address
                                        Method (_STA, 0, NotSerialized)  // _STA: Status
                                        {
                                            Return (0x0F)
                                        }

                                        Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                        {
                                            If (OSDW ())
                                            {
                                                Return (One)
                                            }

                                            Return (Zero)
                                        }
                                    }
                                }

                                Device (DSB4)
                                {
                                    Name (_ADR, 0x00040000)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                    {
                                        If (OSDW ())
                                        {
                                            Return (One)
                                        }

                                        Return (Zero)
                                    }

                                    Device (DEV0)
                                    {
                                        Name (_ADR, Zero)  // _ADR: Address
                                        Method (_STA, 0, NotSerialized)  // _STA: Status
                                        {
                                            Return (0x0F)
                                        }

                                        Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                        {
                                            If (OSDW ())
                                            {
                                                Return (One)
                                            }

                                            Return (Zero)
                                        }
                                    }
                                }

                                Device (DSB5)
                                {
                                    Name (_ADR, 0x00050000)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                    {
                                        If (OSDW ())
                                        {
                                            Return (One)
                                        }

                                        Return (Zero)
                                    }
                                }

                                Device (DSB6)
                                {
                                    Name (_ADR, 0x00060000)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                    {
                                        If (OSDW ())
                                        {
                                            Return (One)
                                        }

                                        Return (Zero)
                                    }
                                }
                            }
                        }

                        Device (DSB5)
                        {
                            Name (_ADR, 0x00050000)  // _ADR: Address
                            OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                            Field (A1E0, ByteAcc, NoLock, Preserve)
                            {
                                AVND,   32,
                                BMIE,   3,
                                Offset (0x18),
                                PRIB,   8,
                                SECB,   8,
                                SUBB,   8,
                                Offset (0x1E),
                                    ,   13,
                                MABT,   1
                            }

                            Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                            {
                                Return (SECB)
                            }

                            Method (_STA, 0, NotSerialized)  // _STA: Status
                            {
                                Return (0x0F)
                            }

                            Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                            {
                                If (OSDW ())
                                {
                                    Return (One)
                                }

                                Return (Zero)
                            }
                        }

                        Device (DSB6)
                        {
                            Name (_ADR, 0x00060000)  // _ADR: Address
                            OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                            Field (A1E0, ByteAcc, NoLock, Preserve)
                            {
                                AVND,   32,
                                BMIE,   3,
                                Offset (0x18),
                                PRIB,   8,
                                SECB,   8,
                                SUBB,   8,
                                Offset (0x1E),
                                    ,   13,
                                MABT,   1
                            }

                            Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                            {
                                Return (SECB)
                            }

                            Method (_STA, 0, NotSerialized)  // _STA: Status
                            {
                                Return (0x0F)
                            }

                            Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                            {
                                If (OSDW ())
                                {
                                    Return (One)
                                }

                                Return (Zero)
                            }
                        }
                    }
                }

                Device (DSB2)
                {
                    Name (_ADR, 0x00020000)  // _ADR: Address
                    OperationRegion (PXCS, PCI_Config, Zero, 0xE0)
                    Field (PXCS, AnyAcc, NoLock, Preserve)
                    {
                        VDID,   32,
                        Offset (0x54),
                            ,   6,
                        HPCE,   1,
                        Offset (0x5A),
                        ABPX,   1,
                            ,   2,
                        PDCX,   1,
                            ,   2,
                        PDSX,   1,
                        Offset (0x5B),
                        Offset (0x60),
                        Offset (0x62),
                        PMEX,   1,
                        Offset (0xDC),
                            ,   31,
                        PMCS,   1
                    }

                    Method (DEVS, 0, NotSerialized)
                    {
                        If (LEqual (VDID, Ones))
                        {
                            Return (Zero)
                        }
                        Else
                        {
                            Return (0x0F)
                        }
                    }

                    Method (HPME, 0, Serialized)
                    {
                        If (PMEX)
                        {
                            Store (0xC8, Local0)
                            While (Local0)
                            {
                                Store (One, PMEX)
                                If (PMEX)
                                {
                                    Decrement (Local0)
                                }
                                Else
                                {
                                    Store (Zero, Local0)
                                }
                            }

                            Store (One, PMCS)
                        }
                    }

                    Method (_PRT, 0, NotSerialized)  // _PRT: PCI Routing Table
                    {
                        If (PICM ())
                        {
                            Return (AG16 ())
                        }

                        Return (PG16 ())
                    }

                    Device (XHC5)
                    {
                        Name (_ADR, Zero)  // _ADR: Address
                        Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                        {
                            If (LEqual (Arg2, Zero))
                            {
                                Return (Buffer (One)
                                {
                                     0x03                                        
                                })
                            }

                            Store (Package (0x10)
                                {
                                    "AAPL,slot-name",
                                    Buffer (0x0C)
                                    {
                                        "Slot-4"
                                    },

                                    "built-in",
                                    Buffer (One)
                                    {
                                         0x00                                        
                                    },

                                    "model",
                                    Buffer (0x2A)
                                    {
                                        "Intel DSL6540 XHC USB 3.1 Type-C (Type-A)"
                                    },

                                    "name",
                                    Buffer (0x25)
                                    {
                                        "Intel DSL6540 XHC USB 3.1 Controller"
                                    },

                                    "device_type",
                                    Buffer (0x13)
                                    {
                                        "USB 3.1 Controller"
                                    },

                                    "USBBusNumber",
                                    Zero,
                                    "UsbCompanionControllerPresent",
                                    One,
                                    "AAPL,XHCI-clock-id",
                                    One
                                }, Local0)
                            DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                            Return (Local0)
                        }

                        Method (_PRW, 0, NotSerialized)  // _PRW: Power Resources for Wake
                        {
                            Return (Package (0x02)
                            {
                                0x6D,
                                Zero
                            })
                        }

                        Device (RHUB)
                        {
                            Name (_ADR, Zero)  // _ADR: Address
                            Device (SSP1)
                            {
                                Name (_ADR, One)  // _ADR: Address
                                Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
                                {
                                    0xFF,
                                    0x09,
                                    Zero,
                                    Zero
                                })
                                Name (_PLD, Package (0x01)  // _PLD: Physical Location of Device
                                {
                                    Buffer (0x10)
                                    {
                                        /* 0000 */  0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                        /* 0008 */  0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
                                    }
                                })
                                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                                {
                                    If (LEqual (Arg2, Zero))
                                    {
                                        Return (Buffer (One)
                                        {
                                             0x03                                        
                                        })
                                    }

                                    Return (Package (0x02)
                                    {
                                        "UsbCPortNumber",
                                        One
                                    })
                                }
                            }

                            Device (SSP2)
                            {
                                Name (_ADR, 0x02)  // _ADR: Address
                                Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
                                {
                                    0xFF,
                                    0x09,
                                    Zero,
                                    Zero
                                })
                                Name (_PLD, Package (0x01)  // _PLD: Physical Location of Device
                                {
                                    Buffer (0x10)
                                    {
                                        /* 0000 */  0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                        /* 0008 */  0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
                                    }
                                })
                                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                                {
                                    If (LEqual (Arg2, Zero))
                                    {
                                        Return (Buffer (One)
                                        {
                                             0x03                                        
                                        })
                                    }

                                    Return (Package (0x02)
                                    {
                                        "UsbCPortNumber",
                                        0x02
                                    })
                                }
                            }

                            Device (HS01)
                            {
                                Name (_ADR, 0x03)  // _ADR: Address
                                Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
                                {
                                    0xFF,
                                    0x09,
                                    Zero,
                                    Zero
                                })
                                Name (_PLD, Package (0x01)  // _PLD: Physical Location of Device
                                {
                                    Buffer (0x10)
                                    {
                                        /* 0000 */  0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                        /* 0008 */  0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
                                    }
                                })
                            }

                            Device (HS02)
                            {
                                Name (_ADR, 0x04)  // _ADR: Address
                                Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
                                {
                                    0xFF,
                                    0x09,
                                    Zero,
                                    Zero
                                })
                                Name (_PLD, Package (0x01)  // _PLD: Physical Location of Device
                                {
                                    Buffer (0x10)
                                    {
                                        /* 0000 */  0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                                        /* 0008 */  0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
                                    }
                                })
                            }
                        }
                    }
                }

                Device (DSB4)
                {
                    Name (_ADR, 0x00040000)  // _ADR: Address
                    Name (_SUN, 0x04)  // _SUN: Slot User Number
                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                    Field (A1E0, ByteAcc, NoLock, Preserve)
                    {
                        AVND,   32,
                        BMIE,   3,
                        Offset (0x18),
                        PRIB,   8,
                        SECB,   8,
                        SUBB,   8,
                        Offset (0x1E),
                            ,   13,
                        MABT,   1
                    }

                    OperationRegion (A1E1, PCI_Config, 0xC0, 0x40)
                    Field (A1E1, ByteAcc, NoLock, Preserve)
                    {
                        Offset (0x01),
                        Offset (0x02),
                        Offset (0x04),
                        Offset (0x08),
                        Offset (0x0A),
                            ,   5,
                        TPEN,   1,
                        Offset (0x0C),
                        SSPD,   4,
                            ,   16,
                        LACR,   1,
                        Offset (0x10),
                            ,   4,
                        LDIS,   1,
                        LRTN,   1,
                        Offset (0x12),
                        CSPD,   4,
                        CWDT,   6,
                            ,   1,
                        LTRN,   1,
                            ,   1,
                        LACT,   1,
                        Offset (0x14),
                        Offset (0x30),
                        TSPD,   4
                    }

                    OperationRegion (A1E2, PCI_Config, 0x80, 0x08)
                    Field (A1E2, ByteAcc, NoLock, Preserve)
                    {
                        Offset (0x01),
                        Offset (0x02),
                        Offset (0x04),
                        PSTA,   2
                    }

                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                    {
                        Return (SECB)
                    }

                    Method (_STA, 0, NotSerialized)  // _STA: Status
                    {
                        Return (0x0F)
                    }

                    Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                    {
                        Return (Zero)
                    }

                    Device (UPS0)
                    {
                        Name (_ADR, Zero)  // _ADR: Address
                        OperationRegion (ARE0, PCI_Config, Zero, 0x04)
                        Field (ARE0, ByteAcc, NoLock, Preserve)
                        {
                            AVND,   16
                        }

                        Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                        {
                            If (OSDW ())
                            {
                                Return (One)
                            }

                            Return (Zero)
                        }

                        Device (DSB0)
                        {
                            Name (_ADR, Zero)  // _ADR: Address
                            OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                            Field (A1E0, ByteAcc, NoLock, Preserve)
                            {
                                AVND,   32,
                                BMIE,   3,
                                Offset (0x18),
                                PRIB,   8,
                                SECB,   8,
                                SUBB,   8,
                                Offset (0x1E),
                                    ,   13,
                                MABT,   1,
                                Offset (0x3E),
                                    ,   6,
                                SBRS,   1
                            }

                            Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                            {
                                Return (SECB)
                            }

                            Method (_STA, 0, NotSerialized)  // _STA: Status
                            {
                                Return (0x0F)
                            }

                            Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                            {
                                If (OSDW ())
                                {
                                    Return (One)
                                }

                                Return (Zero)
                            }

                            Device (DEV0)
                            {
                                Name (_ADR, Zero)  // _ADR: Address
                                Method (_STA, 0, NotSerialized)  // _STA: Status
                                {
                                    Return (0x0F)
                                }

                                Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                {
                                    If (OSDW ())
                                    {
                                        Return (One)
                                    }

                                    Return (Zero)
                                }
                            }
                        }

                        Device (DSB3)
                        {
                            Name (_ADR, 0x00030000)  // _ADR: Address
                            OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                            Field (A1E0, ByteAcc, NoLock, Preserve)
                            {
                                AVND,   32,
                                BMIE,   3,
                                Offset (0x18),
                                PRIB,   8,
                                SECB,   8,
                                SUBB,   8,
                                Offset (0x1E),
                                    ,   13,
                                MABT,   1
                            }

                            Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                            {
                                Return (SECB)
                            }

                            Method (_STA, 0, NotSerialized)  // _STA: Status
                            {
                                Return (0x0F)
                            }

                            Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                            {
                                If (OSDW ())
                                {
                                    Return (One)
                                }

                                Return (Zero)
                            }

                            Device (UPS0)
                            {
                                Name (_ADR, Zero)  // _ADR: Address
                                OperationRegion (ARE0, PCI_Config, Zero, 0x04)
                                Field (ARE0, ByteAcc, NoLock, Preserve)
                                {
                                    AVND,   16
                                }

                                Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                {
                                    If (OSDW ())
                                    {
                                        Return (One)
                                    }

                                    Return (Zero)
                                }

                                Device (DSB0)
                                {
                                    Name (_ADR, Zero)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1,
                                        Offset (0x3E),
                                            ,   6,
                                        SBRS,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Device (DEV0)
                                    {
                                        Name (_ADR, Zero)  // _ADR: Address
                                        Method (_STA, 0, NotSerialized)  // _STA: Status
                                        {
                                            Return (0x0F)
                                        }
                                    }
                                }

                                Device (DSB3)
                                {
                                    Name (_ADR, 0x00030000)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                    {
                                        If (OSDW ())
                                        {
                                            Return (One)
                                        }

                                        Return (Zero)
                                    }

                                    Device (DEV0)
                                    {
                                        Name (_ADR, Zero)  // _ADR: Address
                                        Method (_STA, 0, NotSerialized)  // _STA: Status
                                        {
                                            Return (0x0F)
                                        }

                                        Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                        {
                                            If (OSDW ())
                                            {
                                                Return (One)
                                            }

                                            Return (Zero)
                                        }
                                    }
                                }

                                Device (DSB4)
                                {
                                    Name (_ADR, 0x00040000)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                    {
                                        If (OSDW ())
                                        {
                                            Return (One)
                                        }

                                        Return (Zero)
                                    }

                                    Device (DEV0)
                                    {
                                        Name (_ADR, Zero)  // _ADR: Address
                                        Method (_STA, 0, NotSerialized)  // _STA: Status
                                        {
                                            Return (0x0F)
                                        }

                                        Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                        {
                                            If (OSDW ())
                                            {
                                                Return (One)
                                            }

                                            Return (Zero)
                                        }
                                    }
                                }

                                Device (DSB5)
                                {
                                    Name (_ADR, 0x00050000)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                    {
                                        If (OSDW ())
                                        {
                                            Return (One)
                                        }

                                        Return (Zero)
                                    }
                                }

                                Device (DSB6)
                                {
                                    Name (_ADR, 0x00060000)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                    {
                                        If (OSDW ())
                                        {
                                            Return (One)
                                        }

                                        Return (Zero)
                                    }
                                }
                            }
                        }

                        Device (DSB4)
                        {
                            Name (_ADR, 0x00040000)  // _ADR: Address
                            OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                            Field (A1E0, ByteAcc, NoLock, Preserve)
                            {
                                AVND,   32,
                                BMIE,   3,
                                Offset (0x18),
                                PRIB,   8,
                                SECB,   8,
                                SUBB,   8,
                                Offset (0x1E),
                                    ,   13,
                                MABT,   1
                            }

                            Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                            {
                                Return (SECB)
                            }

                            Method (_STA, 0, NotSerialized)  // _STA: Status
                            {
                                Return (0x0F)
                            }

                            Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                            {
                                If (OSDW ())
                                {
                                    Return (One)
                                }

                                Return (Zero)
                            }

                            Device (UPS0)
                            {
                                Name (_ADR, Zero)  // _ADR: Address
                                OperationRegion (ARE0, PCI_Config, Zero, 0x04)
                                Field (ARE0, ByteAcc, NoLock, Preserve)
                                {
                                    AVND,   16
                                }

                                Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                {
                                    If (OSDW ())
                                    {
                                        Return (One)
                                    }

                                    Return (Zero)
                                }

                                Device (DSB0)
                                {
                                    Name (_ADR, Zero)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1,
                                        Offset (0x3E),
                                            ,   6,
                                        SBRS,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Device (DEV0)
                                    {
                                        Name (_ADR, Zero)  // _ADR: Address
                                        Method (_STA, 0, NotSerialized)  // _STA: Status
                                        {
                                            Return (0x0F)
                                        }

                                        Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                        {
                                            If (OSDW ())
                                            {
                                                Return (One)
                                            }

                                            Return (Zero)
                                        }
                                    }
                                }

                                Device (DSB3)
                                {
                                    Name (_ADR, 0x00030000)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                    {
                                        If (OSDW ())
                                        {
                                            Return (One)
                                        }

                                        Return (Zero)
                                    }

                                    Device (DEV0)
                                    {
                                        Name (_ADR, Zero)  // _ADR: Address
                                        Method (_STA, 0, NotSerialized)  // _STA: Status
                                        {
                                            Return (0x0F)
                                        }

                                        Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                        {
                                            If (OSDW ())
                                            {
                                                Return (One)
                                            }

                                            Return (Zero)
                                        }
                                    }
                                }

                                Device (DSB4)
                                {
                                    Name (_ADR, 0x00040000)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                    {
                                        If (OSDW ())
                                        {
                                            Return (One)
                                        }

                                        Return (Zero)
                                    }

                                    Device (DEV0)
                                    {
                                        Name (_ADR, Zero)  // _ADR: Address
                                        Method (_STA, 0, NotSerialized)  // _STA: Status
                                        {
                                            Return (0x0F)
                                        }

                                        Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                        {
                                            If (OSDW ())
                                            {
                                                Return (One)
                                            }

                                            Return (Zero)
                                        }
                                    }
                                }

                                Device (DSB5)
                                {
                                    Name (_ADR, 0x00050000)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                    {
                                        If (OSDW ())
                                        {
                                            Return (One)
                                        }

                                        Return (Zero)
                                    }
                                }

                                Device (DSB6)
                                {
                                    Name (_ADR, 0x00060000)  // _ADR: Address
                                    OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                                    Field (A1E0, ByteAcc, NoLock, Preserve)
                                    {
                                        AVND,   32,
                                        BMIE,   3,
                                        Offset (0x18),
                                        PRIB,   8,
                                        SECB,   8,
                                        SUBB,   8,
                                        Offset (0x1E),
                                            ,   13,
                                        MABT,   1
                                    }

                                    Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                                    {
                                        Return (SECB)
                                    }

                                    Method (_STA, 0, NotSerialized)  // _STA: Status
                                    {
                                        Return (0x0F)
                                    }

                                    Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                                    {
                                        If (OSDW ())
                                        {
                                            Return (One)
                                        }

                                        Return (Zero)
                                    }
                                }
                            }
                        }

                        Device (DSB5)
                        {
                            Name (_ADR, 0x00050000)  // _ADR: Address
                            OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                            Field (A1E0, ByteAcc, NoLock, Preserve)
                            {
                                AVND,   32,
                                BMIE,   3,
                                Offset (0x18),
                                PRIB,   8,
                                SECB,   8,
                                SUBB,   8,
                                Offset (0x1E),
                                    ,   13,
                                MABT,   1
                            }

                            Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                            {
                                Return (SECB)
                            }

                            Method (_STA, 0, NotSerialized)  // _STA: Status
                            {
                                Return (0x0F)
                            }

                            Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                            {
                                If (OSDW ())
                                {
                                    Return (One)
                                }

                                Return (Zero)
                            }
                        }

                        Device (DSB6)
                        {
                            Name (_ADR, 0x00060000)  // _ADR: Address
                            OperationRegion (A1E0, PCI_Config, Zero, 0x40)
                            Field (A1E0, ByteAcc, NoLock, Preserve)
                            {
                                AVND,   32,
                                BMIE,   3,
                                Offset (0x18),
                                PRIB,   8,
                                SECB,   8,
                                SUBB,   8,
                                Offset (0x1E),
                                    ,   13,
                                MABT,   1
                            }

                            Method (_BBN, 0, NotSerialized)  // _BBN: BIOS Bus Number
                            {
                                Return (SECB)
                            }

                            Method (_STA, 0, NotSerialized)  // _STA: Status
                            {
                                Return (0x0F)
                            }

                            Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                            {
                                If (OSDW ())
                                {
                                    Return (One)
                                }

                                Return (Zero)
                            }
                        }
                    }
                }

                Method (_DSM, 4, NotSerialized)  // _DSM: Device-Specific Method
                {
                    If (LNot (Arg2))
                    {
                        Return (Buffer (One)
                        {
                             0x03                                        
                        })
                    }

                    Return (Package (0x02)
                    {
                        "PCI-Thunderbolt",
                        One
                    })
                }
            }
        }
    }
     
    Thanks to @nmano we now also have an additional SSDT for all ASUS X299 mainboards, i.e SSDT-TB3-BR1A-XHC5-HPME.aml, which needs to be implemented in /EFI/Clover/ACPI/patches/ and fixes further TB ACPI dependencies. This SSDT will also permanently load the TB NHI0 and XHC USB PCI drivers, even in case that no TB devices are connected. Apparently it also resolves some TB sleep/wake issues.

    Note that both TB-SSDTs are mainboard and slot-dependend! With the TBEX 3 or Alpine Ridge in a PCIe slot different from PCIe Slot-4, one needs to adopt both SSDT and DSDT patch in concordance with IOREG.

    All Gigabyte users with the TBEX 3 or Alpine Ridge in PCIe Slot-4 can use SSDT-X299-TB3-iMacPro-GB.aml and SSDT-TB3-RP21-XHC5-HPME.aml instead.



    E.10) System Overview CPU Cosmetics

    As our Skylake-X CPU at present will not be properly recognised by OS X, Apple's System Overview ("About This Mac") reveals incomplete or simply wrong CPU details. Many times CPU's like the i9-7980XE are implemented as "unknown"...

    Overview.png

    I recently discovered on InsanelyMac a sophisticated fix of pure cosmetic nature developed by Shaneee (also thanks to fabiosun for pointing me to this direction), which allows to implement those CPU details you want to be implemented. For the sake of simplicity, I summarise the necessary steps once more below. Note that the following example is only valid for systems with English as main system language. If your system language is German, French, Spanish, Chinese etc., substitute "English.lproj" in the individual commands by the "lproj" of your System language! Thanks to @PedroJSkywalker for this latter important advice!

    1.) Open a terminal and use the following commands:

    Code (Text):
    cp /System/Library/PrivateFrameworks/AppleSystemInfo.framework/Versions/A/Resources/English.lproj/AppleSystemInfo.strings ~/Desktop/
    Code (Text):
    sudo mv /System/Library/PrivateFrameworks/AppleSystemInfo.framework/Versions/A/Resources/English.lproj/AppleSystemInfo.strings /System/Library/PrivateFrameworks/AppleSystemInfo.framework/Versions/A/Resources/English.lproj/AppleSystemInfo.strings-Backup
    2.) Open "AppleSystemInfo.strings" on your Desktop with TextWrangler and change

    Code (Text):
    <key>UnknownCPUKind</key>
    <string>Unknown</string>
    to what ever you want. In my case I choose:

    Code (Text):
    <key>UnknownCPUKind</key>
    <string>4,4 GHz 18-core 36-thread Skylake-X i9-7980XE</string>
    Save "AppleSystemInfo.strings"

    3.) Run the following terminal commands:

    Code (Text):
    sudo codesign -f -s - ~/Desktop/AppleSystemInfo.strings
    Code (Text):
    sudo cp ~/Desktop/AppleSystemInfo.strings /System/Library/PrivateFrameworks/AppleSystemInfo.framework/Versions/A/Resources/English.lproj/
    and reboot your system.

    4.) Open your config.plist with Clover Configurator and in Section "CPU" set "Type" to "Unknown". Save the config.plist and reboot.

    5.) Apple's System Overview now will reveal the following details:

    Overview-correct.png


    As fall back option enter the following terminal commands:

    Code (Text):
    sudo rm /System/Library/PrivateFrameworks/AppleSystemInfo.framework/Versions/A/Resources/English.lproj/AppleSystemInfo.strings
    Code (Text):
    sudo mv /System/Library/PrivateFrameworks/AppleSystemInfo.framework/Versions/A/Resources/English.lproj/AppleSystemInfo.strings-Backup /System/Library/PrivateFrameworks/AppleSystemInfo.framework/Versions/A/Resources/English.lproj/AppleSystemInfo.string
    and reboot.

    E.11) iMac Pro Boot Splash Screen Cosmetics

    Based on the ideas and instructions of @Matthew82 from InsanelyMac, I achieved an iMacPro ASUS Boot Splash Screen

    ASUS-Splash-Screen.png

    by means of the following procedure:

    1.) Installation of the BREW distribution:

    a.) Open a terminal and change to "bash" shell.

    Code (Text):
    bash
    b.) Now enter the following "bash" terminal command and follow the standard BREW installation instructions:

    Code (Text):
    /usr/bin/ruby -e "$(curl -fsSL https://raw.githubusercontent.com/Homebrew/install/master/install)"

    2.) After the successful installation of the BREW distribution, we have to implement the QT5 distribution, again by using a "bash" terminal shell. Just enter the following "bash" terminal commands:

    Code (Text):
    brew install qt5
    Code (Text):
    brew link qt5 --force
    3.) After successfully implementing BREW and QT5 and if not already performed in Section B.1), we can now download the most actual CodeRush UEFIPatch distribution from Github to our home directory with the following terminal command:

    Code (Text):
    git clone https://github.com/LongSoft/UEFITool
    4.) Now compile the UEFI Tool distribution with the following terminal commands:

    Code (Text):
    cd /UEFITools/
    qmake uefitool.pro
    make
    5.) Download and unzip iMacPro.raw to your Desktop.

    6.) Now launch by UEFITool by clicking on the newly compiled UEFITool.app in the UEFITools Folder in your home directory.

    a.) Select "File" -> "Open image file" and load your patched or unpatched BIOS Firmware distribution.

    Select "Search.." in the UEFITool "Edit" Menu and perform a "GUID" search of "7BB28B99-61BB-11D5-9A5D-0090273FC14D" with "Header only"...

    Guid-Search.png

    You will receive a message "GUID pattern "7BB28B99-61BB-11D5-9A5D-0090273FC14D" found as .... in 7BB28B99-....". Double click on that message and search for the "Raw section" accompanying the "7BB28B99-...." entry, which indeed is the Boot Image, which you can easily verify by extracting the raw section body (right-click on "Raw section" and select "Extract body") to your Desktop and by subsequently opening the extracted raw-file directly with Apple's "Preview.app" (right-click an the raw file and select "Open with.." -> Preview.app).

    b.) To exchange the default original ASUS Boot Logo image file stored in "Raw Section" by the iMacPro.raw image file that you previously downloaded to your Desktop, right-click again on "Raw section", select this time "Replace body" and select the iMacPro.raw image file on your Desktop.

    UefiTool.png

    Note that the actual image dimension of iMacPro.raw (2131pix x 1457pix) was adopted for its use on my 38" LG 38UC99. For monitors with reduce screen resolution, iMacPro.raw might have to be adopted to an image dimension that suites your particular screen resolution, before its upload to "Raw section". If the Boot Logo image dimension is too big for your Monitor's screen resolution, you might just end up with a black screen during the BIOS initialisation at boot.

    To do so, select in the Preview.app Menu -> "Tools" -> "Adjust Size". Change the image dimension and save the modified image with "File" -> "Export". In the "Export menu" press "Save", after selecting "JPEG" under "Format" , after choosing "Desktop" as the place to store the image, and after entering the new file name, which has to end with ".jpg".

    Double-check by right-clicking on the resulting jpg image file and selecting "Get Info" that its file size does no exceed 200KB by far. If the latter would be the case, you would not be able to save the modified BIOS Firware file subsequently.

    Finally just rename your new "XXXX.jpg" file to "XXXX.raw....

    I guess, that by following the procedure detailed above, it is obvious that iMacPro.raw also can be substituted by any other image of your personal choice. Just be aware that it's background colour should be black (ecstatic reason for a its nice integration within the else black ASUS BIOS Boot Screen)

    c.) After replacing "Raw Section" with iMacPro.raw or the XXX.raw image of your choice, save your modified BIOS Firmware File with the Option "File" -> "Save Image File..."

    d.) Copy your modified BIOS Firmware file to a USB3.0 Flash Drive, formatted with FAT32.

    e.) Reboot, enter the Mainboard BIOS and save your BIOS settings to the USB Flash Drive

    f.) Flash your mainboard BIOS with the modified BIOS Firmware

    g.) Renter the Mainboard BIOS and restore your BIOS settings from the USB Flash Drive

    h.) Save your restored BIOS settings with (F7) and (F10), reboot and you are done.

    Just don't forget to set BIOS Setting "Boot Logo Display" to "Auto", when using this new approach. Any different setting might result in a black screen during BIOS initialisation.

    E.12) iMac Pro Desktop Background cosmetics

    It might be nice to equip your iMac Pro X299 also with the adequate iMac Pro Desktop Background.

    1.) Download, unzip and copy imac-pro-wallpaper.jpg.zip to your Dektop

    2.) Right-click with the mouse on your Desktop and select "Change Desktop Background.."

    3.) In the left column click on the "+" and add your Desktop Folder

    4.) Select imac-pro-wallpaper.jpg to be your new Desktop Background


    E.13) Native Display Brightness Control / Native NightShift Functionality for Monitors with DCC/IC Support

    1.) Native Display Brightness Control

    Many of you might miss the ability to control the display brightness with the F1/F2 keys on original Apple Keyboards, or with FN&F1/FN&F2 on non-Apple keyboards.

    @bensge wrote a small but genius application to do just that on any Hackintosh System and to show the native OSX brightness system UI.

    NativeDisplayBrightness-UI.png

    The App works for desktops and monitors that support DDC/CI. You have to connect your monitor to your GPU either via HDMI or DP. Note that you also have to enable DDC/CI support on your monitor to make the program work.

    This application automatically adds itself as a Login Item in your User Settings in System Preferences.

    UserSettings.png

    Please carefully read all instructions on his NativeDiplayBrightness GitHub page before downloading the program. An extensive discussion can be followed on his respective thread on Tonymacx.

    To download and compile the source code of the App to your home directory, enter the following terminal command:

    Code (Text):

    git clone https://github.com/Bensge/NativeDisplayBrightness/
    cd ~/NativeDisplayBrightness/
    xcodebuild
     
    The compiled NativeDisplayBrightness.app can be found in subfolder ~/NativeDisplayBrightness/build/Release

    To add the application as a Login Item in your User Settings in System Preferences, just double click on the App.

    If you're using an original Apple keyboard, this app won't work with your F1/F2 keys straight away. On non-Apple keyboards it won't work out off the box, even with FN&F1/FN&F2 as it should work .

    In both cases you need to additionally add two KernelToPatch entries in your config.plist in Section "Kernel and Kext Patches" of Clover Configurator:

    Code (Text):

    Name*                                  Find* [Hex]                                          Replace* [HEX]                                       Comment

    com.apple.driver.AppleHIDKeyboard      30783030 30373030 33612c30 78666630 31303032 31      30783030 30373030 33612c30 78303030 37303033 61      by Wern

    com.apple.driver.AppleHIDKeyboard      30783030 30373030 33622c30 78666630 31303032 30      30783030 30373030 33622c30 78303030 37303033 62      by Wern
     
    Note, that there is no support yet for multi-monitor configurations.

    Thanks to user @Ramalama for drawing my attention to this amazingly util implementation and for all his related instructive help and support.

    2.) Native NightShift Functionality for Monitors with DDC/IC Support

    To enable native NightShift functionality on the 38" LG 38UC99, one needs to download and unzip the respective Display Override Profile DisplayProductID-76fc, subsequently properly sign the file, and finally copy the file to /System/Library/Displays/Contents/Resources/Overrides/DisplayVendorID-1e6d/.

    The latter to steps can be done by the following terminal commands:

    Code (Text):
    cd ~/Downloads
    sudo codesign -f -s - DisplayProductID-76fc
    sudo cp DisplayProductID-76fc /System/Library/Displays/Contents/Resources/Overrides/DisplayVendorID-1e6d/
     
    Subsequently you have to reboot and to newly adjust your Screen Resolution under "Display" in System Preferences.

    DisplayReosultionSetup.png

    And your are done:

    Nightshift.png

    Note that the attached Display Override Profile, does not allow a LG 38UC99 Monitor Frequency of 75Hz. Only 60Hz are supported.

    Many thanks to user @Ramalama for providing this approach to our community. NightShift should also work for the Acer 38" and Dell 38" Monitors. Yet @Ramalama misses the respective EDIDs. Any body with e.g. the Acer XR382CQK should immediately upload the requested information and contact @Ramalama by posting in this thread! Many thanks in advance!


    E.14) Logic-X and Audio Studio Software Functionality

    The ASUS BIOS patching, providing full read/write access for the OSX Kernel to the MSR 0xE2 register, apparently also circumvents the Intel SKZ7 bug and yet missing BIOS microcode implementations. The Xnu CPU Power Management (XCPM) is now solely handled by the OSX Kernel, which completely resolves all former Logic-X or other studio audio software implementations. The same states for all other X299 mainboards with factory-default open MSR 0xE2 register implementation.

    Nevertheless there is a second extremely important intrinsic LOGIC X configuration setting, which has to be adopted depending on the degree of sophistication of the studio audio hardware (Latency) in use.

    In the following description, I will provide the correct audio preference settings for the ASUS Prime X299 with the onboard Realtek ALC S1220A audio chip:

    1.) Within Logic X go to "Preferences" -> "Audio"

    2.) Under Advanced check "Show Advanced Tools"

    3.) Go back to the "Audio" settings and adopt "I/O Buffer Size" from "128" to e.g. "512" or even better "1024" Samples, in case you really use the onboard Realtek ALC S1220A audio chipset. Users of more sophisticated Studio Audio Hardware with better latencies have to adopt the I/O Buffer Size accordingly to their hardware implementation.

    logicx-audio-settings.png

    Now your Logic-X distribution should work absolutely flawless.

    To check the now flawless functionality and performance of Logic-X, download, unzip and run the attached Logic-X test sample Test Hyperthreading Bug.logicx.zip of @DSM2 attached at the bottom of this originating post/guide. Note that the test sample sound volume output is zero, for avoiding epileptic or panic attacks at audience side... this is just a test sample to check the Logic-X functionality and performance and not a chart breaking audio sample.

    Start Intel Power Gadget (IPG) in parallel and play the test sample with Logic-X:

    Logic-X functionality.png

    You will rapidly notice that everything fully behaves as expected. The Hyperthreading-sample plays flawless at alternated CPU frequencies.

    All credits to @DSM2.

    E.15) iStatMenus Hardware Monitoring

    Thanks to extended tweet session between @BJango, @gxsolace and myself, it seems that we achieved a major step forward in properly monitoring Skylake-X/X299 Hardware with iStatMenus. iStatMenus now correctly interfaces with the HWSensor and FakeSMC kext distribution provided by @interferenc.

    The most actual iStatMenus v6.1 distribution can be assessed at https://bjango.com/mac/istatmenus/

    The most actual HWSensor and FakeSMC kext distribution of @interferenc can be assessed at https://github.com/interferenc/HWSensors

    To compile the the HWSensor and FakeSMC kexts of @interferenc, perform the individual steps detailed below:

    1.)

    Code (Text):
    git clone https://github.com/interferenc/HWSensors
    2.)

    Code (Text):
    cp HWSensors ~/Desktop/
    3.)

    Code (Text):
    cd ~/Desktop/HWSensors
    4.)

    Code (Text):
    xcodebuild -project Versioning\ And\ Distribution.xcodeproj/
    5.)

    Code (Text):
    xcodebuild -project HWMonitor.xcodeproj/
    6.)

    Code (Text):
    xcodebuild -project HWSensors.xcodeproj -alltargets
    Subsequently, one finds the all compiled binaries in ~/Desktop/HWSensors/Binaries/.

    Note that all compiled kext binaries are once more attached towards the bottom of this originating thread (guide). Just download and unzip HW-Sensors-IF.zip and copy all kexts to /EFI/Clover/kexts/Other/. Note that this pre-compiled binary package already implements a modified GPU Sensor kext of @Kozlek, which should also account for Polaris GPUs.

    Many thanks to both @interferenc and @Bjango for their awesome and extensive contributions and brilliant work!

    Skylake-X/X299 iStatMenus Hardware Sensor Data:

    iStatMenusHWSensorData.png

    Skylake-X CPU Thread Utilisation Graphs:

    iStatMenus-CPU-Utilization.png


    To change from CPU core to thread utilisation monitoring, uncheck "Hide Hyper-Threading cores" in Section "CPU & GPU" of iStatMenus Preferences.

    iStatMenus-Preferences-1.png

    Temperature unites can be adjusted between Celsius, Fahrenheit and Kelvin in Section "Sensors" of iStatMenus Preferences.

    iStatMenus-Preferences-2.png


    F.) Benchmarking

    IMG_9290.jpg


    F.1) Sylake-X Intel I9-7980XE (4.8GHz) CPU Benchmarking

    i9.png

    xcpm-new-i9-7980XE-4.6GHz.png

    Geekbench CPU Benchmark:
    • Multi-Core Sore: 65.348
    • Single-Core Sore: 5.910
    Cinebench Cpu Benchmark:
    • 4.618 CB
    cpu-benchmarks.png

    Compare with recent Geekbench results for the 18-core iMacPro (W2191B):

    Geekbench CPU Benchmark:




      • Multi-Core Sore: 46.406
      • Single-Core Sore: 5.175
    Geekbench-iMacPro-W2191B.JPG


    F.2) Gigabyte AORUS GTX 1080 Ti Waterforce EB 11GB Extreme Edition Benchmarking

    IMG_9291.jpg

    Geekbench OpenGl and Metal2 Benchmarks:
    • OpenGL Sore: 229.965
    • Metal2 Sore: 242.393
    graphicsbench.png


    G.) Summary and Conclusion:

    Already during the first individual macOS High Sierra 10.13 beta releases, Syklake-X/X299 systems reached full functionality together with flawless stability. Now with final macOS High Sierra 10.13.6 (17G65), it might be the right moment to follow my build and Desktop Installation Guide to unfold the unbelievable Skylake-X/X299 potential together with macOS High Sierra 10.13 (special iMac Pro build)!

    I am quite optimistic that high-end builds based on extremely novel Skylake-X/X299 technology will find manifold application, not only in science and research at universities or research institutions, engineering facilities, or medical labs, etc... Skylake-X processors with up to 18 cores (36 threads) and turbo frequencies up to 4.8 GHz will make X299 to a "relatively cheap" but really serious alternative to the iMac Pro's and Mac Pro's. The principal intention of this desktop guide was to demonstrate, that we are able to build and configure fully functional and relatively "low-cost" high-end systems nowadays, which go far beyond of what Apple is able to offer at present or will be ever able to offer for some reasonable pricing. A Skylake-X/X299-System, that allows the use of all software-packages developed for MacOS, Unix, Linux or even Windows at the same time (e.g. think on Vine, Parallels, or a dual boot system configuration). The flexibility between different mainboards (Asus, Gigabyte, ASRock, MSI, etc.), different Skylake-X processors, and different RAM memory configurations (16-128GB) should make such system affordable for anybody (also home office, audio and video editing/production, etc.) and allow its perfect adaptation for the specific purpose, requirements and available budgets. It might not be necessary to outline, that current Skylake-X/X299 Systems perform absolutely stable on a 24/7/365 basis.

    I am a scientist, expert in solar physics, space weather forecast and related telescope/instrument/space-mission development. In the frame of my scientific research, I developed parallelized image reconstruction, spectral line inversion and numerical modeling algorithms/applications, which require tremendous parallelized calculation power, RAM memory and storage capacities to reduce, analyze and interpret extensive and pioneering scientific ground-based or space-born observational data sets. This basically was also the professional motivation for developing my innovative iMacPro macOS High Sierra Hackintosh Build iSPOR-S (the imaging Spectropolarimetric Parallel Organized Reconstruction Server running iSPOR-DP, the Imaging Spectropolarimetric Parallel Organized Reconstruction Data Pipeline software package for the GREGOR Fabry-Pérot Interferometer, located at the 1.5m GREGOR Solar Telescope (Europe's largest solar telescope) on Tenerife, Canary Islands, Spain) and for the entire respective iMac Pro Skylake-X/X299 Desktop User Guide Development, which hopefully will be also of benefit for others. Anybody interested can find more details on my personal webpage.

    kgp.png
     

    Attached Files:

    Last edited: Jul 11, 2018
  2. kgp

    kgp

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    Aug 18, 2017 at 1:01 AM #2
    kgp

    kgp

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    Update - First version of my Skylake-X/X299 macOS Sierra 10.12 and macOS High Sierra 10.13 Desktop Guides finished and released

    Enjoy! Happy to receive your feedback and suggestions!

    avatar4.png
     
    Last edited: Aug 18, 2017
  3. sparkyboy767

    sparkyboy767

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    Aug 18, 2017 at 5:40 PM #3
    sparkyboy767

    sparkyboy767

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    Awesome work. I'm looking to build something similar to your goal build, so I'll be keeping a close eye on your success here.

    Still unsure whether it's a good idea to go down the Skylake X road or wait for the iMac Pro to be released and go for the Xeons...
     
    kgp likes this.
  4. lokicat

    lokicat

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    Aug 18, 2017 at 11:11 PM #4
    lokicat

    lokicat

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    Thanks for sharing!

    A couple notes after I finally got installation to work on my i9-7900x and Gigabyte Aorus Gaming 7 and using PB5:
    • I had to use a blank drive that was already formatted to Mac extended journal. My fresh out of box SSD did not even show up in Disk Manager. Once formatted using a USB enclosure and my MacBook, it finally showed up upon installation boot. Basically, Disk Manager does nothing in the PB5 installation disk. This is the case for both SATA and NVME. I would think this will not be an issue once High Sierra is official launched.
    • Using the OP's EFI, I got random stop errors right at the start of boot on the USB installation drive, but reset and trying again completes installation. Once installed on my SSD, no problems with boot.
    • My USB ports are randomly working and not.
    • As OP said, the performance of the Gigabyte is not 100%. I think this is due to the state of the Gigabyte BIOS and enabling XCMP. I have already reported some BIOS features not working, even in Windows, to Gigabyte. I'm sure things will stabilize in the near future.
    • Not sure what the "Pre-Boot FileVault" boot option is on the Clover boot screen.
    • Not sure if it's good or bad to use the new APFS file system. I've read conflicting reports. I had my drive pre-formated to standard extended journaled and I don't think PB5 installation changed that.
    I don't know how much more I can try to do given that the Gigabyte BIOS is still beta (F7I) and there are no nVidia web drivers for my Titan xP. It also looks like we need the DEV community help with x299 USB ports. USB 2.0 works ok, but 3.0 is just totally random. I seriously doubt 3.1 works, but don't have anyway of testing.

    However, I do have better confidence now that full support will eventually come, perhaps later this year with the iMac Pro launch. This is all speculative of course.
     
  5. petrikleynhans

    petrikleynhans

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    Aug 19, 2017 at 10:59 AM #5
    petrikleynhans

    petrikleynhans

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    Hey KPG,

    I was wondering if I could pick your brain for a second.

    I have managed to install High Sierra on a MSI X299 mobo. I'm trying to install the nvidia web drivers for my MSI Geforce 1050Ti card. I go through the process in this guide. But whenever I select the web drivers (either manually or via the updater program) my system hangs with the following error.

    IOConsoleUsers: gIOScreenLockState 3, hs 0, bs 0, now 0, sm 0x0. error.

    Could you maybe shed some light?
     
  6. kgp

    kgp

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    Aug 19, 2017 at 11:14 AM #6
    kgp

    kgp

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    You need to install the 10.12.6 AppleGraphicsControl.kext on /S/L/E with the accurate permission suing Kext Utility. Then you have to patch the the "NVDAStartupWeb.kext" with the Nvidia Web Driver Updater v1.5 to the actual OS X version, i.e. "17A330h" (PB4/DP5) or "17A344b" (PB5/DP6))! One of the two steps you certainly missed!

    Cheers,

    KGP
     
  7. petrikleynhans

    petrikleynhans

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    Aug 19, 2017 at 1:32 PM #7
    petrikleynhans

    petrikleynhans

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    Must have done something wrong. I redid it, probably for the fourth time, and this time it worked! It's picking up and the resolution is right, but the refresh rate is not at the stated 60Hz. Also, I can't play any videos.

    But thank you, I'm making progress.
     
  8. kgp

    kgp

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    Aug 19, 2017 at 1:40 PM #8
    kgp

    kgp

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    If you have done everything properly your Nvidia Grapics card will be properly recognized under "Overview" and "System Report & Graphics/Display" of "ABOUT this Mac"

    Cheers,

    KGP
     
  9. kgp

    kgp

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    Aug 19, 2017 at 11:29 PM #9
    kgp

    kgp

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    o.k. I found the solution... in fact I never tried the easy workaround I implemented here.... but now I did ;)

    You have to do it exactly in the following order, do it precisely like this and exactly in this order!

    1.) Backup the 10.13 AppleGraphicsControl.kext
    2.) Install the patched WebDriver-378.05.05.25f01[up_17A315i].pkg
    3.) Reboot
    4.) Patch the the "NVDAStartupWeb.kext" with the Nvidia Web Driver Updater v1.5 to the actual OS X version, i.e. "17A330h"
    (PB4/DP5) or "17A344b" (PB5/DP6)​
    5.) Install the 10.12.6 AppleGraphicsControl.kext to /S/L/E with the accurate permission using Kext Utility or any other kext utility
    of your choice. ​
    6.) Apply the AGDPfix (Don't forget to apply this last step!!! otherwise you will end up with a black screen which you cannot
    circumvent!)​

    And wooooow, it works! :headbang:

    If you again mistake, you have to remove all NVDA*.kext files from /S/L/E and start from the beginning with the workaround ;)

    I updated the guide correspondingly!

    Cheers,

    KGP
     
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    Last edited: Aug 20, 2017
  10. trs96

    trs96 Moderator

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    Aug 20, 2017 at 10:55 AM #10
    trs96

    trs96 Moderator

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    Last edited: Aug 20, 2017

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