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[Guide] Native Power Management for Laptops

going to try this tonight. do I need working internet on the laptop? or can i download the ssdtPRGen.sh from my other mac?

still don't have my non intel wifi chip.
 
jacknick said:
going to try this tonight. do I need working internet on the laptop? or can i download the ssdtPRGen.sh from my other mac?

still don't have my non intel wifi chip.
Click to expand...

You can download on a different computer, then copy the ssdtPRgen.sh script using a USB.

Note that for the hardware in your profile, you DO NOT need ssdtPRgen.sh.
In fact, CPU PM (and IGPU PM) already implemented if you used a plist from the Clover laptop guide:
https://www.tonymacx86.com/threads/guide-booting-the-os-x-installer-on-laptops-with-clover.148093/
 
Hi Rehabman,

Ran geekbench and here are the results. does my PM look ok?

Code: 
AppleIntelInfo.kext v1.4 Copyright © 2012-2015 Pike R. Alpha. All rights reserved

Settings:
------------------------------------
logMSRs............................: 1
logIGPU............................: 1
logIntelRegs.......................: 1
logCStates.........................: 1
logIPGStyle........................: 1
InitialTSC.........................: 0x108eab0554e
MWAIT C-States.....................: 286531872

Model Specific Regiters
------------------------------------
MSR_CORE_THREAD_COUNT......(0x35)  : 0x40008
MSR_PLATFORM_INFO..........(0xCE)  : 0x4043DF1011400
MSR_PMG_CST_CONFIG_CONTROL.(0xE2)  : 0x1E008008
MSR_PMG_IO_CAPTURE_BASE....(0xE4)  : 0x51814
IA32_MPERF.................(0xE7)  : 0x193642706A
IA32_APERF.................(0xE8)  : 0x1B3C227A55
MSR_FLEX_RATIO.............(0x194) : 0x0
MSR_IA32_PERF_STATUS.......(0x198) : 0x1EC100001E00
MSR_IA32_PERF_CONTROL......(0x199) : 0xA00
IA32_CLOCK_MODULATION......(0x19A) : 0x0
IA32_THERM_STATUS..........(0x19C) : 0x883D0808
IA32_MISC_ENABLES..........(0x1A0) : 0x850089
MSR_MISC_PWR_MGMT..........(0x1AA) : 0x401CC1
MSR_TURBO_RATIO_LIMIT......(0x1AD) : 0x25252828
IA32_ENERGY_PERF_BIAS......(0x1B0) : 0x5
MSR_POWER_CTL..............(0x1FC) : 0x24005F
MSR_RAPL_POWER_UNIT........(0x606) : 0xA0E03
MSR_PKG_POWER_LIMIT........(0x610) : 0x42816000DD8160
MSR_PKG_ENERGY_STATUS......(0x611) : 0x18C1855
MSR_PKG_POWER_INFO.........(0x614) : 0x78
MSR_PP0_CURRENT_CONFIG.....(0x601) : 0x238
MSR_PP0_POWER_LIMIT........(0x638) : 0x0
MSR_PP0_ENERGY_STATUS......(0x639) : 0x88EABE
MSR_PP0_POLICY.............(0x63a) : 0x0
MSR_PKGC6_IRTL.............(0x60b) : 0x8876
MSR_PKG_C2_RESIDENCY.......(0x60d) : 0x2292B2AEA8
MSR_PKG_C3_RESIDENCY.......(0x3f8) : 0xBB1F9CFA9C
MSR_PKG_C6_RESIDENCY.......(0x3f9) : 0x0
IA32_TSC_DEADLINE..........(0x6E0) : 0x108EF3E6920
PCH device.................: 0x9D4E8086

Intel Register Data
------------------------------------
CPU_VGACNTRL...............: 0xFFFFFFFF
IS_ELSE(devid)
DCC........................: 0xffffffff ()
CHDECMISC..................: 0xffffffff (XOR bank, ch2 enh enabled, ch1 enh enabled, ch0 enh enabled, flex enabled, ep present)
C0DRB0.....................: 0xffffffff (0xffff)
C0DRB1.....................: 0xffffffff (0xffff)
C0DRB2.....................: 0xffffffff (0xffff)
C0DRB3.....................: 0xffffffff (0xffff)
C1DRB0.....................: 0xffffffff (0xffff)
C1DRB1.....................: 0xffffffff (0xffff)
C1DRB2.....................: 0xffffffff (0xffff)
C1DRB3.....................: 0xffffffff (0xffff)
C0DRA01....................: 0xffffffff (0xffff)
C0DRA23....................: 0xffffffff (0xffff)
C1DRA01....................: 0xffffffff (0xffff)
C1DRA23....................: 0xffffffff (0xffff)
PGETBL_CTL.................: 0xffffffff
VCLK_DIVISOR_VGA0..........: 0xffffffff (n = 63, m1 = 63, m2 = 63)
VCLK_DIVISOR_VGA1..........: 0xffffffff (n = 63, m1 = 63, m2 = 63)
VCLK_POST_DIV..............: 0xffffffff (vga0 p1 = 2, p2 = 4, vga1 p1 = 2, p2 = 4)
DPLL_TEST..................: 0xffffffff (, DPLLA N bypassed, DPLLA M bypassed, DPLLB N bypassed, DPLLB M bypassed)
CACHE_MODE_0...............: 0xffffffff
D_STATE....................: 0xffffffff
DSPCLK_GATE_D..............: 0xffffffff (clock gates disabled: DPUNIT_B VSUNIT VRHUNIT VRDUNIT AUDUNIT DPUNIT_A DPCUNIT TVRUNIT TVCUNIT TVFUNIT TVEUNIT DVSUNIT DSSUNIT DDBUNIT DPRUNIT DPFUNIT DPBMUNIT DPLSUNIT DPLUNIT DPOUNIT DPBUNIT DCUNIT DPUNIT VRUNIT RENCLK_GATE_D1.............: 0xffffffff
RENCLK_GATE_D2.............: 0xffffffff
SDVOB......................: 0xffffffff (enabled, pipe B, stall enabled, detected, gang mode)
SDVOC......................: 0xffffffff (enabled, pipe B, stall enabled, detected, gang mode)
SDVOUDI....................: 0xffffffff
DSPARB.....................: 0xffffffff
FW_BLC.....................: 0xffffffff
FW_BLC2....................: 0xffffffff
FW_BLC_SELF................: 0xffffffff
DSPFW1.....................: 0xffffffff
DSPFW2.....................: 0xffffffff
DSPFW3.....................: 0xffffffff
ADPA.......................: 0xffffffff (enabled, pipe B, +hsync, +vsync)
LVDS.......................: 0xffffffff (enabled, pipe B, 24 bit, 2 channels)
DVOA.......................: 0xffffffff (enabled, pipe B, unknown stall, +hsync, +vsync)
DVOB.......................: 0xffffffff (enabled, pipe B, unknown stall, +hsync, +vsync)
DVOC.......................: 0xffffffff (enabled, pipe B, unknown stall, +hsync, +vsync)
DVOA_SRCDIM................: 0xffffffff
DVOB_SRCDIM................: 0xffffffff
DVOC_SRCDIM................: 0xffffffff
BLC_PWM_CTL................: 0xffffffff
BLC_PWM_CTL2...............: 0xffffffff
PP_CONTROL.................: 0xffffffff (power target: on)
PP_STATUS..................: 0xffffffff (on, ready, sequencing unknown)
PP_ON_DELAYS...............: 0xffffffff
PP_OFF_DELAYS..............: 0xffffffff
PP_DIVISOR.................: 0xffffffff
PFIT_CONTROL...............: 0xffffffff
PFIT_PGM_RATIOS............: 0xffffffff
PORT_HOTPLUG_EN............: 0xffffffff
PORT_HOTPLUG_STAT..........: 0xffffffff
DSPACNTR...................: 0xffffffff (enabled, pipe B)
DSPASTRIDE.................: 0xffffffff (-1 bytes)
DSPAPOS....................: 0xffffffff (65535, 65535)
DSPASIZE...................: 0xffffffff (65536, 65536)
DSPABASE...................: 0xffffffff
DSPASURF...................: 0xffffffff
DSPATILEOFF................: 0xffffffff
PIPEACONF..................: 0xffffffff (enabled, double-wide)
PIPEASRC...................: 0xffffffff (65536, 65536)
PIPEASTAT..................: 0xffffffff (status: FIFO_UNDERRUN CRC_ERROR_ENABLE CRC_DONE_ENABLE GMBUS_EVENT_ENABLE VSYNC_INT_ENABLE DLINE_COMPARE_ENABLE DPST_EVENT_ENABLE LBLC_EVENT_ENABLE OFIELD_INT_ENABLE EFIELD_INT_ENABLE SVBLANK_INT_ENABLE VBLANK_INT_PIPEA_GMCH_DATA_M..........: 0xffffffff
PIPEA_GMCH_DATA_N..........: 0xffffffff
PIPEA_DP_LINK_M............: 0xffffffff
PIPEA_DP_LINK_N............: 0xffffffff
CURSOR_A_BASE..............: 0xffffffff
CURSOR_A_CONTROL...........: 0xffffffff
CURSOR_A_POSITION..........: 0xffffffff
FPA0.......................: 0xffffffff (n = 63, m1 = 63, m2 = 63)
FPA1.......................: 0xffffffff (n = 63, m1 = 63, m2 = 63)
DPLL_A.....................: 0xffffffff (enabled, dvo, unknown clock, unknown mode, p1 = 1, p2 = 0, using FPx1!)
DPLL_A_MD..................: 0xffffffff
HTOTAL_A...................: 0xffffffff (65536 active, 65536 total)
HBLANK_A...................: 0xffffffff (65536 start, 65536 end)
HSYNC_A....................: 0xffffffff (65536 start, 65536 end)
VTOTAL_A...................: 0xffffffff (65536 active, 65536 total)
VBLANK_A...................: 0xffffffff (65536 start, 65536 end)
VSYNC_A....................: 0xffffffff (65536 start, 65536 end)
BCLRPAT_A..................: 0xffffffff
VSYNCSHIFT_A...............: 0xffffffff
DSPBCNTR...................: 0xffffffff (enabled, pipe B)
DSPBSTRIDE.................: 0xffffffff (-1 bytes)
DSPBPOS....................: 0xffffffff (65535, 65535)
DSPBSIZE...................: 0xffffffff (65536, 65536)
DSPBBASE...................: 0xffffffff
DSPBSURF...................: 0xffffffff
DSPBTILEOFF................: 0xffffffff
PIPEBCONF..................: 0xffffffff (enabled, double-wide)
PIPEBSRC...................: 0xffffffff (65536, 65536)
PIPEBSTAT..................: 0xffffffff (status: FIFO_UNDERRUN CRC_ERROR_ENABLE CRC_DONE_ENABLE GMBUS_EVENT_ENABLE VSYNC_INT_ENABLE DLINE_COMPARE_ENABLE DPST_EVENT_ENABLE LBLC_EVENT_ENABLE OFIELD_INT_ENABLE EFIELD_INT_ENABLE SVBLANK_INT_ENABLE VBLANK_INT_PIPEB_GMCH_DATA_M..........: 0xffffffff
PIPEB_GMCH_DATA_N..........: 0xffffffff
PIPEB_DP_LINK_M............: 0xffffffff
PIPEB_DP_LINK_N............: 0xffffffff
CURSOR_B_BASE..............: 0xffffffff
CURSOR_B_CONTROL...........: 0xffffffff
CURSOR_B_POSITION..........: 0xffffffff
FPB0.......................: 0xffffffff (n = 63, m1 = 63, m2 = 63)
FPB1.......................: 0xffffffff (n = 63, m1 = 63, m2 = 63)
DPLL_B.....................: 0xffffffff (enabled, dvo, spread spectrum clock, unknown mode, p1 = 1, p2 = 0, using FPx1!)
DPLL_B_MD..................: 0xffffffff
HTOTAL_B...................: 0xffffffff (65536 active, 65536 total)
HBLANK_B...................: 0xffffffff (65536 start, 65536 end)
HSYNC_B....................: 0xffffffff (65536 start, 65536 end)
VTOTAL_B...................: 0xffffffff (65536 active, 65536 total)
VBLANK_B...................: 0xffffffff (65536 start, 65536 end)
VSYNC_B....................: 0xffffffff (65536 start, 65536 end)
BCLRPAT_B..................: 0xffffffff
VSYNCSHIFT_B...............: 0xffffffff
VCLK_DIVISOR_VGA0..........: 0xffffffff
VCLK_DIVISOR_VGA1..........: 0xffffffff
VCLK_POST_DIV..............: 0xffffffff
VGACNTRL...................: 0xffffffff (disabled)
TV_CTL.....................: 0xffffffff
TV_DAC.....................: 0xffffffff
TV_CSC_Y...................: 0xffffffff
TV_CSC_Y2..................: 0xffffffff
TV_CSC_U...................: 0xffffffff
TV_CSC_U2..................: 0xffffffff
TV_CSC_V...................: 0xffffffff
TV_CSC_V2..................: 0xffffffff
TV_CLR_KNOBS...............: 0xffffffff
TV_CLR_LEVEL...............: 0xffffffff
TV_H_CTL_1.................: 0xffffffff
TV_H_CTL_2.................: 0xffffffff
TV_H_CTL_3.................: 0xffffffff
TV_V_CTL_1.................: 0xffffffff
TV_V_CTL_2.................: 0xffffffff
TV_V_CTL_3.................: 0xffffffff
TV_V_CTL_4.................: 0xffffffff
TV_V_CTL_5.................: 0xffffffff
TV_V_CTL_6.................: 0xffffffff
TV_V_CTL_7.................: 0xffffffff
TV_SC_CTL_1................: 0xffffffff
TV_SC_CTL_2................: 0xffffffff
TV_SC_CTL_3................: 0xffffffff
TV_WIN_POS.................: 0xffffffff
TV_WIN_SIZE................: 0xffffffff
TV_FILTER_CTL_1............: 0xffffffff
TV_FILTER_CTL_2............: 0xffffffff
TV_FILTER_CTL_3............: 0xffffffff
TV_CC_CONTROL..............: 0xffffffff
TV_CC_DATA.................: 0xffffffff
TV_H_LUMA_0................: 0xffffffff
TV_H_LUMA_59...............: 0xffffffff
TV_H_CHROMA_0..............: 0xffffffff
TV_H_CHROMA_59.............: 0xffffffff
FBC_CFB_BASE...............: 0xffffffff
FBC_LL_BASE................: 0xffffffff
FBC_CONTROL................: 0xffffffff
FBC_COMMAND................: 0xffffffff
FBC_STATUS.................: 0xffffffff
FBC_CONTROL2...............: 0xffffffff
FBC_FENCE_OFF..............: 0xffffffff
FBC_MOD_NUM................: 0xffffffff
MI_MODE....................: 0xffffffff
MI_ARB_STATE...............: 0xffffffff
MI_RDRET_STATE.............: 0xffffffff
ECOSKPD....................: 0xffffffff
DP_B.......................: 0xffffffff
DPB_AUX_CH_CTL.............: 0xffffffff
DPB_AUX_CH_DATA1...........: 0xffffffff
DPB_AUX_CH_DATA2...........: 0xffffffff
DPB_AUX_CH_DATA3...........: 0xffffffff
DPB_AUX_CH_DATA4...........: 0xffffffff
DPB_AUX_CH_DATA5...........: 0xffffffff
DP_C.......................: 0xffffffff
DPC_AUX_CH_CTL.............: 0xffffffff
DPC_AUX_CH_DATA1...........: 0xffffffff
DPC_AUX_CH_DATA2...........: 0xffffffff
DPC_AUX_CH_DATA3...........: 0xffffffff
DPC_AUX_CH_DATA4...........: 0xffffffff
DPC_AUX_CH_DATA5...........: 0xffffffff
DP_D.......................: 0xffffffff
DPD_AUX_CH_CTL.............: 0xffffffff
DPD_AUX_CH_DATA1...........: 0xffffffff
DPD_AUX_CH_DATA2...........: 0xffffffff
DPD_AUX_CH_DATA3...........: 0xffffffff
DPD_AUX_CH_DATA4...........: 0xffffffff
DPD_AUX_CH_DATA5...........: 0xffffffff
AUD_CONFIG.................: 0xffffffff
AUD_HDMIW_STATUS...........: 0xffffffff
AUD_CONV_CHCNT.............: 0xffffffff
VIDEO_DIP_CTL..............: 0xffffffff
AUD_PINW_CNTR..............: 0xffffffff
AUD_CNTL_ST................: 0xffffffff
AUD_PIN_CAP................: 0xffffffff
AUD_PINW_CAP...............: 0xffffffff
AUD_PINW_UNSOLRESP.........: 0xffffffff
AUD_OUT_DIG_CNVT...........: 0xffffffff
AUD_OUT_CWCAP..............: 0xffffffff
AUD_GRP_CAP................: 0xffffffff
FENCE  0...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  1...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  2...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  3...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  4...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  5...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  6...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  7...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  8...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  9...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  10..................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  11..................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  12..................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  13..................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  14..................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  15..................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE START 0..............: 0xffffffff ()
FENCE END 0................: 0xffffffff ()
FENCE START 1..............: 0xffffffff ()
FENCE END 1................: 0xffffffff ()
FENCE START 2..............: 0xffffffff ()
FENCE END 2................: 0xffffffff ()
FENCE START 3..............: 0xffffffff ()
FENCE END 3................: 0xffffffff ()
FENCE START 4..............: 0xffffffff ()
FENCE END 4................: 0xffffffff ()
FENCE START 5..............: 0xffffffff ()
FENCE END 5................: 0xffffffff ()
FENCE START 6..............: 0xffffffff ()
FENCE END 6................: 0xffffffff ()
FENCE START 7..............: 0xffffffff ()
FENCE END 7................: 0xffffffff ()
FENCE START 8..............: 0xffffffff ()
FENCE END 8................: 0xffffffff ()
FENCE START 9..............: 0xffffffff ()
FENCE END 9................: 0xffffffff ()
FENCE START 10.............: 0xffffffff ()
FENCE END 10...............: 0xffffffff ()
FENCE START 11.............: 0xffffffff ()
FENCE END 11...............: 0xffffffff ()
FENCE START 12.............: 0xffffffff ()
FENCE END 12...............: 0xffffffff ()
FENCE START 13.............: 0xffffffff ()
FENCE END 13...............: 0xffffffff ()
FENCE START 14.............: 0xffffffff ()
FENCE END 14...............: 0xffffffff ()
FENCE START 15.............: 0xffffffff ()
FENCE END 15...............: 0xffffffff ()
INST_PM....................: 0xffffffff
p2 out of range
p1 out of range
fp select out of range
pipe A dot 600000 n 63 m1 63 m2 63 p1 1 p2 1
p1 out of range
fp select out of range
pipe B dot 85714 n 63 m1 63 m2 63 p1 1 p2 7

CPU Ratio Info:
------------------------------------
CPU Low Frequency Mode.............: 400 MHz
CPU Maximum non-Turbo Frequency....: 2000 MHz
CPU Maximum Turbo Frequency........: 4000 MHz

IGPU Info:
------------------------------------
IGPU Current Frequency.............:    0 MHz
IGPU Minimum Frequency.............:  300 MHz
IGPU Maximum Non-Turbo Frequency...:  300 MHz
IGPU Maximum Turbo Frequency.......: 1150 MHz
IGPU Maximum limit.................: No Limit

CPU P-States [ (13) 22 30 ] iGPU P-States [ ]
CPU C3-Cores [ 0 2 5 7 ]
CPU C3-Cores [ 0 2 4 5 6 7 ]
CPU C3-Cores [ 0 1 2 4 5 6 7 ]
CPU P-States [ (13) 22 25 30 ] iGPU P-States [ ]
CPU C3-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ (13) 21 22 25 30 ] iGPU P-States [ ]
CPU P-States [ (13) 14 21 22 25 30 ] iGPU P-States [ ]
CPU P-States [ 13 14 (18) 21 22 25 30 ] iGPU P-States [ ]
CPU P-States [ (13) 14 17 18 21 22 25 30 ] iGPU P-States [ ]
CPU P-States [ 13 14 16 17 (18) 21 22 25 30 ] iGPU P-States [ ]
CPU P-States [ 13 14 15 16 17 (18) 21 22 25 30 ] iGPU P-States [ ]
CPU P-States [ (13) 14 15 16 17 18 21 22 24 25 30 ] iGPU P-States [ ]
CPU P-States [ 13 14 15 16 17 18 19 21 22 (23) 24 25 30 ] iGPU P-States [ ]
CPU P-States [ 13 14 15 16 17 (18) 19 21 22 23 24 25 30 ] iGPU P-States [ (18) ]
CPU P-States [ 13 14 15 16 17 18 19 21 22 23 24 25 29 30 (33) ] iGPU P-States [ 18 ]
CPU P-States [ (13) 14 15 16 17 18 19 21 22 23 24 25 28 29 30 33 ] iGPU P-States [ 18 ]
CPU P-States [ 13 14 15 16 17 18 19 21 22 (23) 24 25 27 28 29 30 33 ] iGPU P-States [ 18 ]
CPU P-States [ (13) 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 30 33 ] iGPU P-States [ 18 ]
CPU P-States [ (13) 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 33 ] iGPU P-States [ 18 ]
CPU P-States [ (11) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 33 ] iGPU P-States [ 18 ]
CPU P-States [ 11 (13) 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 33 ] iGPU P-States [ 18 ]
CPU P-States [ 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 (31) 32 33 ] iGPU P-States [ 18 ]
CPU P-States [ 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (37) ] iGPU P-States [ (18) ]
CPU P-States [ 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 35 37 (40) ] iGPU P-States [ 18 ]
CPU P-States [ 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 37 (40) ] iGPU P-States [ 18 ]
CPU P-States [ 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 37 39 (40) ] iGPU P-States [ 18 ]
CPU P-States [ 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 37 38 39 (40) ] iGPU P-States [ 18 ]
CPU P-States [ 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (33) 34 35 36 37 38 39 40 ] iGPU P-States [ 18 ]
CPU P-States [ (8) 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ] iGPU P-States [ 18 ]
CPU P-States [ (4) 8 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ] iGPU P-States [ 18 ]
CPU P-States [ 4 8 9 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 (37) 38 39 40 ] iGPU P-States [ 18 ]
CPU P-States [ (4) 8 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ] iGPU P-States [ 18 ]
CPU P-States [ (4) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ] iGPU P-States [ 18 ]
CPU P-States [ (4) 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ] iGPU P-States [ 18 ]
CPU P-States [ (4) 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ] iGPU P-States [ 18 ]
CPU P-States [ 4 5 6 7 8 9 10 11 12 (13) 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ] iGPU P-States [ 18 ]
 

Attachments

  • jacknick_report.12.15.17.zip
    2.3 MB · Views: 78
jacknick said:
Hi Rehabman,

Ran geekbench and here are the results. does my PM look ok?

Code: 
AppleIntelInfo.kext v1.4 Copyright © 2012-2015 Pike R. Alpha. All rights reserved

Settings:
------------------------------------
logMSRs............................: 1
logIGPU............................: 1
logIntelRegs.......................: 1
logCStates.........................: 1
logIPGStyle........................: 1
InitialTSC.........................: 0x108eab0554e
MWAIT C-States.....................: 286531872

Model Specific Regiters
------------------------------------
MSR_CORE_THREAD_COUNT......(0x35)  : 0x40008
MSR_PLATFORM_INFO..........(0xCE)  : 0x4043DF1011400
MSR_PMG_CST_CONFIG_CONTROL.(0xE2)  : 0x1E008008
MSR_PMG_IO_CAPTURE_BASE....(0xE4)  : 0x51814
IA32_MPERF.................(0xE7)  : 0x193642706A
IA32_APERF.................(0xE8)  : 0x1B3C227A55
MSR_FLEX_RATIO.............(0x194) : 0x0
MSR_IA32_PERF_STATUS.......(0x198) : 0x1EC100001E00
MSR_IA32_PERF_CONTROL......(0x199) : 0xA00
IA32_CLOCK_MODULATION......(0x19A) : 0x0
IA32_THERM_STATUS..........(0x19C) : 0x883D0808
IA32_MISC_ENABLES..........(0x1A0) : 0x850089
MSR_MISC_PWR_MGMT..........(0x1AA) : 0x401CC1
MSR_TURBO_RATIO_LIMIT......(0x1AD) : 0x25252828
IA32_ENERGY_PERF_BIAS......(0x1B0) : 0x5
MSR_POWER_CTL..............(0x1FC) : 0x24005F
MSR_RAPL_POWER_UNIT........(0x606) : 0xA0E03
MSR_PKG_POWER_LIMIT........(0x610) : 0x42816000DD8160
MSR_PKG_ENERGY_STATUS......(0x611) : 0x18C1855
MSR_PKG_POWER_INFO.........(0x614) : 0x78
MSR_PP0_CURRENT_CONFIG.....(0x601) : 0x238
MSR_PP0_POWER_LIMIT........(0x638) : 0x0
MSR_PP0_ENERGY_STATUS......(0x639) : 0x88EABE
MSR_PP0_POLICY.............(0x63a) : 0x0
MSR_PKGC6_IRTL.............(0x60b) : 0x8876
MSR_PKG_C2_RESIDENCY.......(0x60d) : 0x2292B2AEA8
MSR_PKG_C3_RESIDENCY.......(0x3f8) : 0xBB1F9CFA9C
MSR_PKG_C6_RESIDENCY.......(0x3f9) : 0x0
IA32_TSC_DEADLINE..........(0x6E0) : 0x108EF3E6920
PCH device.................: 0x9D4E8086

Intel Register Data
------------------------------------
CPU_VGACNTRL...............: 0xFFFFFFFF
IS_ELSE(devid)
DCC........................: 0xffffffff ()
CHDECMISC..................: 0xffffffff (XOR bank, ch2 enh enabled, ch1 enh enabled, ch0 enh enabled, flex enabled, ep present)
C0DRB0.....................: 0xffffffff (0xffff)
C0DRB1.....................: 0xffffffff (0xffff)
C0DRB2.....................: 0xffffffff (0xffff)
C0DRB3.....................: 0xffffffff (0xffff)
C1DRB0.....................: 0xffffffff (0xffff)
C1DRB1.....................: 0xffffffff (0xffff)
C1DRB2.....................: 0xffffffff (0xffff)
C1DRB3.....................: 0xffffffff (0xffff)
C0DRA01....................: 0xffffffff (0xffff)
C0DRA23....................: 0xffffffff (0xffff)
C1DRA01....................: 0xffffffff (0xffff)
C1DRA23....................: 0xffffffff (0xffff)
PGETBL_CTL.................: 0xffffffff
VCLK_DIVISOR_VGA0..........: 0xffffffff (n = 63, m1 = 63, m2 = 63)
VCLK_DIVISOR_VGA1..........: 0xffffffff (n = 63, m1 = 63, m2 = 63)
VCLK_POST_DIV..............: 0xffffffff (vga0 p1 = 2, p2 = 4, vga1 p1 = 2, p2 = 4)
DPLL_TEST..................: 0xffffffff (, DPLLA N bypassed, DPLLA M bypassed, DPLLB N bypassed, DPLLB M bypassed)
CACHE_MODE_0...............: 0xffffffff
D_STATE....................: 0xffffffff
DSPCLK_GATE_D..............: 0xffffffff (clock gates disabled: DPUNIT_B VSUNIT VRHUNIT VRDUNIT AUDUNIT DPUNIT_A DPCUNIT TVRUNIT TVCUNIT TVFUNIT TVEUNIT DVSUNIT DSSUNIT DDBUNIT DPRUNIT DPFUNIT DPBMUNIT DPLSUNIT DPLUNIT DPOUNIT DPBUNIT DCUNIT DPUNIT VRUNIT RENCLK_GATE_D1.............: 0xffffffff
RENCLK_GATE_D2.............: 0xffffffff
SDVOB......................: 0xffffffff (enabled, pipe B, stall enabled, detected, gang mode)
SDVOC......................: 0xffffffff (enabled, pipe B, stall enabled, detected, gang mode)
SDVOUDI....................: 0xffffffff
DSPARB.....................: 0xffffffff
FW_BLC.....................: 0xffffffff
FW_BLC2....................: 0xffffffff
FW_BLC_SELF................: 0xffffffff
DSPFW1.....................: 0xffffffff
DSPFW2.....................: 0xffffffff
DSPFW3.....................: 0xffffffff
ADPA.......................: 0xffffffff (enabled, pipe B, +hsync, +vsync)
LVDS.......................: 0xffffffff (enabled, pipe B, 24 bit, 2 channels)
DVOA.......................: 0xffffffff (enabled, pipe B, unknown stall, +hsync, +vsync)
DVOB.......................: 0xffffffff (enabled, pipe B, unknown stall, +hsync, +vsync)
DVOC.......................: 0xffffffff (enabled, pipe B, unknown stall, +hsync, +vsync)
DVOA_SRCDIM................: 0xffffffff
DVOB_SRCDIM................: 0xffffffff
DVOC_SRCDIM................: 0xffffffff
BLC_PWM_CTL................: 0xffffffff
BLC_PWM_CTL2...............: 0xffffffff
PP_CONTROL.................: 0xffffffff (power target: on)
PP_STATUS..................: 0xffffffff (on, ready, sequencing unknown)
PP_ON_DELAYS...............: 0xffffffff
PP_OFF_DELAYS..............: 0xffffffff
PP_DIVISOR.................: 0xffffffff
PFIT_CONTROL...............: 0xffffffff
PFIT_PGM_RATIOS............: 0xffffffff
PORT_HOTPLUG_EN............: 0xffffffff
PORT_HOTPLUG_STAT..........: 0xffffffff
DSPACNTR...................: 0xffffffff (enabled, pipe B)
DSPASTRIDE.................: 0xffffffff (-1 bytes)
DSPAPOS....................: 0xffffffff (65535, 65535)
DSPASIZE...................: 0xffffffff (65536, 65536)
DSPABASE...................: 0xffffffff
DSPASURF...................: 0xffffffff
DSPATILEOFF................: 0xffffffff
PIPEACONF..................: 0xffffffff (enabled, double-wide)
PIPEASRC...................: 0xffffffff (65536, 65536)
PIPEASTAT..................: 0xffffffff (status: FIFO_UNDERRUN CRC_ERROR_ENABLE CRC_DONE_ENABLE GMBUS_EVENT_ENABLE VSYNC_INT_ENABLE DLINE_COMPARE_ENABLE DPST_EVENT_ENABLE LBLC_EVENT_ENABLE OFIELD_INT_ENABLE EFIELD_INT_ENABLE SVBLANK_INT_ENABLE VBLANK_INT_PIPEA_GMCH_DATA_M..........: 0xffffffff
PIPEA_GMCH_DATA_N..........: 0xffffffff
PIPEA_DP_LINK_M............: 0xffffffff
PIPEA_DP_LINK_N............: 0xffffffff
CURSOR_A_BASE..............: 0xffffffff
CURSOR_A_CONTROL...........: 0xffffffff
CURSOR_A_POSITION..........: 0xffffffff
FPA0.......................: 0xffffffff (n = 63, m1 = 63, m2 = 63)
FPA1.......................: 0xffffffff (n = 63, m1 = 63, m2 = 63)
DPLL_A.....................: 0xffffffff (enabled, dvo, unknown clock, unknown mode, p1 = 1, p2 = 0, using FPx1!)
DPLL_A_MD..................: 0xffffffff
HTOTAL_A...................: 0xffffffff (65536 active, 65536 total)
HBLANK_A...................: 0xffffffff (65536 start, 65536 end)
HSYNC_A....................: 0xffffffff (65536 start, 65536 end)
VTOTAL_A...................: 0xffffffff (65536 active, 65536 total)
VBLANK_A...................: 0xffffffff (65536 start, 65536 end)
VSYNC_A....................: 0xffffffff (65536 start, 65536 end)
BCLRPAT_A..................: 0xffffffff
VSYNCSHIFT_A...............: 0xffffffff
DSPBCNTR...................: 0xffffffff (enabled, pipe B)
DSPBSTRIDE.................: 0xffffffff (-1 bytes)
DSPBPOS....................: 0xffffffff (65535, 65535)
DSPBSIZE...................: 0xffffffff (65536, 65536)
DSPBBASE...................: 0xffffffff
DSPBSURF...................: 0xffffffff
DSPBTILEOFF................: 0xffffffff
PIPEBCONF..................: 0xffffffff (enabled, double-wide)
PIPEBSRC...................: 0xffffffff (65536, 65536)
PIPEBSTAT..................: 0xffffffff (status: FIFO_UNDERRUN CRC_ERROR_ENABLE CRC_DONE_ENABLE GMBUS_EVENT_ENABLE VSYNC_INT_ENABLE DLINE_COMPARE_ENABLE DPST_EVENT_ENABLE LBLC_EVENT_ENABLE OFIELD_INT_ENABLE EFIELD_INT_ENABLE SVBLANK_INT_ENABLE VBLANK_INT_PIPEB_GMCH_DATA_M..........: 0xffffffff
PIPEB_GMCH_DATA_N..........: 0xffffffff
PIPEB_DP_LINK_M............: 0xffffffff
PIPEB_DP_LINK_N............: 0xffffffff
CURSOR_B_BASE..............: 0xffffffff
CURSOR_B_CONTROL...........: 0xffffffff
CURSOR_B_POSITION..........: 0xffffffff
FPB0.......................: 0xffffffff (n = 63, m1 = 63, m2 = 63)
FPB1.......................: 0xffffffff (n = 63, m1 = 63, m2 = 63)
DPLL_B.....................: 0xffffffff (enabled, dvo, spread spectrum clock, unknown mode, p1 = 1, p2 = 0, using FPx1!)
DPLL_B_MD..................: 0xffffffff
HTOTAL_B...................: 0xffffffff (65536 active, 65536 total)
HBLANK_B...................: 0xffffffff (65536 start, 65536 end)
HSYNC_B....................: 0xffffffff (65536 start, 65536 end)
VTOTAL_B...................: 0xffffffff (65536 active, 65536 total)
VBLANK_B...................: 0xffffffff (65536 start, 65536 end)
VSYNC_B....................: 0xffffffff (65536 start, 65536 end)
BCLRPAT_B..................: 0xffffffff
VSYNCSHIFT_B...............: 0xffffffff
VCLK_DIVISOR_VGA0..........: 0xffffffff
VCLK_DIVISOR_VGA1..........: 0xffffffff
VCLK_POST_DIV..............: 0xffffffff
VGACNTRL...................: 0xffffffff (disabled)
TV_CTL.....................: 0xffffffff
TV_DAC.....................: 0xffffffff
TV_CSC_Y...................: 0xffffffff
TV_CSC_Y2..................: 0xffffffff
TV_CSC_U...................: 0xffffffff
TV_CSC_U2..................: 0xffffffff
TV_CSC_V...................: 0xffffffff
TV_CSC_V2..................: 0xffffffff
TV_CLR_KNOBS...............: 0xffffffff
TV_CLR_LEVEL...............: 0xffffffff
TV_H_CTL_1.................: 0xffffffff
TV_H_CTL_2.................: 0xffffffff
TV_H_CTL_3.................: 0xffffffff
TV_V_CTL_1.................: 0xffffffff
TV_V_CTL_2.................: 0xffffffff
TV_V_CTL_3.................: 0xffffffff
TV_V_CTL_4.................: 0xffffffff
TV_V_CTL_5.................: 0xffffffff
TV_V_CTL_6.................: 0xffffffff
TV_V_CTL_7.................: 0xffffffff
TV_SC_CTL_1................: 0xffffffff
TV_SC_CTL_2................: 0xffffffff
TV_SC_CTL_3................: 0xffffffff
TV_WIN_POS.................: 0xffffffff
TV_WIN_SIZE................: 0xffffffff
TV_FILTER_CTL_1............: 0xffffffff
TV_FILTER_CTL_2............: 0xffffffff
TV_FILTER_CTL_3............: 0xffffffff
TV_CC_CONTROL..............: 0xffffffff
TV_CC_DATA.................: 0xffffffff
TV_H_LUMA_0................: 0xffffffff
TV_H_LUMA_59...............: 0xffffffff
TV_H_CHROMA_0..............: 0xffffffff
TV_H_CHROMA_59.............: 0xffffffff
FBC_CFB_BASE...............: 0xffffffff
FBC_LL_BASE................: 0xffffffff
FBC_CONTROL................: 0xffffffff
FBC_COMMAND................: 0xffffffff
FBC_STATUS.................: 0xffffffff
FBC_CONTROL2...............: 0xffffffff
FBC_FENCE_OFF..............: 0xffffffff
FBC_MOD_NUM................: 0xffffffff
MI_MODE....................: 0xffffffff
MI_ARB_STATE...............: 0xffffffff
MI_RDRET_STATE.............: 0xffffffff
ECOSKPD....................: 0xffffffff
DP_B.......................: 0xffffffff
DPB_AUX_CH_CTL.............: 0xffffffff
DPB_AUX_CH_DATA1...........: 0xffffffff
DPB_AUX_CH_DATA2...........: 0xffffffff
DPB_AUX_CH_DATA3...........: 0xffffffff
DPB_AUX_CH_DATA4...........: 0xffffffff
DPB_AUX_CH_DATA5...........: 0xffffffff
DP_C.......................: 0xffffffff
DPC_AUX_CH_CTL.............: 0xffffffff
DPC_AUX_CH_DATA1...........: 0xffffffff
DPC_AUX_CH_DATA2...........: 0xffffffff
DPC_AUX_CH_DATA3...........: 0xffffffff
DPC_AUX_CH_DATA4...........: 0xffffffff
DPC_AUX_CH_DATA5...........: 0xffffffff
DP_D.......................: 0xffffffff
DPD_AUX_CH_CTL.............: 0xffffffff
DPD_AUX_CH_DATA1...........: 0xffffffff
DPD_AUX_CH_DATA2...........: 0xffffffff
DPD_AUX_CH_DATA3...........: 0xffffffff
DPD_AUX_CH_DATA4...........: 0xffffffff
DPD_AUX_CH_DATA5...........: 0xffffffff
AUD_CONFIG.................: 0xffffffff
AUD_HDMIW_STATUS...........: 0xffffffff
AUD_CONV_CHCNT.............: 0xffffffff
VIDEO_DIP_CTL..............: 0xffffffff
AUD_PINW_CNTR..............: 0xffffffff
AUD_CNTL_ST................: 0xffffffff
AUD_PIN_CAP................: 0xffffffff
AUD_PINW_CAP...............: 0xffffffff
AUD_PINW_UNSOLRESP.........: 0xffffffff
AUD_OUT_DIG_CNVT...........: 0xffffffff
AUD_OUT_CWCAP..............: 0xffffffff
AUD_GRP_CAP................: 0xffffffff
FENCE  0...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  1...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  2...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  3...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  4...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  5...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  6...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  7...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  8...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  9...................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  10..................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  11..................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  12..................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  13..................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  14..................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE  15..................: 0xffffffff (enabled, Y tiled, 16384 pitch, 0x0ff00000 - 0x17f00000 (131072kb))
FENCE START 0..............: 0xffffffff ()
FENCE END 0................: 0xffffffff ()
FENCE START 1..............: 0xffffffff ()
FENCE END 1................: 0xffffffff ()
FENCE START 2..............: 0xffffffff ()
FENCE END 2................: 0xffffffff ()
FENCE START 3..............: 0xffffffff ()
FENCE END 3................: 0xffffffff ()
FENCE START 4..............: 0xffffffff ()
FENCE END 4................: 0xffffffff ()
FENCE START 5..............: 0xffffffff ()
FENCE END 5................: 0xffffffff ()
FENCE START 6..............: 0xffffffff ()
FENCE END 6................: 0xffffffff ()
FENCE START 7..............: 0xffffffff ()
FENCE END 7................: 0xffffffff ()
FENCE START 8..............: 0xffffffff ()
FENCE END 8................: 0xffffffff ()
FENCE START 9..............: 0xffffffff ()
FENCE END 9................: 0xffffffff ()
FENCE START 10.............: 0xffffffff ()
FENCE END 10...............: 0xffffffff ()
FENCE START 11.............: 0xffffffff ()
FENCE END 11...............: 0xffffffff ()
FENCE START 12.............: 0xffffffff ()
FENCE END 12...............: 0xffffffff ()
FENCE START 13.............: 0xffffffff ()
FENCE END 13...............: 0xffffffff ()
FENCE START 14.............: 0xffffffff ()
FENCE END 14...............: 0xffffffff ()
FENCE START 15.............: 0xffffffff ()
FENCE END 15...............: 0xffffffff ()
INST_PM....................: 0xffffffff
p2 out of range
p1 out of range
fp select out of range
pipe A dot 600000 n 63 m1 63 m2 63 p1 1 p2 1
p1 out of range
fp select out of range
pipe B dot 85714 n 63 m1 63 m2 63 p1 1 p2 7

CPU Ratio Info:
------------------------------------
CPU Low Frequency Mode.............: 400 MHz
CPU Maximum non-Turbo Frequency....: 2000 MHz
CPU Maximum Turbo Frequency........: 4000 MHz

IGPU Info:
------------------------------------
IGPU Current Frequency.............:    0 MHz
IGPU Minimum Frequency.............:  300 MHz
IGPU Maximum Non-Turbo Frequency...:  300 MHz
IGPU Maximum Turbo Frequency.......: 1150 MHz
IGPU Maximum limit.................: No Limit

CPU P-States [ (13) 22 30 ] iGPU P-States [ ]
CPU C3-Cores [ 0 2 5 7 ]
CPU C3-Cores [ 0 2 4 5 6 7 ]
CPU C3-Cores [ 0 1 2 4 5 6 7 ]
CPU P-States [ (13) 22 25 30 ] iGPU P-States [ ]
CPU C3-Cores [ 0 1 2 3 4 5 6 7 ]
CPU P-States [ (13) 21 22 25 30 ] iGPU P-States [ ]
CPU P-States [ (13) 14 21 22 25 30 ] iGPU P-States [ ]
CPU P-States [ 13 14 (18) 21 22 25 30 ] iGPU P-States [ ]
CPU P-States [ (13) 14 17 18 21 22 25 30 ] iGPU P-States [ ]
CPU P-States [ 13 14 16 17 (18) 21 22 25 30 ] iGPU P-States [ ]
CPU P-States [ 13 14 15 16 17 (18) 21 22 25 30 ] iGPU P-States [ ]
CPU P-States [ (13) 14 15 16 17 18 21 22 24 25 30 ] iGPU P-States [ ]
CPU P-States [ 13 14 15 16 17 18 19 21 22 (23) 24 25 30 ] iGPU P-States [ ]
CPU P-States [ 13 14 15 16 17 (18) 19 21 22 23 24 25 30 ] iGPU P-States [ (18) ]
CPU P-States [ 13 14 15 16 17 18 19 21 22 23 24 25 29 30 (33) ] iGPU P-States [ 18 ]
CPU P-States [ (13) 14 15 16 17 18 19 21 22 23 24 25 28 29 30 33 ] iGPU P-States [ 18 ]
CPU P-States [ 13 14 15 16 17 18 19 21 22 (23) 24 25 27 28 29 30 33 ] iGPU P-States [ 18 ]
CPU P-States [ (13) 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 30 33 ] iGPU P-States [ 18 ]
CPU P-States [ (13) 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 33 ] iGPU P-States [ 18 ]
CPU P-States [ (11) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 33 ] iGPU P-States [ 18 ]
CPU P-States [ 11 (13) 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 33 ] iGPU P-States [ 18 ]
CPU P-States [ 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 (31) 32 33 ] iGPU P-States [ 18 ]
CPU P-States [ 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (37) ] iGPU P-States [ (18) ]
CPU P-States [ 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 35 37 (40) ] iGPU P-States [ 18 ]
CPU P-States [ 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 37 (40) ] iGPU P-States [ 18 ]
CPU P-States [ 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 37 39 (40) ] iGPU P-States [ 18 ]
CPU P-States [ 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 37 38 39 (40) ] iGPU P-States [ 18 ]
CPU P-States [ 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (33) 34 35 36 37 38 39 40 ] iGPU P-States [ 18 ]
CPU P-States [ (8) 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ] iGPU P-States [ 18 ]
CPU P-States [ (4) 8 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ] iGPU P-States [ 18 ]
CPU P-States [ 4 8 9 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 (37) 38 39 40 ] iGPU P-States [ 18 ]
CPU P-States [ (4) 8 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ] iGPU P-States [ 18 ]
CPU P-States [ (4) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ] iGPU P-States [ 18 ]
CPU P-States [ (4) 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ] iGPU P-States [ 18 ]
CPU P-States [ (4) 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ] iGPU P-States [ 18 ]
CPU P-States [ 4 5 6 7 8 9 10 11 12 (13) 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ] iGPU P-States [ 18 ]
Click to expand...

CPU PM looks like it is working.
For XCPM supported CPUs, it is quite easy with config.plist/ACPI/SSDT/Generate/PluginType=true.
 
So I switched to MacBook9,1 from MacBook11,1 on my Skylake Core m3 laptop and since then the CPU frequency at idle as reported by Intel Power Gadget has gone up from ~600Mhz to a fixed 1.2Ghz. I haven't changed anything in Clover's (4330) config.plist except for the SMBIOS block and adding a kernel patch to stop it from crashing (caused by HWP according to RehabMan)

- X86PlatformPlugin still loads
- GeneratePluginType set to True in config.plist, I can see the property in ioreg
- According to AppleIntelInfo (2.9), HWP is enabled
- CPU P-States go from 4 to 20 and GPU P-States from 2 to 16 when I run GeekBench

So it looks like it should work yet it... doesn't? Not sure what's going on here. AppleIntelInfo.dat below:

Code: 
AppleIntelInfo.kext v2.9 Copyright © 2012-2017 Pike R. Alpha. All rights reserved.

Settings:
------------------------------------------
logMSRs..................................: 1
logIGPU..................................: 1
logCStates...............................: 1
logIPGStyle..............................: 1
InitialTSC...............................: 0x7f858c2104 (36 MHz)
MWAIT C-States...........................: 286531872

Processor Brandstring....................: Intel(R) Core(TM) m3-6Y30 CPU @ 0.90GHz

Processor Signature..................... : 0x406E3
------------------------------------------
- Family............................... : 6
- Stepping............................. : 3
- Model................................ : 0x4E (78)

Model Specific Registers (MSRs)
------------------------------------------

MSR_IA32_PLATFORM_ID.............(0x17)  : 0x1C000000000000
------------------------------------------
- Processor Flags...................... : 7

MSR_CORE_THREAD_COUNT............(0x35)  : 0x20004
------------------------------------------
- Core Count........................... : 2
- Thread Count......................... : 4

MSR_PLATFORM_INFO................(0xCE)  : 0x4043DF1010F00
------------------------------------------
- Maximum Non-Turbo Ratio.............. : 0xF (1500 MHz)
- Ratio Limit for Turbo Mode........... : 1 (programmable)
- TDP Limit for Turbo Mode............. : 1 (programmable)
- Low Power Mode Support............... : 1 (LPM supported)
- Number of ConfigTDP Levels........... : 2 (additional TDP level(s) available)
- Maximum Efficiency Ratio............. : 4
- Minimum Operating Ratio.............. : 4

MSR_PMG_CST_CONFIG_CONTROL.......(0xE2)  : 0x1E008006
------------------------------------------
- I/O MWAIT Redirection Enable......... : 0 (not enabled)
- CFG Lock............................. : 1 (MSR locked until next reset)
- C3 State Auto Demotion............... : 1 (enabled)
- C1 State Auto Demotion............... : 1 (enabled)
- C3 State Undemotion.................. : 1 (enabled)
- C1 State Undemotion.................. : 1 (enabled)
- Package C-State Auto Demotion........ : 0 (disabled/unsupported)
- Package C-State Undemotion........... : 0 (disabled/unsupported)

MSR_PMG_IO_CAPTURE_BASE..........(0xE4)  : 0x51814
------------------------------------------
- LVL_2 Base Address................... : 0x1814
- C-state Range........................ : 5 (C-States not included, I/O MWAIT redirection not enabled)

IA32_MPERF.......................(0xE7)  : 0x285E230BFD
IA32_APERF.......................(0xE8)  : 0x2689A7B741

MSR_FLEX_RATIO...................(0x194) : 0x0
------------------------------------------

MSR_IA32_PERF_STATUS.............(0x198) : 0x1DC200001600
------------------------------------------
- Current Performance State Value...... : 0x1600 (2200 MHz)

MSR_IA32_PERF_CONTROL............(0x199) : 0xA00
------------------------------------------
- Target performance State Value....... : 0xA00 (1000 MHz)
- Intel Dynamic Acceleration........... : 0 (IDA engaged)

IA32_CLOCK_MODULATION............(0x19A) : 0x0

IA32_THERM_INTERRUPT.............(0x19B) : 0x10
------------------------------------------
- High-Temperature Interrupt Enable.... : 0 (disabled)
- Low-Temperature Interrupt Enable..... : 0 (disabled)
- PROCHOT# Interrupt Enable............ : 0 (disabled)
- FORCEPR# Interrupt Enable............ : 0 (disabled)
- Critical Temperature Interrupt Enable : 1 (enabled)
- Threshold #1 Value................... : 0
- Threshold #1 Interrupt Enable........ : 0 (disabled)
- Threshold #2 Value................... : 0
- Threshold #2 Interrupt Enable........ : 0 (disabled)
- Power Limit Notification Enable...... : 0 (disabled)

IA32_THERM_STATUS................(0x19C) : 0x883D0800
------------------------------------------
- Thermal Status....................... : 0
- Thermal Log.......................... : 0
- PROCHOT # or FORCEPR# event.......... : 0
- PROCHOT # or FORCEPR# log............ : 0
- Critical Temperature Status.......... : 0
- Critical Temperature log............. : 0
- Thermal Threshold #1 Status.......... : 0
- Thermal Threshold #1 log............. : 0
- Thermal Threshold #2 Status.......... : 0
- Thermal Threshold #2 log............. : 0
- Power Limitation Status.............. : 0
- Power Limitation log................. : 1
- Current Limit Status................. : 0
- Current Limit log.................... : 0
- Cross Domain Limit Status............ : 0
- Cross Domain Limit log............... : 0
- Digital Readout...................... : 61
- Resolution in Degrees Celsius........ : 1
- Reading Valid........................ : 1 (valid)

MSR_THERM2_CTL...................(0x19D) : 0x0

IA32_MISC_ENABLES................(0x1A0) : 0x850089
------------------------------------------
- Fast-Strings......................... : 1 (enabled)
- FOPCODE compatibility mode Enable.... : 0
- Automatic Thermal Control Circuit.... : 1 (enabled)
- Split-lock Disable................... : 0
- Performance Monitoring............... : 1 (available)
- Bus Lock On Cache Line Splits Disable : 0
- Hardware prefetch Disable............ : 0
- Processor Event Based Sampling....... : 0 (PEBS supported)
- GV1/2 legacy Enable.................. : 0
- Enhanced Intel SpeedStep Technology.. : 1 (enabled)
- MONITOR FSM.......................... : 1 (MONITOR/MWAIT supported)
- Adjacent sector prefetch Disable..... : 0
- CFG Lock............................. : 0 (MSR not locked)
- xTPR Message Disable................. : 1 (disabled)

MSR_TEMPERATURE_TARGET...........(0x1A2) : 0xA640000
------------------------------------------
- Turbo Attenuation Units.............. : 0
- Temperature Target................... : 100
- TCC Activation Offset................ : 10

MSR_MISC_PWR_MGMT................(0x1AA) : 0x401CC1
------------------------------------------
- EIST Hardware Coordination........... : 1 (hardware coordination disabled)
- Energy/Performance Bias support...... : 1
- Energy/Performance Bias.............. : 0 (disabled/MSR not visible to software)
- Thermal Interrupt Coordination Enable : 1 (thermal interrupt routed to all cores)
- SpeedShift Technology Enable......... : 1 (enabled)
- SpeedShift Interrupt Coordination.... : 1 (enabled)
- SpeedShift Energy Efficient Perf..... : 1 (enabled)
- SpeedShift Technology Setup for HWP.. : Yes (setup for HWP)

MSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x14141416
------------------------------------------
- Maximum Ratio Limit for C01.......... : 16 (2200 MHz)
- Maximum Ratio Limit for C02.......... : 14 (2000 MHz)

IA32_ENERGY_PERF_BIAS............(0x1B0) : 0x5
------------------------------------------
- Power Policy Preference...............: 5 (balanced performance and energy saving)

MSR_POWER_CTL....................(0x1FC) : 0x24005F
------------------------------------------
- Bi-Directional Processor Hot..........: 1 (enabled)
- C1E Enable............................: 1 (enabled)

MSR_RAPL_POWER_UNIT..............(0x606) : 0xA0E03
------------------------------------------
- Power Units.......................... : 3 (1/8 Watt)
- Energy Status Units.................. : 14 (61 micro-Joules)
- Time Units .......................... : 10 (976.6 micro-Seconds)

MSR_PKG_POWER_LIMIT..............(0x610) : 0x42807800DD8038
------------------------------------------
- Package Power Limit #1............... : 7 Watt
- Enable Power Limit #1................ : 1 (enabled)
- Package Clamping Limitation #1....... : 1 (allow going below OS-requested P/T state during Time Window for Power Limit #1)
- Time Window for Power Limit #1....... : 110 (163840 milli-Seconds)
- Package Power Limit #2............... : 15 Watt
- Enable Power Limit #2................ : 1 (enabled)
- Package Clamping Limitation #2....... : 0 (disabled)
- Time Window for Power Limit #2....... : 33 (10 milli-Seconds)
- Lock................................. : 0 (MSR not locked)

MSR_PKG_ENERGY_STATUS............(0x611) : 0xC39489
------------------------------------------
- Total Energy Consumed................ : 782 Joules (Watt = Joules / seconds)

MSR_PP0_POWER_LIMIT..............(0x638) : 0x0

MSR_PP0_ENERGY_STATUS............(0x639) : 0x5ACE04
------------------------------------------
- Total Energy Consumed................ : 363 Joules (Watt = Joules / seconds)

MSR_PP0_POWER_LIMIT..............(0x638) : 0x0

MSR_PP0_ENERGY_STATUS............(0x639) : 0x5ACE1D
------------------------------------------
- Total Energy Consumed................ : 363 Joules (Watt = Joules / seconds)

MSR_PP1_POWER_LIMIT..............(0x640) : 0x0

MSR_PP1_ENERGY_STATUS............(0x641) : 0x1ED91
------------------------------------------
- Total Energy Consumed................ : 7 Joules (Watt = Joules / seconds)

MSR_PP1_POLICY...................(0x642) : 0x18
------------------------------------------
- Priority Level....................... : 24

MSR_CONFIG_TDP_NOMINAL...........(0x648) : 0x9
MSR_CONFIG_TDP_LEVEL1............(0x649) : 0x6001E
MSR_CONFIG_TDP_LEVEL2............(0x64a) : 0xF0038
MSR_CONFIG_TDP_CONTROL...........(0x64b) : 0x0
MSR_TURBO_ACTIVATION_RATIO.......(0x64c) : 0x0
MSR_PKGC3_IRTL...................(0x60a) : 0x884E
MSR_PKGC6_IRTL...................(0x60b) : 0x8876
MSR_PKGC7_IRTL...................(0x60c) : 0x8894
MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x45D0A75F3D
MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0x0
MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x45D0A75F3D
MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0x0
MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0x0
MSR_PKG_C7_RESIDENCY.............(0x3fa) : 0x0
MSR_PKG_C8_RESIDENCY.............(0x630) : 0x0
MSR_PKG_C9_RESIDENCY.............(0x631) : 0x0
MSR_PKG_C10_RESIDENCY............(0x632) : 0x0
MSR_PKG_C8_LATENCY...............(0x633) : 0x0
MSR_PKG_C9_LATENCY...............(0x634) : 0x0
MSR_PKG_C10_LATENCY..............(0x635) : 0x0

MSR_PLATFORM_ENERGY_COUNTER......(0x64D) : 0xAB6CAC
------------------------------------------

MSR_PPERF........................(0x64E) : 0x228F91319A
------------------------------------------
- Hardware workload scalability........ : 148437545370

MSR_CORE_PERF_LIMIT_REASONS......(0x64F) : 0x14001000
------------------------------------------
- PROCHOT Status....................... : 0
- Thermal Status....................... : 0
- Residency State Regulation Status.... : 0
- Running Average Thermal Limit Status. : 0
- VR Therm Alert Status................ : 0
- VR Therm Design Current Status....... : 0
- Other Status......................... : 0
- Package/Platform-Level #1 Power Limit : 0
- Package/Platform-Level #2 Power Limit : 0
- Max Turbo Limit Status............... : 1 (frequency reduced below OS request due to multi-core turbo limits)
- Turbo Transition Attenuation Status.. : 0
- PROCHOT Log.......................... : 0
- Thermal Log.......................... : 0
- Residency State Regulation Log....... : 0
- Running Average Thermal Limit Log.... : 0
- VR Therm Alert Log................... : 0
- VR Thermal Design Current Log........ : 0
- Other Status Log..................... : 0
- Package/Platform-Level #1 Power Limit : 1 (status bit has asserted)
- Package/Platform-Level #2 Power Limit : 0
- Max Turbo Limit Log.................. : 1 (status bit has asserted)
- Turbo Transition Attenuation Log..... : 0
HDC Supported

IA32_PKG_HDC_CTL.................(0xDB0) : 0x0

IA32_PM_CTL1.....................(0xDB1) : 0x1
------------------------------------------
HDC Allow Block..................(0xDB1) : 1 (HDC blocked)

IA32_THREAD_STALL................(0xDB2) : 0x0

MSR_PKG_HDC_CONFIG...............(0x652) : 0x2
------------------------------------------
Pkg Cx Monitor ..................(0x652) : 2 (count package C3 and deeper)
MSR_CORE_HDC_RESIDENCY...........(0x653) : 0x0

MSR_PKG_HDC_SHALLOW_RESIDENCY....(0x655) : 0x0

MSR_PKG_HDC_DEEP_RESIDENCY.......(0x656) : 0x0

IA32_TSC_DEADLINE................(0x6E0) : 0x7F896F2310
MSR_PPERF........................(0x63E) : 0x1 (14)

IA32_PM_ENABLE...................(0x770) : 0x1 (HWP Supported and Enabled)

IA32_HWP_CAPABILITIES............(0x771) : 0x1060916
-----------------------------------------
- Highest Performance.................. : 22
- Guaranteed Performance............... : 9
- Most Efficient Performance........... : 6
- Lowest Performance................... : 1

IA32_HWP_INTERRUPT...............(0x773) : 0x1
------------------------------------------
- Guaranteed Performance Change........ : 1 (Interrupt generated on change of)
- Excursion Minimum.................... : 0 (Interrupt generation disabled)

IA32_HWP_REQUEST................(0x774) : 0x80161604
-----------------------------------------
- Minimum Performance................. : 4
- Maximum Performance................. : 22
- Desired Performance................. : 22
- Energy Efficient Performance........ : 128
- Activity Window..................... : 0, 0
- Package Control..................... : 0

IA32_HWP_STATUS..................(0x777) : 0x0
-----------------------------------------
- Guaranteed Performance Change....... : 0 (has not occured)
- Excursion To Minimum................ : 0 (has not occured)

CPU Ratio Info:
------------------------------------------
Base Clock Frequency (BLCK)............. : 100 MHz
Maximum Efficiency Ratio/Frequency.......:  4 ( 400 MHz)
Maximum non-Turbo Ratio/Frequency........: 15 (1500 MHz)
Maximum Turbo Ratio/Frequency............: 22 (2200 MHz)

IGPU Info:
------------------------------------------
IGPU Current Frequency...................:    0 MHz
IGPU Minimum Frequency...................:  300 MHz
IGPU Maximum Non-Turbo Frequency.........:  300 MHz
IGPU Maximum Turbo Frequency.............:  850 MHz
IGPU Maximum limit.......................: No Limit

P-State ratio * 100 = Frequency in MHz
------------------------------------------
CPU P-States [ (12) 14 20 ] iGPU P-States [ ]
CPU C3-Cores [ 1 2 3 ]
CPU C7-Cores [ 0 1 2 3 ]
CPU P-States [ (12) 14 20 ] iGPU P-States [ ]
CPU P-States [ (12) 14 17 20 ] iGPU P-States [ ]
CPU C3-Cores [ 0 1 2 3 ]
CPU P-States [ (12) 14 17 20 ] iGPU P-States [ (6) ]
CPU P-States [ (12) 14 17 18 20 ] iGPU P-States [ 6 ]
CPU P-States [ 12 (13) 14 17 18 20 ] iGPU P-States [ 6 ]
CPU P-States [ 12 13 14 (15) 17 18 20 ] iGPU P-States [ (6) ]
CPU P-States [ (8) 12 13 14 15 17 18 20 ] iGPU P-States [ 6 ]
CPU P-States [ 8 (9) 12 13 14 15 17 18 20 ] iGPU P-States [ 6 ]
CPU P-States [ 8 9 12 13 14 15 17 18 (20) ] iGPU P-States [ 6 ]
CPU P-States [ 8 9 12 13 14 15 17 18 (20) ] iGPU P-States [ 6 ]
CPU P-States [ 4 8 9 12 13 14 15 17 18 (20) ] iGPU P-States [ 6 ]
CPU P-States [ 4 8 9 12 13 14 15 17 18 (20) ] iGPU P-States [ 6 ]
CPU P-States [ 4 8 9 12 13 14 15 17 18 (19) 20 ] iGPU P-States [ 6 ]
CPU P-States [ 4 8 9 12 13 14 15 (16) 17 18 19 20 ] iGPU P-States [ 6 ]
CPU P-States [ 4 8 9 (11) 12 13 14 15 16 17 18 19 20 ] iGPU P-States [ 6 ]
CPU P-States [ 4 8 9 11 (12) 13 14 15 16 17 18 19 20 ] iGPU P-States [ (2) 6 ]
CPU P-States [ 4 8 9 11 (12) 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 (11) ]
CPU P-States [ 4 8 9 11 (12) 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 11 (16) ]
CPU P-States [ 4 8 9 11 (12) 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 11 (13) 16 ]
CPU P-States [ 4 8 9 11 (12) 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 (9) 11 13 16 ]
CPU P-States [ 4 8 9 11 (12) 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 (8) 9 11 13 16 ]
CPU P-States [ 4 8 9 11 (12) 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 8 9 11 (12) 13 16 ]
CPU P-States [ 4 8 9 11 (12) 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 8 9 11 12 13 (15) 16 ]
CPU P-States [ 4 (7) 8 9 11 12 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 8 9 11 12 13 15 (16) ]
CPU P-States [ 4 (5) 7 8 9 11 12 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 8 9 11 12 13 15 16 ]
CPU P-States [ 4 5 7 8 9 (10) 11 12 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 8 9 11 12 13 15 16 ]
CPU P-States [ 4 5 (6) 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 8 9 11 12 13 15 16 ]
CPU P-States [ 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 (20) ] iGPU P-States [ 2 6 (7) 8 9 11 12 13 15 16 ]
CPU P-States [ 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (22) ] iGPU P-States [ 2 6 7 8 9 (10) 11 12 13 15 16 ]
 

Attachments

  • problem-reporting.zip
    3.8 MB · Views: 87
foo1234 said:
So I switched to MacBook9,1 from MacBook11,1 on my Skylake Core m3 laptop and since then the CPU frequency at idle as reported by Intel Power Gadget has gone up from ~600Mhz to a fixed 1.2Ghz. I haven't changed anything in Clover's (4330) config.plist except for the SMBIOS block and adding a kernel patch to stop it from crashing (caused by HWP according to RehabMan)

- X86PlatformPlugin still loads
- GeneratePluginType set to True in config.plist, I can see the property in ioreg
- According to AppleIntelInfo (2.9), HWP is enabled
- CPU P-States go from 4 to 20 and GPU P-States from 2 to 16 when I run GeekBench

So it looks like it should work yet it... doesn't? Not sure what's going on here. AppleIntelInfo.dat below:

Code: 
AppleIntelInfo.kext v2.9 Copyright © 2012-2017 Pike R. Alpha. All rights reserved.

Settings:
------------------------------------------
logMSRs..................................: 1
logIGPU..................................: 1
logCStates...............................: 1
logIPGStyle..............................: 1
InitialTSC...............................: 0x7f858c2104 (36 MHz)
MWAIT C-States...........................: 286531872

Processor Brandstring....................: Intel(R) Core(TM) m3-6Y30 CPU @ 0.90GHz

Processor Signature..................... : 0x406E3
------------------------------------------
- Family............................... : 6
- Stepping............................. : 3
- Model................................ : 0x4E (78)

Model Specific Registers (MSRs)
------------------------------------------

MSR_IA32_PLATFORM_ID.............(0x17)  : 0x1C000000000000
------------------------------------------
- Processor Flags...................... : 7

MSR_CORE_THREAD_COUNT............(0x35)  : 0x20004
------------------------------------------
- Core Count........................... : 2
- Thread Count......................... : 4

MSR_PLATFORM_INFO................(0xCE)  : 0x4043DF1010F00
------------------------------------------
- Maximum Non-Turbo Ratio.............. : 0xF (1500 MHz)
- Ratio Limit for Turbo Mode........... : 1 (programmable)
- TDP Limit for Turbo Mode............. : 1 (programmable)
- Low Power Mode Support............... : 1 (LPM supported)
- Number of ConfigTDP Levels........... : 2 (additional TDP level(s) available)
- Maximum Efficiency Ratio............. : 4
- Minimum Operating Ratio.............. : 4

MSR_PMG_CST_CONFIG_CONTROL.......(0xE2)  : 0x1E008006
------------------------------------------
- I/O MWAIT Redirection Enable......... : 0 (not enabled)
- CFG Lock............................. : 1 (MSR locked until next reset)
- C3 State Auto Demotion............... : 1 (enabled)
- C1 State Auto Demotion............... : 1 (enabled)
- C3 State Undemotion.................. : 1 (enabled)
- C1 State Undemotion.................. : 1 (enabled)
- Package C-State Auto Demotion........ : 0 (disabled/unsupported)
- Package C-State Undemotion........... : 0 (disabled/unsupported)

MSR_PMG_IO_CAPTURE_BASE..........(0xE4)  : 0x51814
------------------------------------------
- LVL_2 Base Address................... : 0x1814
- C-state Range........................ : 5 (C-States not included, I/O MWAIT redirection not enabled)

IA32_MPERF.......................(0xE7)  : 0x285E230BFD
IA32_APERF.......................(0xE8)  : 0x2689A7B741

MSR_FLEX_RATIO...................(0x194) : 0x0
------------------------------------------

MSR_IA32_PERF_STATUS.............(0x198) : 0x1DC200001600
------------------------------------------
- Current Performance State Value...... : 0x1600 (2200 MHz)

MSR_IA32_PERF_CONTROL............(0x199) : 0xA00
------------------------------------------
- Target performance State Value....... : 0xA00 (1000 MHz)
- Intel Dynamic Acceleration........... : 0 (IDA engaged)

IA32_CLOCK_MODULATION............(0x19A) : 0x0

IA32_THERM_INTERRUPT.............(0x19B) : 0x10
------------------------------------------
- High-Temperature Interrupt Enable.... : 0 (disabled)
- Low-Temperature Interrupt Enable..... : 0 (disabled)
- PROCHOT# Interrupt Enable............ : 0 (disabled)
- FORCEPR# Interrupt Enable............ : 0 (disabled)
- Critical Temperature Interrupt Enable : 1 (enabled)
- Threshold #1 Value................... : 0
- Threshold #1 Interrupt Enable........ : 0 (disabled)
- Threshold #2 Value................... : 0
- Threshold #2 Interrupt Enable........ : 0 (disabled)
- Power Limit Notification Enable...... : 0 (disabled)

IA32_THERM_STATUS................(0x19C) : 0x883D0800
------------------------------------------
- Thermal Status....................... : 0
- Thermal Log.......................... : 0
- PROCHOT # or FORCEPR# event.......... : 0
- PROCHOT # or FORCEPR# log............ : 0
- Critical Temperature Status.......... : 0
- Critical Temperature log............. : 0
- Thermal Threshold #1 Status.......... : 0
- Thermal Threshold #1 log............. : 0
- Thermal Threshold #2 Status.......... : 0
- Thermal Threshold #2 log............. : 0
- Power Limitation Status.............. : 0
- Power Limitation log................. : 1
- Current Limit Status................. : 0
- Current Limit log.................... : 0
- Cross Domain Limit Status............ : 0
- Cross Domain Limit log............... : 0
- Digital Readout...................... : 61
- Resolution in Degrees Celsius........ : 1
- Reading Valid........................ : 1 (valid)

MSR_THERM2_CTL...................(0x19D) : 0x0

IA32_MISC_ENABLES................(0x1A0) : 0x850089
------------------------------------------
- Fast-Strings......................... : 1 (enabled)
- FOPCODE compatibility mode Enable.... : 0
- Automatic Thermal Control Circuit.... : 1 (enabled)
- Split-lock Disable................... : 0
- Performance Monitoring............... : 1 (available)
- Bus Lock On Cache Line Splits Disable : 0
- Hardware prefetch Disable............ : 0
- Processor Event Based Sampling....... : 0 (PEBS supported)
- GV1/2 legacy Enable.................. : 0
- Enhanced Intel SpeedStep Technology.. : 1 (enabled)
- MONITOR FSM.......................... : 1 (MONITOR/MWAIT supported)
- Adjacent sector prefetch Disable..... : 0
- CFG Lock............................. : 0 (MSR not locked)
- xTPR Message Disable................. : 1 (disabled)

MSR_TEMPERATURE_TARGET...........(0x1A2) : 0xA640000
------------------------------------------
- Turbo Attenuation Units.............. : 0
- Temperature Target................... : 100
- TCC Activation Offset................ : 10

MSR_MISC_PWR_MGMT................(0x1AA) : 0x401CC1
------------------------------------------
- EIST Hardware Coordination........... : 1 (hardware coordination disabled)
- Energy/Performance Bias support...... : 1
- Energy/Performance Bias.............. : 0 (disabled/MSR not visible to software)
- Thermal Interrupt Coordination Enable : 1 (thermal interrupt routed to all cores)
- SpeedShift Technology Enable......... : 1 (enabled)
- SpeedShift Interrupt Coordination.... : 1 (enabled)
- SpeedShift Energy Efficient Perf..... : 1 (enabled)
- SpeedShift Technology Setup for HWP.. : Yes (setup for HWP)

MSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x14141416
------------------------------------------
- Maximum Ratio Limit for C01.......... : 16 (2200 MHz)
- Maximum Ratio Limit for C02.......... : 14 (2000 MHz)

IA32_ENERGY_PERF_BIAS............(0x1B0) : 0x5
------------------------------------------
- Power Policy Preference...............: 5 (balanced performance and energy saving)

MSR_POWER_CTL....................(0x1FC) : 0x24005F
------------------------------------------
- Bi-Directional Processor Hot..........: 1 (enabled)
- C1E Enable............................: 1 (enabled)

MSR_RAPL_POWER_UNIT..............(0x606) : 0xA0E03
------------------------------------------
- Power Units.......................... : 3 (1/8 Watt)
- Energy Status Units.................. : 14 (61 micro-Joules)
- Time Units .......................... : 10 (976.6 micro-Seconds)

MSR_PKG_POWER_LIMIT..............(0x610) : 0x42807800DD8038
------------------------------------------
- Package Power Limit #1............... : 7 Watt
- Enable Power Limit #1................ : 1 (enabled)
- Package Clamping Limitation #1....... : 1 (allow going below OS-requested P/T state during Time Window for Power Limit #1)
- Time Window for Power Limit #1....... : 110 (163840 milli-Seconds)
- Package Power Limit #2............... : 15 Watt
- Enable Power Limit #2................ : 1 (enabled)
- Package Clamping Limitation #2....... : 0 (disabled)
- Time Window for Power Limit #2....... : 33 (10 milli-Seconds)
- Lock................................. : 0 (MSR not locked)

MSR_PKG_ENERGY_STATUS............(0x611) : 0xC39489
------------------------------------------
- Total Energy Consumed................ : 782 Joules (Watt = Joules / seconds)

MSR_PP0_POWER_LIMIT..............(0x638) : 0x0

MSR_PP0_ENERGY_STATUS............(0x639) : 0x5ACE04
------------------------------------------
- Total Energy Consumed................ : 363 Joules (Watt = Joules / seconds)

MSR_PP0_POWER_LIMIT..............(0x638) : 0x0

MSR_PP0_ENERGY_STATUS............(0x639) : 0x5ACE1D
------------------------------------------
- Total Energy Consumed................ : 363 Joules (Watt = Joules / seconds)

MSR_PP1_POWER_LIMIT..............(0x640) : 0x0

MSR_PP1_ENERGY_STATUS............(0x641) : 0x1ED91
------------------------------------------
- Total Energy Consumed................ : 7 Joules (Watt = Joules / seconds)

MSR_PP1_POLICY...................(0x642) : 0x18
------------------------------------------
- Priority Level....................... : 24

MSR_CONFIG_TDP_NOMINAL...........(0x648) : 0x9
MSR_CONFIG_TDP_LEVEL1............(0x649) : 0x6001E
MSR_CONFIG_TDP_LEVEL2............(0x64a) : 0xF0038
MSR_CONFIG_TDP_CONTROL...........(0x64b) : 0x0
MSR_TURBO_ACTIVATION_RATIO.......(0x64c) : 0x0
MSR_PKGC3_IRTL...................(0x60a) : 0x884E
MSR_PKGC6_IRTL...................(0x60b) : 0x8876
MSR_PKGC7_IRTL...................(0x60c) : 0x8894
MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x45D0A75F3D
MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0x0
MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x45D0A75F3D
MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0x0
MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0x0
MSR_PKG_C7_RESIDENCY.............(0x3fa) : 0x0
MSR_PKG_C8_RESIDENCY.............(0x630) : 0x0
MSR_PKG_C9_RESIDENCY.............(0x631) : 0x0
MSR_PKG_C10_RESIDENCY............(0x632) : 0x0
MSR_PKG_C8_LATENCY...............(0x633) : 0x0
MSR_PKG_C9_LATENCY...............(0x634) : 0x0
MSR_PKG_C10_LATENCY..............(0x635) : 0x0

MSR_PLATFORM_ENERGY_COUNTER......(0x64D) : 0xAB6CAC
------------------------------------------

MSR_PPERF........................(0x64E) : 0x228F91319A
------------------------------------------
- Hardware workload scalability........ : 148437545370

MSR_CORE_PERF_LIMIT_REASONS......(0x64F) : 0x14001000
------------------------------------------
- PROCHOT Status....................... : 0
- Thermal Status....................... : 0
- Residency State Regulation Status.... : 0
- Running Average Thermal Limit Status. : 0
- VR Therm Alert Status................ : 0
- VR Therm Design Current Status....... : 0
- Other Status......................... : 0
- Package/Platform-Level #1 Power Limit : 0
- Package/Platform-Level #2 Power Limit : 0
- Max Turbo Limit Status............... : 1 (frequency reduced below OS request due to multi-core turbo limits)
- Turbo Transition Attenuation Status.. : 0
- PROCHOT Log.......................... : 0
- Thermal Log.......................... : 0
- Residency State Regulation Log....... : 0
- Running Average Thermal Limit Log.... : 0
- VR Therm Alert Log................... : 0
- VR Thermal Design Current Log........ : 0
- Other Status Log..................... : 0
- Package/Platform-Level #1 Power Limit : 1 (status bit has asserted)
- Package/Platform-Level #2 Power Limit : 0
- Max Turbo Limit Log.................. : 1 (status bit has asserted)
- Turbo Transition Attenuation Log..... : 0
HDC Supported

IA32_PKG_HDC_CTL.................(0xDB0) : 0x0

IA32_PM_CTL1.....................(0xDB1) : 0x1
------------------------------------------
HDC Allow Block..................(0xDB1) : 1 (HDC blocked)

IA32_THREAD_STALL................(0xDB2) : 0x0

MSR_PKG_HDC_CONFIG...............(0x652) : 0x2
------------------------------------------
Pkg Cx Monitor ..................(0x652) : 2 (count package C3 and deeper)
MSR_CORE_HDC_RESIDENCY...........(0x653) : 0x0

MSR_PKG_HDC_SHALLOW_RESIDENCY....(0x655) : 0x0

MSR_PKG_HDC_DEEP_RESIDENCY.......(0x656) : 0x0

IA32_TSC_DEADLINE................(0x6E0) : 0x7F896F2310
MSR_PPERF........................(0x63E) : 0x1 (14)

IA32_PM_ENABLE...................(0x770) : 0x1 (HWP Supported and Enabled)

IA32_HWP_CAPABILITIES............(0x771) : 0x1060916
-----------------------------------------
- Highest Performance.................. : 22
- Guaranteed Performance............... : 9
- Most Efficient Performance........... : 6
- Lowest Performance................... : 1

IA32_HWP_INTERRUPT...............(0x773) : 0x1
------------------------------------------
- Guaranteed Performance Change........ : 1 (Interrupt generated on change of)
- Excursion Minimum.................... : 0 (Interrupt generation disabled)

IA32_HWP_REQUEST................(0x774) : 0x80161604
-----------------------------------------
- Minimum Performance................. : 4
- Maximum Performance................. : 22
- Desired Performance................. : 22
- Energy Efficient Performance........ : 128
- Activity Window..................... : 0, 0
- Package Control..................... : 0

IA32_HWP_STATUS..................(0x777) : 0x0
-----------------------------------------
- Guaranteed Performance Change....... : 0 (has not occured)
- Excursion To Minimum................ : 0 (has not occured)

CPU Ratio Info:
------------------------------------------
Base Clock Frequency (BLCK)............. : 100 MHz
Maximum Efficiency Ratio/Frequency.......:  4 ( 400 MHz)
Maximum non-Turbo Ratio/Frequency........: 15 (1500 MHz)
Maximum Turbo Ratio/Frequency............: 22 (2200 MHz)

IGPU Info:
------------------------------------------
IGPU Current Frequency...................:    0 MHz
IGPU Minimum Frequency...................:  300 MHz
IGPU Maximum Non-Turbo Frequency.........:  300 MHz
IGPU Maximum Turbo Frequency.............:  850 MHz
IGPU Maximum limit.......................: No Limit

P-State ratio * 100 = Frequency in MHz
------------------------------------------
CPU P-States [ (12) 14 20 ] iGPU P-States [ ]
CPU C3-Cores [ 1 2 3 ]
CPU C7-Cores [ 0 1 2 3 ]
CPU P-States [ (12) 14 20 ] iGPU P-States [ ]
CPU P-States [ (12) 14 17 20 ] iGPU P-States [ ]
CPU C3-Cores [ 0 1 2 3 ]
CPU P-States [ (12) 14 17 20 ] iGPU P-States [ (6) ]
CPU P-States [ (12) 14 17 18 20 ] iGPU P-States [ 6 ]
CPU P-States [ 12 (13) 14 17 18 20 ] iGPU P-States [ 6 ]
CPU P-States [ 12 13 14 (15) 17 18 20 ] iGPU P-States [ (6) ]
CPU P-States [ (8) 12 13 14 15 17 18 20 ] iGPU P-States [ 6 ]
CPU P-States [ 8 (9) 12 13 14 15 17 18 20 ] iGPU P-States [ 6 ]
CPU P-States [ 8 9 12 13 14 15 17 18 (20) ] iGPU P-States [ 6 ]
CPU P-States [ 8 9 12 13 14 15 17 18 (20) ] iGPU P-States [ 6 ]
CPU P-States [ 4 8 9 12 13 14 15 17 18 (20) ] iGPU P-States [ 6 ]
CPU P-States [ 4 8 9 12 13 14 15 17 18 (20) ] iGPU P-States [ 6 ]
CPU P-States [ 4 8 9 12 13 14 15 17 18 (19) 20 ] iGPU P-States [ 6 ]
CPU P-States [ 4 8 9 12 13 14 15 (16) 17 18 19 20 ] iGPU P-States [ 6 ]
CPU P-States [ 4 8 9 (11) 12 13 14 15 16 17 18 19 20 ] iGPU P-States [ 6 ]
CPU P-States [ 4 8 9 11 (12) 13 14 15 16 17 18 19 20 ] iGPU P-States [ (2) 6 ]
CPU P-States [ 4 8 9 11 (12) 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 (11) ]
CPU P-States [ 4 8 9 11 (12) 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 11 (16) ]
CPU P-States [ 4 8 9 11 (12) 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 11 (13) 16 ]
CPU P-States [ 4 8 9 11 (12) 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 (9) 11 13 16 ]
CPU P-States [ 4 8 9 11 (12) 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 (8) 9 11 13 16 ]
CPU P-States [ 4 8 9 11 (12) 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 8 9 11 (12) 13 16 ]
CPU P-States [ 4 8 9 11 (12) 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 8 9 11 12 13 (15) 16 ]
CPU P-States [ 4 (7) 8 9 11 12 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 8 9 11 12 13 15 (16) ]
CPU P-States [ 4 (5) 7 8 9 11 12 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 8 9 11 12 13 15 16 ]
CPU P-States [ 4 5 7 8 9 (10) 11 12 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 8 9 11 12 13 15 16 ]
CPU P-States [ 4 5 (6) 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ] iGPU P-States [ 2 6 8 9 11 12 13 15 16 ]
CPU P-States [ 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 (20) ] iGPU P-States [ 2 6 (7) 8 9 11 12 13 15 16 ]
CPU P-States [ 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (22) ] iGPU P-States [ 2 6 7 8 9 (10) 11 12 13 15 16 ]
Click to expand...

Your AppleIntelInfo output show PM working.
Why do you think it is not working?
 
RehabMan said:
Your AppleIntelInfo output show PM working.
Why do you think it is not working?
Click to expand...
Frequency at idle is 1.2Ghz whereas before it was 600Mhz. Surely battery will deplete faster? Actually, I'll boot with MacBook11,1 again and compare power consumption figures.

Or maybe that's just how it's supposed to be. I don't have a real MacBook to compare.
 
foo1234 said:
Frequency at idle is 1.2Ghz whereas before it was 600Mhz.
Click to expand...

Your AppleIntelInfo data shows lower states reached:
Code: 
CPU P-States [ 4 5 6 7 8 9 10 11 ... ]

Ability to idle at lower states depends on CPU demand.
Check in Activity Monitor to find processes that may be using CPU.
 
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