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BrcmPatchRAM - Upload firmware into Broadcom Bluetooth USB devices

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RehabMan said:
SSDT-Disable_EHCI.dsl assumes LPC is named LPCB. Yours is named LPC. You must make appropriate changes for your actual ACPI naming.
Click to expand...
I changed it to LPC in SSDT-Disable_EHCI.dsl, compiled, and added it to my EFI folder. However, I still see EH01 in IOReg.

I'm also assuming that I will lose my touchscreen when this is working, since that always seems to be on the USB 2.0 bus.
 
CoBrA2168 said:
I changed it to LPC in SSDT-Disable_EHCI.dsl, compiled, and added it to my EFI folder. However, I still see EH01 in IOReg.
Click to expand...

Read post #715.

I'm also assuming that I will lose my touchscreen when this is working, since that always seems to be on the USB 2.0 bus.
Click to expand...

Yes.
 
RehabMan said:
Your DSDT.aml has no EH02, yet you did not remove the EH02 related code from SSDT-Disable_EHCI.
Click to expand...
Should the LPC Scope look like this?
Code: 
Field(FDM1, DWordAcc, NoLock, Preserve)
        {
            ,13,    // skip first 13 bits
            ,1,
            FDE1,1, // should be bit 15 (0-based) (FD EHCI#1)
        }
 
CoBrA2168 said:
Should the LPC Scope look like this?
Code: 
Field(FDM1, DWordAcc, NoLock, Preserve)
        {
            ,13,    // skip first 13 bits
            ,1,
            FDE1,1, // should be bit 15 (0-based) (FD EHCI#1)
        }
Click to expand...

No (that is very wrong). Leave it as-is.

Note: In the future, I will separate Disable_EHCI.dsl into separate Disable_EH01, Disable_EH02 files.
 
Last edited:
RehabMan said:
No (that is very wrong). Leave it as-is.
Click to expand...
Okay, EHCI is finally disabled (confirmed from IOReg). I will test to see if this helps.

Are there any other side affects by not using FakePCIID_XHCIMux and putting all of my devices on XHCI? Also, even before I was able to disable EHCI, I noticed that all devices other than my touchscreen (USB-A ports, BT, and webcam) were routed to XHCI anyway. So could I just not include XHCIMux and keep using EHCI?

EDIT: I read more of the USB guide to understand exactly what that is doing. If my understanding is correct, the reason for routing USB2 devices to EHCI is to get around the 15-port limit on 10.11. My machine only has 7 USB devices: 3 USB-A ports, BT, webcam, touchscreen, and SD-card reader (disabled in my custom port injector). If my understanding is correct, then my machine should function just fine if I completely disable EHCI.
 
Last edited:
CoBrA2168 said:
Okay, EHCI is finally disabled (confirmed from IOReg). I will test to see if this helps.

Are there any other side affects by not using FakePCIID_XHCIMux and putting all of my devices on XHCI? Also, even before I was able to disable EHCI, I noticed that all devices other than my touchscreen (USB-A ports, BT, and webcam) were routed to XHCI anyway. So could I just not include XHCIMux and keep using EHCI?
Click to expand...

Both ways valid. I think your touchscreen is wired directly to EHCI instead of XHC. That's why it is not affected by the routing. Maybe. You can also use FakePCIID_XHCIMux to force things that BIOS might be routing from XHCI to EHCI by injecting RM,pr2-force=<ff3f0000>. If you look in some of my github projects, you will see where I do this. It is even done on-the-fly depending on whether EHCI is disabled in SSDT-XHC.dsl (in hotpatch repo). Understanding why ... that requires some knowledge of the PR2 routing registers on the XHCI chipset (refer to the chipset datasheet).

Note... untested diffs for separating disable EH01/EH02...
Code: 
diff --git a/Patches.xcodeproj/project.pbxproj b/Patches.xcodeproj/project.pbxproj
index 91817fd..84d77ef 100644
--- a/Patches.xcodeproj/project.pbxproj
+++ b/Patches.xcodeproj/project.pbxproj
@@ -18,6 +18,8 @@
        ED16FCE51C98D3F6002B97A6 /* SSDT-XWAK.dsl */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; name = "SSDT-XWAK.dsl"; path = "hotpatch/SSDT-XWAK.dsl"; sourceTree = "<group>"; };
        ED2500581CF681E2006A5FB7 /* config_HD5600.plist */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.plist.xml; path = config_HD5600.plist; sourceTree = "<group>"; };
        ED3636B91CA426EF004CE8B4 /* config_HD520_530_540.plist */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.plist.xml; path = config_HD520_530_540.plist; sourceTree = "<group>"; };
+        ED415C871DDE28C900AC633E /* SSDT-Disable_EH01.dsl */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; name = "SSDT-Disable_EH01.dsl"; path = "hotpatch/SSDT-Disable_EH01.dsl"; sourceTree = "<group>"; };
+        ED415C881DDE28CF00AC633E /* SSDT-Disable_EH02.dsl */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; name = "SSDT-Disable_EH02.dsl"; path = "hotpatch/SSDT-Disable_EH02.dsl"; sourceTree = "<group>"; };
        ED57679B1CF5D81300ABAEF8 /* config_HD550.plist */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.plist.xml; path = config_HD550.plist; sourceTree = "<group>"; };
        ED6DB3B41C873F5C00DB1B7A /* config_HD3000_1366x768_7series.plist */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.plist.xml; path = config_HD3000_1366x768_7series.plist; sourceTree = "<group>"; };
        ED6DB3B51C873F5C00DB1B7A /* config_HD3000_1366x768.plist */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.plist.xml; path = config_HD3000_1366x768.plist; sourceTree = "<group>"; };
@@ -105,6 +107,8 @@
                ED9956131C94BA0C00B3B13F /* SSDT-LANC_PRW.dsl */,
                ED99560F1C94BA0C00B3B13F /* SSDT-PTSWAK.dsl */,
                ED99560E1C94BA0C00B3B13F /* SSDT-Disable_EHCI.dsl */,
+                ED415C871DDE28C900AC633E /* SSDT-Disable_EH01.dsl */,
+                ED415C881DDE28CF00AC633E /* SSDT-Disable_EH02.dsl */,
                ED16FCE51C98D3F6002B97A6 /* SSDT-XWAK.dsl */,
                EDB68B771C99B72500147700 /* SSDT-XSEL.dsl */,
                EDD76F281C9B1E4A0023D100 /* SSDT-ESEL.dsl */,
diff --git a/hotpatch/SSDT-Disable_EH01.dsl b/hotpatch/SSDT-Disable_EH01.dsl
new file mode 100644
index 0000000..d0b9104
--- /dev/null
+++ b/hotpatch/SSDT-Disable_EH01.dsl
@@ -0,0 +1,49 @@
+// Disabling EHCI #1 (and EHCI #2)
+
+DefinitionBlock("", "SSDT", 2, "hack", "D-EH01", 0)
+{
+    External(_SB.PCI0, DeviceObj)
+    External(_SB.PCI0.EH01, DeviceObj)
+    External(_SB.PCI0.LPCB, DeviceObj)
+
+    // registers needed for disabling EHC#1
+    Scope(_SB.PCI0.EH01)
+    {
+        OperationRegion(RMP1, PCI_Config, 0x54, 2)
+        Field(RMP1, WordAcc, NoLock, Preserve)
+        {
+            PSTE, 2  // bits 2:0 are power state
+        }
+    }
+    Scope(_SB.PCI0.LPCB)
+    {
+        OperationRegion(RMP3, PCI_Config, 0xF0, 4)
+        Field(RMP3, DWordAcc, NoLock, Preserve)
+        {
+            RCB3, 32, // Root Complex Base Address
+        }
+        // address is in bits 31:14
+        OperationRegion(FDM3, SystemMemory, (RCB3 & Not((1<<14)-1)) + 0x3418, 4)
+        Field(FDM3, DWordAcc, NoLock, Preserve)
+        {
+            ,15,    // skip first 15 bits
+            FDE1,1, // should be bit 15 (0-based) (FD EHCI#1)
+        }
+    }
+    Scope(_SB.PCI0)
+    {
+        Device(RMD3)
+        {
+            Name(_HID, "RMD30000")
+            Method(_INI)
+            {
+                // disable EHCI#1
+                // put EHCI#1 in D3hot (sleep mode)
+                ^^EH01.PSTE = 3
+                // disable EHCI#1 PCI space
+                ^^LPCB.FDE1 = 1
+            }
+        }
+    }
+}
+//EOF
diff --git a/hotpatch/SSDT-Disable_EH02.dsl b/hotpatch/SSDT-Disable_EH02.dsl
new file mode 100644
index 0000000..4a04934
--- /dev/null
+++ b/hotpatch/SSDT-Disable_EH02.dsl
@@ -0,0 +1,49 @@
+// Disabling EHCI #1 (and EHCI #2)
+
+DefinitionBlock("", "SSDT", 2, "hack", "D-EH02", 0)
+{
+    External(_SB.PCI0, DeviceObj)
+    External(_SB.PCI0.EH02, DeviceObj)
+    External(_SB.PCI0.LPCB, DeviceObj)
+
+    // registers needed for disabling EHC#1
+    Scope(_SB.PCI0.EH02)
+    {
+        OperationRegion(RMP1, PCI_Config, 0x54, 2)
+        Field(RMP1, WordAcc, NoLock, Preserve)
+        {
+            PSTE, 2  // bits 2:0 are power state
+        }
+    }
+    Scope(_SB.PCI0.LPCB)
+    {
+        OperationRegion(RMP4, PCI_Config, 0xF0, 4)
+        Field(RMP4, DWordAcc, NoLock, Preserve)
+        {
+            RCB4, 32, // Root Complex Base Address
+        }
+        // address is in bits 31:14
+        OperationRegion(FDM4, SystemMemory, (RCB4 & Not((1<<14)-1)) + 0x3418, 4)
+        Field(FDM4, DWordAcc, NoLock, Preserve)
+        {
+            ,13,    // skip first 13 bits
+            FDE2,1, // should be bit 13 (0-based) (FD EHCI#2)
+        }
+    }
+    Scope(_SB.PCI0)
+    {
+        Device(RMD4)
+        {
+            Name(_HID, "RMD40000")
+            Method(_INI)
+            {
+                // disable EHCI#2
+                // put EHCI#2 in D3hot (sleep mode)
+                ^^EH02.PSTE = 3
+                // disable EHCI#2 PCI space
+                ^^LPCB.FDE2 = 1
+            }
+        }
+    }
+}
+//EOF
diff --git a/hotpatch/SSDT-XHC.dsl b/hotpatch/SSDT-XHC.dsl
index 693a7f2..2df2862 100644
--- a/hotpatch/SSDT-XHC.dsl
+++ b/hotpatch/SSDT-XHC.dsl
@@ -21,7 +21,7 @@ DefinitionBlock("", "SSDT", 2, "hack", "XHC", 0)
                 "AAPL,max-port-current-in-sleep", Buffer() { 0x34, 0x08, 0, 0 },
             }
             // force USB2 on XHC if EHCI is disabled
-            If (CondRefOf(\_SB.PCI0.RMD2))
+            If (CondRefOf(\_SB.PCI0.RMD2) || CondRefOf(\_SB.PCI0.RMD3) || CondRefOf(\_SB.PCI0.RMD4))
             {
                 CreateDWordField(DerefOf(Local0[1]), 0, PR2F)
                 PR2F = 0x3fff
 
RehabMan said:
Both ways valid. I think your touchscreen is wired directly to EHCI instead of XHC. That's why it is not affected by the routing. Maybe. You can also use FakePCIID_XHCIMux to force things that BIOS might be routing from XHCI to EHCI by injecting RM,pr2-force=<ff3f0000>. If you look in some of my github projects, you will see where I do this. It is even done on-the-fly depending on whether EHCI is disabled in SSDT-XHC.dsl (in hotpatch repo). Understanding why ... that requires some knowledge of the PR2 routing registers on the XHCI chipset (refer to the chipset datasheet).

Note... untested diffs for separating disable EH01/EH02...
Code: 
diff --git a/Patches.xcodeproj/project.pbxproj b/Patches.xcodeproj/project.pbxproj
index 91817fd..84d77ef 100644
--- a/Patches.xcodeproj/project.pbxproj
+++ b/Patches.xcodeproj/project.pbxproj
@@ -18,6 +18,8 @@
        ED16FCE51C98D3F6002B97A6 /* SSDT-XWAK.dsl */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; name = "SSDT-XWAK.dsl"; path = "hotpatch/SSDT-XWAK.dsl"; sourceTree = "<group>"; };
        ED2500581CF681E2006A5FB7 /* config_HD5600.plist */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.plist.xml; path = config_HD5600.plist; sourceTree = "<group>"; };
        ED3636B91CA426EF004CE8B4 /* config_HD520_530_540.plist */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.plist.xml; path = config_HD520_530_540.plist; sourceTree = "<group>"; };
+        ED415C871DDE28C900AC633E /* SSDT-Disable_EH01.dsl */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; name = "SSDT-Disable_EH01.dsl"; path = "hotpatch/SSDT-Disable_EH01.dsl"; sourceTree = "<group>"; };
+        ED415C881DDE28CF00AC633E /* SSDT-Disable_EH02.dsl */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text; name = "SSDT-Disable_EH02.dsl"; path = "hotpatch/SSDT-Disable_EH02.dsl"; sourceTree = "<group>"; };
        ED57679B1CF5D81300ABAEF8 /* config_HD550.plist */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.plist.xml; path = config_HD550.plist; sourceTree = "<group>"; };
        ED6DB3B41C873F5C00DB1B7A /* config_HD3000_1366x768_7series.plist */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.plist.xml; path = config_HD3000_1366x768_7series.plist; sourceTree = "<group>"; };
        ED6DB3B51C873F5C00DB1B7A /* config_HD3000_1366x768.plist */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = text.plist.xml; path = config_HD3000_1366x768.plist; sourceTree = "<group>"; };
@@ -105,6 +107,8 @@
                ED9956131C94BA0C00B3B13F /* SSDT-LANC_PRW.dsl */,
                ED99560F1C94BA0C00B3B13F /* SSDT-PTSWAK.dsl */,
                ED99560E1C94BA0C00B3B13F /* SSDT-Disable_EHCI.dsl */,
+                ED415C871DDE28C900AC633E /* SSDT-Disable_EH01.dsl */,
+                ED415C881DDE28CF00AC633E /* SSDT-Disable_EH02.dsl */,
                ED16FCE51C98D3F6002B97A6 /* SSDT-XWAK.dsl */,
                EDB68B771C99B72500147700 /* SSDT-XSEL.dsl */,
                EDD76F281C9B1E4A0023D100 /* SSDT-ESEL.dsl */,
diff --git a/hotpatch/SSDT-Disable_EH01.dsl b/hotpatch/SSDT-Disable_EH01.dsl
new file mode 100644
index 0000000..d0b9104
--- /dev/null
+++ b/hotpatch/SSDT-Disable_EH01.dsl
@@ -0,0 +1,49 @@
+// Disabling EHCI #1 (and EHCI #2)
+
+DefinitionBlock("", "SSDT", 2, "hack", "D-EH01", 0)
+{
+    External(_SB.PCI0, DeviceObj)
+    External(_SB.PCI0.EH01, DeviceObj)
+    External(_SB.PCI0.LPCB, DeviceObj)
+
+    // registers needed for disabling EHC#1
+    Scope(_SB.PCI0.EH01)
+    {
+        OperationRegion(RMP1, PCI_Config, 0x54, 2)
+        Field(RMP1, WordAcc, NoLock, Preserve)
+        {
+            PSTE, 2  // bits 2:0 are power state
+        }
+    }
+    Scope(_SB.PCI0.LPCB)
+    {
+        OperationRegion(RMP3, PCI_Config, 0xF0, 4)
+        Field(RMP3, DWordAcc, NoLock, Preserve)
+        {
+            RCB3, 32, // Root Complex Base Address
+        }
+        // address is in bits 31:14
+        OperationRegion(FDM3, SystemMemory, (RCB3 & Not((1<<14)-1)) + 0x3418, 4)
+        Field(FDM3, DWordAcc, NoLock, Preserve)
+        {
+            ,15,    // skip first 15 bits
+            FDE1,1, // should be bit 15 (0-based) (FD EHCI#1)
+        }
+    }
+    Scope(_SB.PCI0)
+    {
+        Device(RMD3)
+        {
+            Name(_HID, "RMD30000")
+            Method(_INI)
+            {
+                // disable EHCI#1
+                // put EHCI#1 in D3hot (sleep mode)
+                ^^EH01.PSTE = 3
+                // disable EHCI#1 PCI space
+                ^^LPCB.FDE1 = 1
+            }
+        }
+    }
+}
+//EOF
diff --git a/hotpatch/SSDT-Disable_EH02.dsl b/hotpatch/SSDT-Disable_EH02.dsl
new file mode 100644
index 0000000..4a04934
--- /dev/null
+++ b/hotpatch/SSDT-Disable_EH02.dsl
@@ -0,0 +1,49 @@
+// Disabling EHCI #1 (and EHCI #2)
+
+DefinitionBlock("", "SSDT", 2, "hack", "D-EH02", 0)
+{
+    External(_SB.PCI0, DeviceObj)
+    External(_SB.PCI0.EH02, DeviceObj)
+    External(_SB.PCI0.LPCB, DeviceObj)
+
+    // registers needed for disabling EHC#1
+    Scope(_SB.PCI0.EH02)
+    {
+        OperationRegion(RMP1, PCI_Config, 0x54, 2)
+        Field(RMP1, WordAcc, NoLock, Preserve)
+        {
+            PSTE, 2  // bits 2:0 are power state
+        }
+    }
+    Scope(_SB.PCI0.LPCB)
+    {
+        OperationRegion(RMP4, PCI_Config, 0xF0, 4)
+        Field(RMP4, DWordAcc, NoLock, Preserve)
+        {
+            RCB4, 32, // Root Complex Base Address
+        }
+        // address is in bits 31:14
+        OperationRegion(FDM4, SystemMemory, (RCB4 & Not((1<<14)-1)) + 0x3418, 4)
+        Field(FDM4, DWordAcc, NoLock, Preserve)
+        {
+            ,13,    // skip first 13 bits
+            FDE2,1, // should be bit 13 (0-based) (FD EHCI#2)
+        }
+    }
+    Scope(_SB.PCI0)
+    {
+        Device(RMD4)
+        {
+            Name(_HID, "RMD40000")
+            Method(_INI)
+            {
+                // disable EHCI#2
+                // put EHCI#2 in D3hot (sleep mode)
+                ^^EH02.PSTE = 3
+                // disable EHCI#2 PCI space
+                ^^LPCB.FDE2 = 1
+            }
+        }
+    }
+}
+//EOF
diff --git a/hotpatch/SSDT-XHC.dsl b/hotpatch/SSDT-XHC.dsl
index 693a7f2..2df2862 100644
--- a/hotpatch/SSDT-XHC.dsl
+++ b/hotpatch/SSDT-XHC.dsl
@@ -21,7 +21,7 @@ DefinitionBlock("", "SSDT", 2, "hack", "XHC", 0)
                 "AAPL,max-port-current-in-sleep", Buffer() { 0x34, 0x08, 0, 0 },
             }
             // force USB2 on XHC if EHCI is disabled
-            If (CondRefOf(\_SB.PCI0.RMD2))
+            If (CondRefOf(\_SB.PCI0.RMD2) || CondRefOf(\_SB.PCI0.RMD3) || CondRefOf(\_SB.PCI0.RMD4))
             {
                 CreateDWordField(DerefOf(Local0[1]), 0, PR2F)
                 PR2F = 0x3fff
Click to expand...
Which example includes a case where you force something on EHCI to XHCI? My last goal is to force the touchscreen from the USB 2.0 hub to XHCI.

Also I edited my previous post with some more information.
 
CoBrA2168 said:
Which example includes a case where you force something on EHCI to XHCI? My last goal is to force the touchscreen from the USB 2.0 hub to XHCI.
Click to expand...

It is not possible to force something directly wired to EHCI to appear on XHCI (there is no facility to route from EHCI to XHCI, only from XHCI to EHCI).
But if that port is actually on XHCI and BIOS is routing it to EHCI by default, then it possible to turn off that routing by changing RM,pr2-force as I mentioned.
Most of my projects set pr2-force as I mentioned for the case EHCI is disabled... just to turn off the routing for the case FakePCIID_XHCIMux is installed.
 
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