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<< Solved >> AMD WX4170 dGPU on ZBook G5 17 Laptop

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H87M-PRO
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i5-4690K
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HD4600 + GTX 660 TI
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  2. MacBook Pro
By changing the modules it changes some unknown items like that GPIO, and this change could contribute to the gpu not properly initializing or
But I have 3 working vbioses and one custom. So problem only in modules, as everything other in zbook vbios is working.

There is a big difference in how Mojave and Catalina X4000 kext initialize/reset the gpu, and I believe the answer may lie there.
Back to compare, this shows that only zbook vbioses are shorted. I even compare other PCIe desktop Polaris and they have those additional features in command modules, but hp Zbook doesn’t. For some reason hp deleted that info. Original vbios even glitchy on Ubuntu, but custom hybrid is working like it should be working!
I even forgot about Windows issues with multiple displays. I don’t know why hp done this, but their laptop vbioses are big problem...
 
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I have an idea for patching l2c bus registers of vbios to get fan control working. I think that the gpu use special registers to talk with chipset. And registers are somewhere in system bios located. Supported GPUs by laptop can use same registers, but unsupported use another registers which is simply missing in system bios. So that’s why they can’t be read. If I will disassemble working gpu and copy that registers, put them in non supported vbios gpu, then theoretically they will work, and communication will be fine. Chipset will read registers and generate pwm. As if data is missing, pwm is not generating pwm, and the fan is 100% speed. This is crazy idea, but could be real ability for get it native working and solve problems of upgrade amd mxm GPUs! Sad thing is amd not manufacturing mxm GPUs anymore... the 41xx, 7100 and 550 is the last...

I don’t think that hw temperature registers are generated by core controller firmware. I will boot Windows to look how AIDA64 is reading ACPI. And what is difference between g3 and g4 thermal acpi



Edit1
The idea fails. Possibly the chipset just can’t read temperature from gpu, mismatch in efi driver. So that’s unsolved. Only way is disable temperature readings with acpi and create acpi table to control pwm with other method. My knowledge can’t help here.

Why Windows success with rom? Simply when rom fails after few seconds of explorer working , Windows will disable gpu and load successfully vbios from main system bios. That’s why my method of testing vbios will fail for you. So we can test builds only with MacOS for you.

MacOS won’t work? AGDCC possibly fails. And rom won’t work. I think, somehow at one place in vbios, the offset could be exist. Some module contain it. I can find it on diff comparison as vortex and aonomorhid has fully same size of VgaFirmware, so diff only in module length. I will try to find out where this could be located, by adding afflec to comparison
 
Last edited:
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I compared Affleck and Aomorhid
And here is diffs in modules. possibly it will help to find mystery offset...
 

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  • Aomorhid.zip
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  • Affleck.zip
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  • CompareDissasembly.zip
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Joined
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Good news! Parser found!

Every vbios has offset with call to this hex! Driver calls it ptrMainCallParserFar, AND ITS LOCATED HERE: (TV_VideoMode/DispOutInfo)
CALL TO THIS VGA FIRMWARE LOCATION
E80100CB83EC068BEC8946006633C0C646040089.....

Previously
Screen Shot 2021-06-21 at 02.05.18.png







Thats why driver cant draw anything if custom vbios not change this offset
 
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NEW VBIOS BUILD
AMD RADEON WX4150 (HP Zbook G3)


DESCRIPTION:
Vaughn VgaFirmware as bootloader
Crane modules

WHATS NEW?
Strusture rebuild
(All modules was realocated - this is proof that modules have no call offsets to other modules, only to firmware with parsers, table offsets. As all offsets are based on begining of the rom, the offsets are easy to patch)
Firmware patch (Backlight controller)
TV_VideoMode patch (Parser replaced)


FEATURES:
More Stable then previous build

explorer_BjMNdIr1xF.png

Screenshot 2021-06-21 at 11.32.39.png


Also need additional patch for Make Bus Build-In, not PCIe, maybe thats is cosmetics, but latest build was trying to switch igpu to mxm
 

Attachments

  • _54_Vau+Cra+Disp+NewLoc+Parser+BL.txt
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  • _54_Vau+Cra+Disp+NewLoc+Parser+BL.rom.zip
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Last edited:
Joined
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Messages
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HD4600 + GTX 660 TI
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  2. MacBook Pro
WX4170RESEARCH
(this tag will be used for fast search in thread and sorting messages)


Lets begin

COMMAND AND DATA MODULES LUT OFFSETs
(From longest to shortest)

HEX - DEC

CRANE (67e8)
9764 - 38756 - the longest Firmware. This offset will be used for wx4170 build

PEGATRON (67e8)
975C - 38748

AFFLECK (67e0)
8B8A - 35722

AOMORHID (67e0)
8AD4 - 35540

RADEON PRO 560 (67ef)
5114 - 20756

RADEON PRO 560X (67ef)
510C - 20748

76E9 Is File Size = EC00 (Crane Original, but should be replaced to 80E9 = 10000 (65536 bytes) to reserve space for modules)


The idea is to split vrom to 3 sections (Header, VgaFirmware aka bootloader and other subprograms, Modules)

- Header contain all important info for GPU core for boot, and useless after boot success
- VgaFirmware aka bootloader is core firmware (can be swaped with any firmware but with same generation of GPU, Apple 5xx has same firm, Zbook G5 4150-4170 same firm) But this is important as somehow could communicate with pcb components.
- Modules contain instructions and specs for GPU



VGA FIRMWARE OFFSETs
(unsorted)

VGA FIRMWARE OFFSETs

CRANE (67e8)
02AD

PEGATRON (67e8)
02A5

AFFLECK (67e0)
029D

AOMORHID (67e0)
02A1

RADEON PRO 560 (67ef)
02A5

RADEON PRO 560X (67ef)
029D

Edit1. For this generation of builds will use Pegatron and Falcon 560 or 560X modules. If they are able to work on 4170, then they could be patched with 4170 specs. The Pegatron is best in this case, as easy patching Hp style modules programming. But vbios itself should be flashed to gpu and logged with Ubuntu.
 
Last edited:
Joined
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Motherboard
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HD4600 + GTX 660 TI
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  2. MacBook Pro
WX4170RESEARCH
(this tag will be used for fast search in thread and sorting messages)


AOMORHID
Research


Look inside PowerPlayInfo and FirmwareInfo (Dissasembly)
Early method of Atom ROM table & PCI INFO READERs


PowerPlayInfo
Research Based on Materials at:

Calculator


uc = 2ch (1byte)
us = 4ch (2byte)
ul = 8ch (16byte)



int8_t c;
int32_t i;
uint8_t uc;
uint32_t ui;
int64_t l;


========================== ========================== ==========================
========================== = BEGINNING OF RESEARCH = ==========================
========================== ========================== ==========================

========================== ========================== ==========================

FA02 - FileSize (LittleEndian)
07 - ucTableFormatRevision
01 - ucTableContentRevision
00 - ucTableRevision
4D00 - usTableSize (LittleEndian)
92060000 - ulGoldenPPID (LittleEndian etc.) // PPGen use only
63260000 - ulGoldenRevision // PPGen use only
1A00 - usFormatId // To be used ONLY by PPGen.
0000 - usVoltageTime // in microseconds
02000000 - ulPlatformCaps // See ATOM_PPLIB_CAPS_*
00000000 ≠ ulMaxODEngineClock
00000000 ≠ ulMaxODMempryClock
0000 ≠ usPowerControlLimit
2300 - usUlvVoltageOffset = 35 by Unsigned short (16-bit) calculator

========================== ========================== ==========================



========================== OFFSET_MAP_LOCATIONS_IN_MODULE ==========================
4D00000078020000B9013F018B00FD00D501C60200008102B602E0020000F04F01005307000000000000
========================== OFFSET_MAP_LOCATIONS_IN_MODULE ==========================


- usStateArrayOffset; // points to ATOM_Tonga_State_Array
- usFanTableOffset; // points to ATOM_Tonga_Fan_Table
- usThermalControllerOffset; // points to ATOM_Tonga_Thermal_Controller
- usReserv; // CustomThermalPolicy removed for Tonga. Keep this filed as reserved. */
- usMclkDependencyTableOffset; // points to ATOM_Tonga_MCLK_Dependency_Table */
- usSclkDependencyTableOffset; // points to ATOM_Tonga_SCLK_Dependency_Table */
- usVddcLookupTableOffset; // points to ATOM_Tonga_Voltage_Lookup_Table */
- usVddgfxLookupTableOffset; // points to ATOM_Tonga_Voltage_Lookup_Table */
- usMMDependencyTableOffset; // points to ATOM_Tonga_MM_Dependency_Table */
- usVCEStateTableOffset; // points to ATOM_Tonga_VCE_State_Table; */
- usPPMTableOffset; // points to ATOM_Tonga_PPM_Table */
- usPowerTuneTableOffset; // points to ATOM_PowerTune_Table */
- usHardLimitTableOffset; // points to ATOM_Tonga_Hard_Limit_Table */
- usPCIETableOffset; // points to ATOM_Tonga_PCIE_Table */
- usGPIOTableOffset; // points to ATOM_Tonga_GPIO_Table */
- usReserved[6];

========================== StateArrayOffset ==========================
******************0000007000100000000000500004000000000000000000100010000000000010000000000000000000000
========================== StateArrayOffset ==========================

// based on ATOM_Tonga_POWERPLAYTABLE

01 - ucRevId
03 - ucNumEntries

00 - ucEngineClockIndexHigh
00 - ucEngineClockIndexLow
00 - ucMemoryClockIndexHigh
00 - ucMemoryClockIndexLow
00 - ucPCIEGenLow
00 - ucPCIEGenHigh
00 - ucPCIELaneLow
00 - ucPCIELaneHigh
0800 - usClassification
000000000 - ulCapsAndSettings
0000 - usClassification2
0000000 - ulUnused

07 - ucEngineClockIndexHigh
00 - ucEngineClockIndexLow
01 - ucMemoryClockIndexHigh
00 - ucMemoryClockIndexLow
00 - ucPCIEGenLow
00 - ucPCIEGenHigh
00 - ucPCIELaneLow
00 - ucPCIELaneHigh
0500 - usClassification
00400000 - ulCapsAndSettings
0000 - usClassification2
00000000 - ulUnused

01 - ucEngineClockIndexHigh
00 - ucEngineClockIndexLow
01 - ucMemoryClockIndexHigh
00 - ucMemoryClockIndexLow
00 - ucPCIEGenLow
00 - ucPCIEGenHigh
00 - ucPCIELaneLow
00 - ucPCIELaneHigh
0100 - usClassification
00000000 - ulCapsAndSettings
0000 - usClassification2
00000000 - ulUnused


========================== PolarisVddcLookup ==========================
000EEE02000000000000200300000000000052030000000000008403000000000000B603000000000000E8030000000000001A0400000000000002FF00000000000003FF00000000000004FF00000000000005FF00000000000006FF00000000000007FF00000000000008FF000000000000
========================== PolarisVddcLookup ==========================
Based on _ATOM_Tonga_Voltage_Lookup_Record


00 - ucRevId
0E - ucNumEntries

EE02 - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh

2003 - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh

5203 - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh

8403 - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh

B603 - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh

E803 - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh

1A04 - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh

02FF - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh

03FF - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh


04FF - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh

05FF - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh

06FF - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh

07FF - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh

08FF - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh


========================== PolarisVddgfxLookup ==========================
0008840300000000000002FF00000000000003FF00000000000004FF00000000000005FF00000000000006FF00000000000007FF00000000000008FF000000000000
========================== PolarisVddgfxLookup ==========================

00 - ucRevId
08 - ucNumEntries

8403 - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000

02FF - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh

03FF - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh

04FF - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh

05FF - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh

06FF - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh

07FF - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh

08FF - usVdd // Base voltage
0000 - usCACLow
0000 - usCACMid
0000 - usCACHigh


========================== PolarisSclkDependency ==========================
010800000098530000000000800000000007E6FFF4C90000000000920000000008E6FF144A0100000000120000000009E6FFC499010000000012000000000AE6FF4CAD010000000012000000000BE6FFC0BB010000000012000000000CE6FFFCCA010000000012000000000DCDFF24D501000000001200000000
========================== PolarisSclkDependency ==========================
Based on _ATOM_Polaris_SCLK_Dependency_Record


01 - ucRevId
08 - ucNumEntries



00 - ucVddInd /* Base voltage */
0000 - usVddcOffset /* Offset relative to base voltage */
98530000 - ulSclk;
0000 - usEdcCurrent;
00 - ucReliabilityTemperature;
80 - ucCKSVOffsetandDisable;
00000000 - ulSclkOffset; //Bits 0~6: Voltage offset for CKS, Bit 7: Disable/enable for the SCLK level


07 - ucVddInd /* Base voltage */
E6FF - usVddcOffset /* Offset relative to base voltage */
F4C90000 - ulSclk;
0000 - usEdcCurrent;
00 - ucReliabilityTemperature;
92 - ucCKSVOffsetandDisable;
00000000 - ulSclkOffset; //Bits 0~6: Voltage offset for CKS, Bit 7: Disable/enable for the SCLK level


08 - ucVddInd /* Base voltage */
E6FF - usVddcOffset /* Offset relative to base voltage */
144A0100 - ulSclk;
0000 - usEdcCurrent;
00 - ucReliabilityTemperature;
12 - ucCKSVOffsetandDisable;
00000000 - ulSclkOffset; //Bits 0~6: Voltage offset for CKS, Bit 7: Disable/enable for the SCLK level


09 - ucVddInd /* Base voltage */
E6FF - usVddcOffset /* Offset relative to base voltage */
C4990100 - ulSclk;
0000 - usEdcCurrent;
00 - ucReliabilityTemperature;
12 - ucCKSVOffsetandDisable;
00000000 - ulSclkOffset; //Bits 0~6: Voltage offset for CKS, Bit 7: Disable/enable for the SCLK level


0A - ucVddInd /* Base voltage */
E6FF - usVddcOffset /* Offset relative to base voltage */
4CAD0100 - ulSclk;
0000 - usEdcCurrent;
00 - ucReliabilityTemperature;
12 - ucCKSVOffsetandDisable;
00000000 - ulSclkOffset; //Bits 0~6: Voltage offset for CKS, Bit 7: Disable/enable for the SCLK level


0B - ucVddInd /* Base voltage */
E6FF - usVddcOffset /* Offset relative to base voltage */
C0BB0100 - ulSclk;
0000 - usEdcCurrent;
00 - ucReliabilityTemperature;
12 - ucCKSVOffsetandDisable;
00000000 - ulSclkOffset; //Bits 0~6: Voltage offset for CKS, Bit 7: Disable/enable for the SCLK level


0C - ucVddInd /* Base voltage */
E6FF - usVddcOffset /* Offset relative to base voltage */
FCCA0100 - ulSclk;
0000 - usEdcCurrent;
00 - ucReliabilityTemperature;
12 - ucCKSVOffsetandDisable;
00000000 - ulSclkOffset; //Bits 0~6: Voltage offset for CKS, Bit 7: Disable/enable for the SCLK level


0D - ucVddInd /* Base voltage */
CDFF - usVddcOffset /* Offset relative to base voltage */
24D50100 - ulSclk;
0000 - usEdcCurrent;
00 - ucReliabilityTemperature;
12 - ucCKSVOffsetandDisable;
00000000 - ulSclkOffset; //Bits 0~6: Voltage offset for CKS, Bit 7: Disable/enable for the SCLK level



========================== PolarisMclkDependency ==========================
00020020030000E80330750000000000E8030000E803F04902000000
========================== PolarisMclkDependency ==========================
00 - ucRevId
02 - ucNumEntries


00 - ucVddcInd // Vddc voltage
2003 - usVddci
0000 - usVddgfxOffset // Offset relative to Vddc voltage
E803 - usMvdd
30750000 - ulMclk
0000 - usReserved


00 - ucVddcInd // Vddc voltage
E803 - usVddci
0000 - usVddgfxOffset // Offset relative to Vddc voltage
E803 - usMvdd
F0490200 - ulMclk
0000 - usReserved

========================== PolarisMMDependency ==========================
000700000008CF000070110100A8DE00000000000050C3000001B4FF90E20000F824010018F6000000000000A8DE0000029BFF18F6000080380100880D01000000000000FA00000382FFA0090100084C0100F824010000000000701101000469FF281D0100A85B0100683C010000000000E02801000537FFC82C010060670100F04F010000000000683C01000605FF80380100187301007863010000000000084C0100
========================== PolarisMMDependency ==========================
Based on ATOM_Tonga_MM_Dependency_Record



00 - ucRevId
07 - ucNumEntries


00 - ucVddcInd //VDDC voltage
0000 - usVddgfxOffset //Offset relative to VDDC voltage
08CF0000 - ulDClk //UVD D-clock
70110100 - ulVClk //UVD V-clock
A8DE0000 - ulEClk //VCE clock
00000000 - ulAClk //ACP clock
50C30000 - ulSAMUClk


01 - ucVddcInd //VDDC voltage
B4FF - usVddgfxOffset //Offset relative to VDDC voltage
90E20000 - ulDClk //UVD D-clock
F8240100 - ulVClk //UVD V-clock
18F60000 - ulEClk //VCE clock
00000000 - ulAClk //ACP clock
A8DE0000 - ulSAMUClk


02 - ucVddcInd //VDDC voltage
9BFF - usVddgfxOffset //Offset relative to VDDC voltage
18F60000 - ulDClk //UVD D-clock
80380100 - ulVClk //UVD V-clock
880D0100 - ulEClk //VCE clock
00000000 - ulAClk //ACP clock
00FA0000 - ulSAMUClk



03 - ucVddcInd //VDDC voltage
82FF - usVddgfxOffset //Offset relative to VDDC voltage
A0090100 - ulDClk //UVD D-clock
084C0100 - ulVClk //UVD V-clock
F8240100 - ulEClk //VCE clock
00000000 - ulAClk //ACP clock
70110100 - ulSAMUClk


04 - ucVddcInd //VDDC voltage
69FF - usVddgfxOffset //Offset relative to VDDC voltage
281D0100 - ulDClk //UVD D-clock
A85B0100 - ulVClk //UVD V-clock
683C0100 - ulEClk //VCE clock
00000000 - ulAClk //ACP clock
E0280100 - ulSAMUClk


05 - ucVddcInd //VDDC voltage
37FF - usVddgfxOffset //Offset relative to VDDC voltage
C82C0100 - ulDClk //UVD D-clock
60670100 - ulVClk //UVD V-clock
F04F0100 - ulEClk //VCE clock
00000000 - ulAClk //ACP clock
683C0100 - ulSAMUClk


06 - ucVddcInd //VDDC voltage
05FF - usVddgfxOffset //Offset relative to VDDC voltage
80380100 - ulDClk //UVD D-clock
18730100 - ulVClk //UVD V-clock
78630100 - ulEClk //VCE clock
00000000 - ulAClk //ACP clock
084C0100 - ulSAMUClk


========================== ThermalController ==========================
011700008000000000
========================== ThermalController ==========================
Based on Tonga_Thermal_Controller


01 - ucRevId;
17 - ucType; //one of ATOM_TONGA_PP_THERMALCONTROLLER
00 - ucI2cLine; //as interpreted by DAL I2C
00 - ucI2cAddress;
80 - ucFanParameters; //Fan Control Parameters
00 - ucFanMinRPM; //Fan Minimum RPM (hundreds) -- for display purposes only
00 - ucFanMaxRPM; //Fan Maximum RPM (hundreds) -- for display purposes only
00 - ucReserved;
00 - ucFlags; //to be defined


========================== PolarisPowerTune ==========================

========================== PolarisPowerTune ==========================

04 - ucRevId
3200 - usTDP = 32*16
0000 - usConfigurableTDP
2A00 - usTDC
3200 - usBatteryPowerLimit
3200 - usSmallPowerLimit
0000 - usLowCACLeakage
0000 - usHighCACLeakage
3200 - usMaximumPowerDeliveryLimit
5A00 - usTjMax
0000 - usPowerTuneDataSetID
0000 - usEDCLimit
5E00 - usSoftwareShutdownTemp
0200 - usClockStretchAmount
6900 - usTemperatureLimitHotspot
5000 - usTemperatureLimitLiquid1
5000 - usTemperatureLimitLiquid2
0000 - usTemperatureLimitVrVddc
0000 - usTemperatureLimitVrMvdd
5000 - usTemperatureLimitPlx
00 - ucLiquid1_I2C_address
00 - ucLiquid2_I2C_address
90 - ucLiquid_I2C_Line
00 - ucVr_I2C_address
90 - ucVr_I2C_Line
00 - ucPlx_I2C_address
90 - ucPlx_I2C_Line
3200 - usReserved



========================== UNKNOWN ==========================
0500000000
========================== UNKNOWN ==========================
Based on UNKNOWN

0500000000



========================== PolarisHardLimit - typeRecord ==========================
01 - ucRevId
01 - ucNumEntries
8C550000 - ulSCLKLimit
24770000 - ulMCLKLimit
E803 - usVddcLimit
0000 - usVddciLimit
E803 - usVddgfxLimit


//////////// Pegatron Vs VORTEX ////////////////
////// 08E80000 Vs FCE90000 - ulSCLKLimit //////
////// F0490200 Vs 24770000 - ulMCLKLimit //////
////////////////////////////////////////////////


========================== PolarisVCEState ==========================
01 - ucRevisionID
06 - ucNumEntries

00 - ucVCEClockIdx // References MM dep table, the VCEDependencyTableOffset value
00 - ucFlag // 2 bits indicates memory p-states?
01 - ucSCLKIdx
01 - ucMCLKIdx

00 - ucVCEClockIdx
00 - ucFlag
01 - ucSCLKIdx
01 - ucMCLKIdx

00 - ucVCEClockIdx
02 - ucFlag
01 - ucSCLKIdx
01 - ucMCLKIdx

00 - ucVCEClockIdx
02 - ucFlag
01 - ucSCLKIdx
01 - ucMCLKIdx

00 - ucVCEClockIdx
02 - ucFlag
01 - ucSCLKIdx
01 - ucMCLKIdx

00 - ucVCEClockIdx
02 - ucFlag
01 - ucSCLKIdx
01 - ucMCLKIdx



========================== PolarisPCIE ==========================
010300000800FC0A000000000800F465000002000800F4650000
========================== PolarisPCIE ==========================
01 - ucRevId - // Table version is 1
03 - ucNumEntries

00 - ucPCIEGenSpeed
0008 - usPCIELaneWidth
00FC0A00 - ulPCIEClock
00 - ucReserved1

00 - ucPCIEGenSpeed
0008 - usPCIELaneWidth
00F46500 - ulPCIEClock
00 - ucReserved1

02 - ucPCIEGenSpeed
0008 - usPCIELaneWidth
00F46500 - ulPCIEClock
00 - ucReserved1

FirmwareInfo



Materials used


========================== ========================== ==========================
========================== = BEGINNING OF RESEARCH = ==========================
========================== ========================== ==========================

6C0002020100320F985300003075000000000000407E05000000000000000000C02709000000000092F40000000020039A0B70170000000028880400000000000000000000000000409CC40910276B033E401027102710270000000000000000000000000000000000000000

========================== ========================== ==========================
========================== = FIRMWARE INFO = ==========================
========================== ========================== ==========================

usStructureSize = 0x006c (108)
ucTableFormatRevision = 0x02 (2)
ucTableContentRevision = 0x02 (2)
ulFirmwareRevision = 0x0f320001 (254935041)



ulDefaultEngineClock = 0x00005398 (21400) //In 10Khz unit
ulDefaultMemoryClock = 0x00007530 (30000) //In 10Khz unit

ulReserved [0] = 0x00000000 (0)
ulReserved [1] = 0x00057e40 (360000)
ulReserved1 = 0x00000000 (0)
ulReserved2 = 0x00000000 (0)

ulMaxPixelClockPLL_Output = 0x000927c0 (600000) //In 10Khz unit
ulBinaryAlteredInfo = 0x00000000 (0)
ulDefaultDispEngineClkFreq = 0x0000f492 (62610) //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.
ucReserved3 = 0x00 (0)
ucMinAllowedBL_Level = 0x00 (0)
usBootUpVDDCVoltage = 0x0320 (800) //In MV unit
usLcdMinPixelClockPLL_Output = 0x0b9a (2970) // In MHz unit
usLcdMaxPixelClockPLL_Output = 0x1770 (6000) // In MHz unit
ulReserved4 = 0x00000000 (0)
ulMinPixelClockPLL_Output = 0x00048828 (297000) // In MHz unit
ulReserved5 = 0x00000000 (0)
ulReserved6 = 0x00000000 (0)
ulReserved7 = 0x00000000 (0)
usReserved11 = 0x9c40 (40000) //In 10Khz unit, Max. Pclk used only for DAC
usMinPixelClockPLL_Input = 0x09c4 (2500) //In 10Khz unit
usMaxPixelClockPLL_Input = 0x2710 (10000) //In 10Khz unit
usBootUpVDDCIVoltage = 0x036b (875) //In unit of mv; Was usMinPixelClockPLL_Output;



ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability :


ATOM_FIRMWARE_CAPABILITY sbfAccess (union)
usFirmwarePosted:1 = 0x0000 (0)
usDualCRTC_Support:1 = 0x0001 (1)
usExtendedDesktopSupport:1 = 0x0001 (1)
usMemoryClockSS_Support:1 = 0x0001 (1)
usEngineClockSS_Support:1 = 0x0001 (1)
usGPUControlsBL:1 = 0x0001 (1)
usWMI_SUPPORT:1 = 0x0000 (0)
usPPMode_Assigned:1 = 0x0000 (0)
usHyperMemory_Support:1 = 0x0000 (0)
usHyperMemory_Size:4 = 0x0000 (0)
usReserved:3 = 0x0002 (2)
usSusAccess (union) = 0x403e (16446) BE = 3E40


usCoreReferenceClock = 0x2710 (10000) //In 10Khz unit
usMemoryReferenceClock = 0x2710 (10000) //In 10Khz unit
usUniphyDPModeExtClkFreq = 0x2710 (10000) //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
ucMemoryModule_ID = 0x00 (0) //Indicate what is the board design
ucReserved9 [0] = 0x00 (0)
ucReserved9 [1] = 0x00 (0)
ucReserved9 [2] = 0x00 (0)
usBootUpMVDDCVoltage = 0x0000 (0) //In unit of mv; Was usMinPixelClockPLL_Output
usReserved12 = 0x0000 (0)
ulReserved10 [0] = 0x00000000 (0)
ulReserved10 [1] = 0x00000000 (0)
ulReserved10 [2] = 0x00000000 (0) // New added comparing to previous version



ADDED TEST BUILD OF Atom ROM table READER_early + PCI INFO READER_early
 

Attachments

  • AOMORHID_PP_Research (2).txt
    15.2 KB · Views: 13
  • AOMORHID_Firmware_Research.txt
    5 KB · Views: 10
  • Atom ROM table + PCI INFO READER_early.zip
    6.5 KB · Views: 10
Last edited:
Joined
Mar 29, 2019
Messages
157
Motherboard
H87M-PRO
CPU
i5-4690K
Graphics
HD4600 + GTX 660 TI
Mac
  1. iMac
  2. MacBook Pro
END WX4170 GPU BIOS PATCHING PROJECT STATEMENT


After a lot of tryies and researches, project will be closed for a while. All discoveries are present in thread.

MAIN PROBLEM: HP ZBook vbios roms have problems in Ubuntu, MacOs and wont work on Catalina and higher. In most cases the problem refers PowerManagment, HDCP, Backlight, Connectors color issues (Dp, eDp, HDMI).

GLITCHY ROMS BY HP: WX4150 (Vaughn ((Zbook G4), Vortex ((Zbook G5)), WX4170 (Affleck (Zbook G4), Aomorhid (Zbook G5))

STABLE ROMS (
NEED A LOT PATCHES): WX4150 (Dell - Crane (Laptop mobile rom), HP - Pegatron (Desktop, MiniPC))


POSSIBLE SOLUTION

As there is no WX4170 vbios for usage away from Zbooks, We need to patch OEM vbios to get not existing properties, or create new build based on WX4150.

I think that every vbios consists of different parts:
- Header
(File Size Info, Boot Tables info offsets, PCI Info config, Atom Bios Info, Boot message, Config.h file, Bios filename, PCI host specs, etc)
RESEARCH VAUGHN WX4150


55 AA FILE MASK
7F E9 FILE SIZE

A1 02 OFFSET TO “MP” FILE INSIDE VGA FIRMWARE ??????????????????????????

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

44 02 OFFSET TO PCIR (0x0244)

00 00 00 00

49 42 4D IBM (ASCII)

04 CRC-8 FileChecksum (Based on Filesize E97F)

3A 88 OFFSET TO PFR IMAGE ??????????????????????????????

00 00 00 00 00 00 00 00 00 00 00

04 20

37 36 31 32 39 35 35 32 30 761295520

00 00 00 00 00 00

99 02 OFFSET TO VGA FIRMWARE (0x0299)

00 00 00 00 00 00

20 02 OFFSET TO ATOM SIGNATURE (0x0220) (ATOM)

00 00 00 00 00 00

31 32 2F 30 32 2F 31 36 2C 31 30 3A 31 34 3A 30 30 12/02/16,10:14:00 - RELEASE DATE (loc 0x0050) (ASCII)

00 00
00 E9 Unknown Feature (Not offset)
A7 03 Offset to (hex = 01C706A8043D59891EAA)
00 E9
B1 03 Offset to (hex = 042E8E1ED5038BC3A3)
00 00
00 F4 Offset to Filename (BR01090.001)
00 00
15 00
00 00
D0 01 Unknown Feature (Not offset)
00 AA Unknown Feature (Not offset)
01 21 Unknown Feature (Not offset)
E1 02 Unknown Feature (Not offset)
80 7E Unknown Feature (Not offset)
00 22 Unknown Feature (Not offset)
0F 44 Unknown Feature (Not offset)
02 12 Unknown Feature (Not offset)
00 00 00 00 00 00
3C 40 Unknown Feature (Not offset)
0E 02 Unknown Feature (Not offset)
07 3C Unknown Feature (Not offset)
01 1A Unknown Feature (Not offset)
00 04 Unknown Feature (Not offset)
00 00
00 EE
A0 FF
06 00
08 30
40 0E
01 00
00 00 00 00
00 14
03 00
00 00 00 00
00 BE
7E 11
00 B9
07 1A
D6 50
2C 00
00 00 00 00 00 00 00 00
00 0C
40 41
43 00
00 00
00 10
00 00
00 42
00 00
00 80 Unknown Feature (Affleck = 00 00)
7E 06
00 20
00 20
00 12
00 0E
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00 42 52 30 31 30 39 30 2E 30 30 31 BR01090.001 (ASCII)

00
46 47 4C 20 42 41 46 46 49 4E 4D 00 50 43 49 5F 45 58 50 52 45 53 53 00 47 44 44 52 35 FGL BAFFINMPCI_EXPRESSGDDR5 (ASCII)

00

0D 0A

48 50 20 56 61 75 67 68 6E 20 47 31 2D 35 30 20 47 44 44 52 35 HP Vaughn G1-50 GDDR5 (Product Name) (ASCII)

20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20

0D 0A 00 0D 0A 20 0D 0A 00

28 43 29 20 31 39 38 38 2D 32 30 31 30 2C 20 41 64 76 61 6E 63 65 64 20 4D 69 63 72 6F 20 44 65 76 69 63 65 73 2C 20 49 6E 63 2E (C) 1988-2010, Advanced Micro Devices, Inc. (ASCII)

00

41 54 4F 4D 42 49 4F 53 42 4B 2D 41 4D 44 ATOMBIOSBK-AMD (ASCII)

20

56 45 52 VER (ASCII)
30 31 35 2E 30 35 30 2E 30 30 30 2E 30 30 30 2E 30 30 31 30 39 30 015.050.000.000.001090 (BIOS VERSION) (ASCII)

00 42 52 30 31 30 39 30 2E 30 30 31 20 00 31 33 34 38 38 34 37 20 00 33 36 38 31 32 34 20 20 00 20 20 20 20 20 20 20 20 00 48 50 5F 42 41 46 46 49 4E 4D 5F 47 4C 50 52 4F 5F 56 41 55 47 48 4E 5F 47 44 44 52 35 5F 4D 58 4D 5C 63 6F 6E 66 69 67 2E 68 00 00 00 90



ATOM ($...ATOM.АЕКiк….<ХЂD†‹,Њ .)
24 00 FileSize (0024)
01 01 Version (0101)
41 54 4F 4D ATOM (ASCII) (Atom Magic) uaFirmWareSignature[4]
00 C0 OFFSET TO BIOS Runtime Segment Address (0x00C0)
C5 03 OFFSET TO ProtectedModeInfo (0x03C5) (PM IMAGE)
CA 01 OFFSET TO ConfigFileName (0x01CA) BR01090.001 (ASCII)
69 02 OFFSET TO CRC_Block (0x0269) (HEX = B7 28 39 10)
1E 01 OFFSET TO BiosBootupMessage (0x011E)
EA 03 OFFSET TO (0x03EA) Int 10
00 00 PCI Bus Device Init Code
00 00 IO Base Address
3C 10 SUBVENDOR ID (HP)
D5 80 SSID (80D5)
44 02 OFFSET TO PCIR (0x0244)
86 8B OFFSET TO COMMAND TABLE (0x8B86)
2C 8C OFFSET TO DATA TABLE (0x8C2C)
A0 Extended Function Code
00 Reserved










PCI CONFIG

50 43 49 52 PCIR (ASCII)
02 10 VENDOR ID
E8 67 DEVICE ID
00 00
18 00
00 00
00 03
7F 00
32 0F
00 80 UEFI GOP DISABLED (00 00 - is for enabled)
00 00
41 4D
44 20
41 54 4F 4D 42 49 4F 53 AMD ATOMBIOS (ASCII)
00 B7 28 39 10 00 CRC_Block
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- Bootloader
- MP, PFR IMAGE,
AND a lot subprograms, that can be located until the begining of COMMAND TABLE, DATA TABLE OFFSETS LUTs.
- LUTs: COMMAND TABLE, DATA TABLE OFFSETS
- Data modules,
(TVOUTINFO module uses Parser Offset to bootloader subprogram)
- Zero bytes between some modules
- Command modules.
- End Of File
(FF padding)
- UEFI GOP (Base graphic output protocol aka Efi driver)
- GOP Tables Always at 38000 Offset (Base graphic output protocol aka Efi driver)

Then next proofed discovery: Comparing mbp 13.3 i saw that starting from bootloader and till to Command and Data tables the image is fully Identical, The Apple is using one Gpu firmware aka bootloader for whole 4XX generation GPU. So difference only in Header info and data, command tables. So this data and command tables is making GPU Specs and distinguishes Radeon Pro 450 from 460. Then i done the same comparison with MBP 14,3 5XX Gpus, and they was using not 4XX firmware, but was identical at 5XX, and again only diff at modules. I was wanting to get third proof, and was lucky with Zbook G5 Vbioses (4150 Vortex and 4170 Aomorhid), and voila the firmware is identical. So only what is making WX4170 so powerfull is one or more of 12 differentces in modules. So if patch important data inside modules, the specs will be change.

Going forward: we can use stable rom and patch specs to meet the wanted results.
To make this trick we need compare Vortex modules to working Crane and Pegatron roms. So we get 24 differences in Crane and only 11 differences in Pegatron Desktop. The Pegatron main problem - it couldnt be used without power supply connected to laptop, as it has no Low Power mod, it will kill Vrms, or charger controller. But it could be tested only on AC without any problems.

So if compare Crane, Vaughn and Pegatron modules, we can find the differences that making rom laptop type, then patch Pegatron modules to make it mobile.

After this patch compare Vortex and Aomorhid modules make 4150 vbios specs same as 4170. The only problem then is vbios signature verification in Windows. As I can’t find any security protection in the vrom, the only security protection is CRC PCI signature, but I cannot find this present in hex of Windows drivers. But if this crc signature check vbios, I can’t find the way of this signature created. But the other possible method, which is easier: Windows driver could have repository with checksums of 16 or 32 bytes. So driver could read vbios, generate checksum ans compare with the repository. If this checksum is not equal, then driver will not initialize, but if ok, then driver will work. If this method is used, then it could be reversed and generate crc formula revealed. This formula could be migrated to standalone app to help generate true checksum patch for vbios. Anyway the easiest way is use PixelClockPatch with bios signature verification feature before reboot after drivers are installed.

Later will add files and components



UPDATING.....
 
Last edited:
Joined
Mar 29, 2019
Messages
157
Motherboard
H87M-PRO
CPU
i5-4690K
Graphics
HD4600 + GTX 660 TI
Mac
  1. iMac
  2. MacBook Pro
Debug Version of 4170 based on 4150 Pegatron but with specs of 4170

This modules were replaced:
Cmd_ASIC_Init_Aomorhid.rom
Cmd_ClockSource_Aomorhid.rom
Cmd_SetVoltage_Aomorhid.rom
Cmd_SpeedFanControl_Aomorhid.rom
Data_ASIC_ProfilingInfo l ASIC_VDDCI_Info_Aomorhid.rom
Data_FirmwareInfo_Aomorhid.rom
Data_Object_Info_Aomorhid-patched.rom
Data_Object_Info_Aomorhid.rom
Data_PowerPlayInfo_Aomorhid.rom
Data_VoltageObjectInfo_Aomorhid.rom
Data_VRAM_Info_Aomorhid.rom
Data_VRAM_Info_Pegatron.rom

Also HP bug fixed at Object_Info





PegAom-Modules4170-vramPeg
Is using Pegatron VramInfo

PegAom-Modules4170-vramAomorhid
(If PegVram will fail) Is using Aomorhid VramInfo


IMPORTANT:
First boot to Ubuntu and record bootsequence loging (it will appear if something wrong with device\rom)
If boot is okay, then boot to windows. If windows is okay too, then Discrete mode can be tested. If something is failing - report!
 

Attachments

  • PegAom-Modules4170-vramAomorhid.rom.zip
    114.7 KB · Views: 8
  • PegAom-Modules4170-vramPeg.rom.zip
    115 KB · Views: 10
Joined
Mar 29, 2019
Messages
157
Motherboard
H87M-PRO
CPU
i5-4690K
Graphics
HD4600 + GTX 660 TI
Mac
  1. iMac
  2. MacBook Pro
FOR FUTURE VBIOS BUILD FOR 4170

Modules collection:

modules_Affleck-4170
modules_Aomorhid-4170
modules_Apple_560x
modules_dell-4150
modules_hp_Pegatron-4150Desktop
modules_hp_Vaughn-4150
modules_hp_Vortex-4150



Added Diffs of:
Aomorhid_vs_560X
Aomorhid_vs_Affleck
Aomorhid_vs_Pegatron
Vaughn_vs_Affleck
Vaughn_vs_Aomorhid
Vaughn_vs_Pegatron
Vaughn_vs_Vortex
 

Attachments

  • 4150+4170+560Modules.zip
    450.4 KB · Views: 13
  • Diff01.zip
    258.1 KB · Views: 7
Last edited:
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