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10.7.4 Sandy Bridge CPU Power Management Fix

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mumstead said:
Strange. With the overclock SSDT I am only reaching Pstates 16 17 18 19 20 42. I am using a 2600k @ 4200 with a Z68X-UD3H-B3 and MacPro3,1. Why am I not getting anything between 20 and 42?

Same here. Z68X-UD3P, 2600k, MacPro3,1 and my states are: MSRDumper PStatesReached: 16 17 18 19 20 42
 
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FishCow said:
samisnake said:
thanks for the tips h8tr, fishcow and xxmacmanxx

fishcow, does your system sleep alright with that added to scope_pr?


I'll report back what I find out.
cheers
Hmmm - surprising.
Sleep, wake from sleep and restart after sleep appears to be working even with FireWire device.
I generally don't sleep my hack, but good to know I can I guess :)
Hope the info helps
 
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I'm still having issues using a P8Z68-V Pro with a Core i7-2600K @ 4.2GHz. Bios 3203 patched.

Current (self-built using Maldon method) DSDT & DropSSDT=Yes: CoreMulti 16 & 42.
New generic SSDT with or without DSDT: CoreMulti 16 only.

Should I wait for the new patched DSDT (I see they were pulled a few days ago) or is there something else I need to do? I see Macman mentioned something about moving processor code from SSDT to DSDT a couple of pages back.

Of note I can boot 3203 without a DSDT (I just lose HDEF).

Awesome work on the whole guys, this is by far the most stable Hack I've had, and I can cope with 16/42 multipliers in the meantime.
 
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SSDT failed on my setup. Had to revert back to DropSSDT and I am thus cycling between 1.6 and 4.4.

My question is, could this possibly because my OC is 4.4 instead of 4.2 or is there likely some other factor at work?

My gear:

MB - GA-Z68XP-UD4 (Bios downgraded to F5, and using DSDT for F5 from this site's library)

CPU - 2500K @ 4.4

MultiBeast settings are:

DSDT + Trim (for SSD), eSATA, IOAHCIBlock + FakeSMC +Plugins + 64-bit screen + Mac Pro 3,1 Def

org plist is basically standard looking.

First response to the MultiBeast w/ OC SSDT was KP. Tweaked a few BIOS settings, and managed to avoid KP, but stuck @ 1.6. Reverted back and now I'm back to "Toggle Mode" :p

Hope a picture emerges from these reports.
 
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philz said:
For the overclockers above 4.2 (that's what multibeast OC goes up to) take a look at the second post in my OC thread:
viewtopic.php?f=49&t=60862

Should make it work. Remember that system definition still matters, macmini5,1 works fine or 5,3 :)

Update: Using this guide as a template, I modified for my 4.4 OC and I'm now getting incremental multipliers.

Oddly, I don't get these unless I have DropSSDT = Yes.

Either I misread something, or something is odd. I don't really care though, it works :)

Thank you Sir Geek.
 

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I am using a Core i5-2405S. I have not updated Lion at this time (still at 10.7.3). Do I need this "fix" after updating to 10.7.4?
 
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MacMan said:
This fix was tested on an ASUS P8P67 Pro with a modded BIOS and an i5-2500K without a DSDT.

To use a DSDT with the ASUS you will need to move the Processor code from the SSDT to the DSDT before using this fix.

MacMan,

Thanks for coming up with a fix so fast! :). Which BIOS version did that board have? It seems the odd behaviour of Asus boards with regards to the _PR section in the DDST has changed in the 3k BIOS and the edits described in this thread are no longer necessary.

For me (P8P67 Pro on BIOS 3207) the results from Multibeast don't seem to be as good as for people who are still on a 2k BIOS.
 
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Ok,

my Speedstepping is also working now (Thanks to H8TR), but there are still some information I'd like to share.

First of all, like racerx already said somewhere, if you have a specific Mac Model (like me, MacPro 5,1) you can only get a specific amount of p-states. I will only get five.

Another "fix" I made to my DSDT is, to integrate the SSDT. I'm not sure how important this fix is or whether you can ignore it or not, but I'm now capable of booting, even though I'm using the DropSSDT command, which proves that my first idea I mentioned earlier is correct.

So, here is what I did:

If your SSDT looks like this or similar (it has a line with "Processor (P0000....)"), you may want to apply this fix:

Code:
Scope (\_PR)
    {
        Processor (P000, 0x01, 0x00000410, 0x06)
        {
            Method (_PDC, 1, NotSerialized)
            {
                \_PR.PDC (Arg0)
            }

            Method (_OSC, 4, NotSerialized)
            {
                Return (\_PR.OSC)
                Arg0
                Arg1
                Arg2
                Arg3
            }
        }

        Processor (P001, 0x02, 0x00000410, 0x06)
        {
            Method (_PDC, 1, NotSerialized)
            {
                \_PR.PDC (Arg0)
            }

            Method (_OSC, 4, NotSerialized)
            {
                Return (\_PR.OSC)
                Arg0
                Arg1
                Arg2
                Arg3
            }
        }

        Processor (P002, 0x03, 0x00000410, 0x06)
        {
            Method (_PDC, 1, NotSerialized)
            {
                \_PR.PDC (Arg0)
            }

            Method (_OSC, 4, NotSerialized)
            {
                Return (\_PR.OSC)
                Arg0
                Arg1
                Arg2
                Arg3
            }
        }

        Processor (P003, 0x04, 0x00000410, 0x06)
        {
            Method (_PDC, 1, NotSerialized)
            {
                \_PR.PDC (Arg0)
            }

            Method (_OSC, 4, NotSerialized)
            {
                Return (\_PR.OSC)
                Arg0
                Arg1
                Arg2
                Arg3
            }
        }
    }


Open your DSDT.aml and Search for "APSS". If you do not find it, than you should skip this post as it is not important for you.

The method "APSS" is in the "Scope (_PR)". Scroll down to the end of the scope to the last line before the scope is closed with a "}" (You need to integrate your SSDT to this scope).

Code:
[...]            }

            And (PDCV, CAP, PDCV)
            If (LEqual (CINT, Zero))
            {
                Store (One, CINT)
                If (LEqual (And (PDCV, 0x09), 0x09))
                {
                    If (LNotEqual (NPSS, Zero))
                    {
                        Load (SSDT, HNDL)
                    }
                }

                If (LEqual (And (PDCV, 0x10), 0x10))
                {
                    If (LNotEqual (NCST, 0xFF))
                    {
                        Load (CSDT, CHDL)
                    }
                }
            }

            Return (Arg3)
        }

      You need to paste it here!

}

Copy and Paste the data from the SSDT. Don't start at the first line, start with "Processor (P000, 0x01, 0x00000410, 0x06)". Watch out that you do not copy the last two "}" from your SSDT as this closes the definition block and scope that you do not want in your DSDT.

Code:
            }

            And (PDCV, CAP, PDCV)
            If (LEqual (CINT, Zero))
            {
                Store (One, CINT)
                If (LEqual (And (PDCV, 0x09), 0x09))
                {
                    If (LNotEqual (NPSS, Zero))
                    {
                        Load (SSDT, HNDL)
                    }
                }

                If (LEqual (And (PDCV, 0x10), 0x10))
                {
                    If (LNotEqual (NCST, 0xFF))
                    {
                        Load (CSDT, CHDL)
                    }
                }
            }

            Return (Arg3)
        }

        Processor (P000, 0x01, 0x00000410, 0x06)
        {
            Method (_PDC, 1, NotSerialized)
            {
                \_PR.PDC (Arg0)
            }

            Method (_OSC, 4, NotSerialized)
            {
                Return (\_PR.OSC)
                Arg0
                Arg1
                Arg2
                Arg3
            }
        }

        Processor (P001, 0x02, 0x00000410, 0x06)
        {
            Method (_PDC, 1, NotSerialized)
            {
                \_PR.PDC (Arg0)
            }

            Method (_OSC, 4, NotSerialized)
            {
                Return (\_PR.OSC)
                Arg0
                Arg1
                Arg2
                Arg3
            }
        }

        Processor (P002, 0x03, 0x00000410, 0x06)
        {
            Method (_PDC, 1, NotSerialized)
            {
                \_PR.PDC (Arg0)
            }

            Method (_OSC, 4, NotSerialized)
            {
                Return (\_PR.OSC)
                Arg0
                Arg1
                Arg2
                Arg3
            }
        }

        Processor (P003, 0x04, 0x00000410, 0x06)
        {
            Method (_PDC, 1, NotSerialized)
            {
                \_PR.PDC (Arg0)
            }

            Method (_OSC, 4, NotSerialized)
            {
                Return (\_PR.OSC)
                Arg0
                Arg1
                Arg2
                Arg3
            }
        }
}

After you copied it to your DSDT, press compile. If you get an error like "Too few arguments, \_PR.OSC needs 4 arguments", got to each line for each processor core and edit this:

Code:
Return (\_PR.OSC)

to look like this:

Code:
Return (\_PR.OSC(Arg0, Arg1, Arg2, Arg3)

Don't forget to delete the Arg0, Arg1, Arg2 and Arg3 that are under the \_PR.OSC(Arg0, Arg1, Arg2, Arg3).

Put your DSDT.aml to Extra/Extension and try it out!

Greetings,

xxmacmanxx
 

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Craigrox said:
In the main post it says the first i5 that is supported is the 2500. I am using the i5-2400 which the standard clock speed is 200MHz slower I believe. I have been affected by the 10.7.4 update and am wondering if it is safe for me to use this new fix?

When I added DropSSDT to chameleon before now the pc would fail to boot with something similar to TJMax=0.

Thank you for the update and hope it supports my system!

You don't need this fix for your processor type.
 
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Anyone with P8Z68V-PRO DSDT (ROM 3XXX) with SSDT processor fix working? Can you share your DSDT? Thanks.
 
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