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[SUCCESS] Gigabyte Designare Z390 (Thunderbolt 3) + i7-9700K + AMD RX 580

@CaseySJ Recently I'm getting (rather rare) CPU panics, seems like some issue with the NVME controller, panic log and my Clover EFI folder attached.

I'm using a Mushkin Helix-L 500 M.2 SSD in slot 1 (Windows) and a Samsung 970 Evo Plus M.2 SSD in slot 2 for the Hackintosh. Any idea?
 

Attachments

  • CLOVER.zip
    5.8 MB · Views: 65
  • cpu_panic.txt
    6.2 KB · Views: 138
Just updated!, thanks for your help
Checksum is correct now. But I guess your new UI will require dynamic recalculation of the checksum.

Can you explain (with screenshots if possible) what is the method to calculate checksum after vendor and device name changing please?
You could try to find the answer in my script. When any information is changed, the two bytes that store the length is updated (linux source code says the max length value is 0x3FF; add 13 to get the total = 0x40c bytes, but linux patch notes says Apple ThunderboltDROM's are always 0x100 bytes max so you should probably limit max size to that). crc32c checksum is recalculated using all the bytes starting from offset 13.

I still expect to post a Mini-Guide for ThunderboltUtil and to update each of the Thunderbolt DROM Micro-Guides. Coming soon.
A super mini guide:
Code:
source ThunderboltUtil.sh
loadamlfile SSDT-TBOLT3-RP05-PORT7-DESIGNARE-Z390.aml
usedromnum 1
# use "dumpdrom" command any time to see how each change affects it (checksums and length are hidden)
busnumber=0
setuid  $(printf "%016x" $(( (((((RANDOM << 15) + RANDOM) << 15) + RANDOM) & 0xffffffffff) << 8 + busnumber )))
setstring 1 "vendor"
setstring 2 "device"
makedromdsl
# copy the new ThunderboltDROM contents
# In MaciASL, select the old ThunderboltDROM contents, then paste
etc.
 
Is there a separate TB header on the Designare?

Edit: just looked at the manual: no spare TB header so no way to put a TB card me think...
I’ll update the DROM micro guide for GC-Titan Ridge with a note on bridging pins 1 and 3 if motherboard lacks a Thunderbolt header. These cards can definitely be used without THB_C headers.

Edit: done
 
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Yes sir!
In the week-end ill deliver a version with all motherboards and PCIe cards.

Can you explain (with screenshots if possible) what is the method to calculate checksum after vendor and device name changing please?


Vendor and Device name changers are ready!
View attachment 479031
To calculate CRC32 checksum, best option is to use ThunderboltUtil. In fact you could use that to do all of the DROM manipulation. Your code would then become a GUI wrapper around ThunderboltUtil.
 
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Thanks for confirming with your experiences! Is the patched NVM 50 firmware floating around in this thread? If so would you be able to link me to it? I did some googling but wasn't able to find it. Also have you noticed any differences between patched 23 vs. patched 50?
Here's a link to the versions I tried. One with good success, the other with none. NVM23 worked well for me but I didn't stay on it long in an effort to find a way to get dual monitor support over one TB connection. I landed on NVM50 and I don't feel a need to change unless a new option becomes available.

Edit: https://www.tonymacx86.com/threads/...olt-3-i7-9700k-amd-rx-580.267551/post-2126514
 
@CaseySJ @joevt et al.

Here it is! GC-Titan Ridge Version 2.0! Attached is the freshly ripped firmware. Worked a long day so all I have done is open it, take pictures, and ripped the firmware from the blue chip. Have at it!

View attachment 479040
View attachment 479041
View attachment 479042

3Pin TB header cable
View attachment 479043
Awesome -- congratulations on being the first to own V2.0!!
  • GC-Titan Ridge Version 2.0 ships with NVM 50.
  • Extracted DROM from your firmware file, but found an issue with ThunderboltUtilregarding enabling/disabling Thunderbolt Switch.
Meanwhile, I used ThunderboltUtil in a roundabout manner to enable Thunderbolt Switch and calculate CRC-32. The new DROM string is as follows:
Code:
                                "ThunderboltDROM",
                                Buffer (0x76)
                                {
                                    /* 0000 */  0x71, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xED,  // q.......
                                    /* 0008 */  0x00, 0xD9, 0xF6, 0xC7, 0xE2, 0x01, 0x69, 0x00,  // ......i.
                                    /* 0010 */  0xED, 0x00, 0x07, 0xA2, 0x01, 0x01, 0x08, 0x81,  // ........
                                    /* 0018 */  0x80, 0x02, 0x80, 0x00, 0x00, 0x00, 0x08, 0x82,  // ........
                                    /* 0020 */  0x90, 0x01, 0x80, 0x00, 0x00, 0x00, 0x08, 0x83,  // ........
                                    /* 0028 */  0x80, 0x04, 0x80, 0x01, 0x00, 0x00, 0x08, 0x84,  // ........
                                    /* 0030 */  0x90, 0x03, 0x80, 0x01, 0x00, 0x00, 0x05, 0x85,  // ........
                                    /* 0038 */  0x50, 0x00, 0x00, 0x05, 0x86, 0x50, 0x00, 0x00,  // P....P..
                                    /* 0040 */  0x02, 0x87, 0x0B, 0x88, 0x20, 0x01, 0x00, 0x64,  // .... ..d
                                    /* 0048 */  0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x89, 0x80,  // ........
                                    /* 0050 */  0x05, 0x8A, 0x50, 0x40, 0x00, 0x05, 0x8B, 0x50,  // [email protected]
                                    /* 0058 */  0x40, 0x00, 0x0B, 0x01, 0x47, 0x49, 0x47, 0x41,  // @...GIGA
                                    /* 0060 */  0x42, 0x59, 0x54, 0x45, 0x00, 0x11, 0x02, 0x47,  // BYTE...G
                                    /* 0068 */  0x43, 0x2D, 0x54, 0x49, 0x54, 0x41, 0x4E, 0x20,  // C-TITAN
                                    /* 0070 */  0x52, 0x49, 0x44, 0x47, 0x45, 0x00               // RIDGE.
                                },
It has been added to the attached SSDT. Please use a custom UID, however (those 5 "green" bytes in the DROM Micro-Guide) and update CRC-8 (byte 1).
 

Attachments

  • SSDT-TBOLT3-RP05-PORT7-GC-TITAN-RIDGE-V2.aml
    2.3 KB · Views: 77
I’ll update the DROM micro guide for GC-Titan Ridge with a note on bridging pins 1 and 3 if motherboard lacks a Thunderbolt header. These cards can definitely be used without THB_C headers.

Edit: done
Wow, this rig could become more like a mini MacPro then...;)
 
Awesome -- congratulations on being the first to own V2.0!!
  • GC-Titan Ridge Version 2.0 ships with NVM 50.
  • Extracted DROM from your firmware file, but found an issue with ThunderboltUtilregarding enabling/disabling Thunderbolt Switch.
Meanwhile, I used ThunderboltUtil in a roundabout manner to enable Thunderbolt Switch and calculate CRC-32. The new DROM string is as follows:
Code:
                                "ThunderboltDROM",
                                Buffer (0x76)
                                {
                                    /* 0000 */  0x71, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xED,  // q.......
                                    /* 0008 */  0x00, 0xD9, 0xF6, 0xC7, 0xE2, 0x01, 0x69, 0x00,  // ......i.
                                    /* 0010 */  0xED, 0x00, 0x07, 0xA2, 0x01, 0x01, 0x08, 0x81,  // ........
                                    /* 0018 */  0x80, 0x02, 0x80, 0x00, 0x00, 0x00, 0x08, 0x82,  // ........
                                    /* 0020 */  0x90, 0x01, 0x80, 0x00, 0x00, 0x00, 0x08, 0x83,  // ........
                                    /* 0028 */  0x80, 0x04, 0x80, 0x01, 0x00, 0x00, 0x08, 0x84,  // ........
                                    /* 0030 */  0x90, 0x03, 0x80, 0x01, 0x00, 0x00, 0x05, 0x85,  // ........
                                    /* 0038 */  0x50, 0x00, 0x00, 0x05, 0x86, 0x50, 0x00, 0x00,  // P....P..
                                    /* 0040 */  0x02, 0x87, 0x0B, 0x88, 0x20, 0x01, 0x00, 0x64,  // .... ..d
                                    /* 0048 */  0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x89, 0x80,  // ........
                                    /* 0050 */  0x05, 0x8A, 0x50, 0x40, 0x00, 0x05, 0x8B, 0x50,  // [email protected]
                                    /* 0058 */  0x40, 0x00, 0x0B, 0x01, 0x47, 0x49, 0x47, 0x41,  // @...GIGA
                                    /* 0060 */  0x42, 0x59, 0x54, 0x45, 0x00, 0x11, 0x02, 0x47,  // BYTE...G
                                    /* 0068 */  0x43, 0x2D, 0x54, 0x49, 0x54, 0x41, 0x4E, 0x20,  // C-TITAN
                                    /* 0070 */  0x52, 0x49, 0x44, 0x47, 0x45, 0x00               // RIDGE.
                                },
It has been added to the attached SSDT. Please use a custom UID, however (those 5 "green" bytes in the DROM Micro-Guide) and update CRC-8 (byte 1).
I have one of these coming on Tuesday. If I were to add it to my system with rev1 version and use it without the header, would the new DROM file have any affect? Or would it need to run a patched firmware as well? Would love to do some additional testing.
 
Awesome -- congratulations on being the first to own V2.0!!

Very cool! Just to clarify, would it be the same modified FW that @gandem is talking about? or is this a new version just for this card?
 
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