[SUCCESS] Gigabyte Designare Z390 (Thunderbolt 3) + i7-9700K + AMD RX 580

[dgsga]

Progress!!

...would the lack of DSB4 in the SSDT have anything to do with this?

thanks!

@faithie999 It's great to hear you've made progress, I was beginning to wonder if anyone else could reproduce my results. You definitely need the DSB4 device under UPSB, so duplicate DSB1 and change the _ADR address to 0x00040000, like so:

Device (DSB4)
            {
                Name (_ADR, 0x00040000)  // _ADR: Address
                Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                {
                    Return (Zero)
                }
            }

To get your display to work properly you need to activate IOThunderboltPort5 (notice that it's not populated in your IOreg).To do this you need to inject your ThunderboltDROM into the NHI0 Device via OpenCore config.plist. Copy the DROM from your original firmware using HexFiend, change the UID and correct the CRC-8 checksum as per the tutorial here: https://www.tonymacx86.com/threads/...olt-3-i7-9700k-amd-rx-580.267551/post-2087139. Just upload your original firmware if you're not sure what to do and I'll fix it for you. Don't use the DROM from the tutorial, you must use the one from your card firmware

 

[rj510]

Just started looking at this. Some comments:

View attachment 467012View attachment 467013

• In the first screenshot we see that for each PCIe slot there's an External PINI declaration. This PINI function is not defined in Gigabyte's firmware.
• In the second screenshot we see the _INI method in which the code checks if a real PINI method exists (CondRefOf (PINI)) and if so, PINI is then called.
• This means we don't have to rename _INI to XINI. Instead, we just create a new method in Scope (_SB.PCI0.RP05) called PINI. And that method will be invoked automatically.

CaseySJ,

It's not clear to me what TB-related patches for flashed firmware we're to be using. I have some of what's shown in the Spoiler below included, but now don't know if this is useful. Can you clarify?

Also, what new PINI method should we include in the SSDT?

Thanks.

Spoiler: TB-related patches

 

[faithie999]

@faithie999 It's great to hear you've made progress, I was beginning to wonder if anyone else could reproduce my results. You definitely need the DSB4 device under UPSB, so duplicate DSB1 and change the _ADR address to 0x00040000, like so:

Device (DSB4)
            {
                Name (_ADR, 0x00040000)  // _ADR: Address
                Method (_RMV, 0, NotSerialized)  // _RMV: Removal Status
                {
                    Return (Zero)
                }
            }

To get your display to work properly you need to activate IOThunderboltPort@5 (notice that it's not populated in your IOreg).To do this you need to inject your ThunderboltDROM into the NHI0 Device via OpenCore config.plist. Copy the DROM from your original firmware using HexFiend, change the UID and correct the CRC-8 checksum as per the tutorial in this thread. Just upload your original firmware if you're not sure what to do and I'll fix it for you. Don't use the DROM from the tutorial, you must use the one from your card firmware

I was looking at your SSDT again. your instructions say to change _E2C to _E17 in one line of the SSDT, which I did, but in the SSDT there are two occurrences of XE2C nearby. should I change them to XE17 as well?

I thought maybe this is supposed to refer to the _GPE._E17 that I changed to _GPE.XE17 in my DSDT.

 

[dgsga]

I was looking at your SSDT again. your instructions say to change _E2C to _E17 in one line of the SSDT, which I did, but in the SSDT there are two occurrences of XE2C nearby. should I change them to XE17 as well?

I thought maybe this is supposed to refer to the _GPE._E17 that I changed to _GPE.XE17 in my DSDT.

View attachment 467518

Yes!

 

[CaseySJ]

So, @CaseySJ -

I have a GC-TitanRidge card with an NVM of 43. Do you think it would be worthwhile to flash it to NVM33 and then re-flash with one of the patches? Either from DSM2 or one of Elias64Fr's patches?

I'm getting the impression that NVM 33 has the best response so far, but then it sounds like it needs to be re-flashed and adjusted to get it work the best. Also, an SSDT must also be customized to work with it, correct?

Have I got that right?

Hello @mm2margaret,

Flashing the card with modified NVM 33 might offer the best compatibility out of the various alternatives. But it's only necessary to flash once. Then the GC-Titan Ridge Thunderbolt DROM Micro-Guide should be used to tailor the DROM and enable hot-plug.

 

[terry1958]

Hi CaseySJ,
I am using Opencore 0.5.8 and noticed this in the file

Should both these entries be in the patch file as they seem to just be a duplicate ?.

Yours Terry.

 

[scottkendall]

So, @CaseySJ -

I have a GC-TitanRidge card with an NVM of 43. Do you think it would be worthwhile to flash it to NVM33 and then re-flash with one of the patches? Either from DSM2 or one of Elias64Fr's patches?

I'm getting the impression that NVM 33 has the best response so far, but then it sounds like it needs to be re-flashed and adjusted to get it work the best. Also, an SSDT must also be customized to work with it, correct?

Have I got that right?

Maybe I am some kind of exception to the rule but I did not have to reflash the card. I have been running NVM 33 on my GC-Titan Ridge since the day Casey put it out, I had put DSM2 Firmware on the card prior. The only adjustment I made was to change out the SSDT once Casey released the DROM Micro Guide. You do not need to customize the SSDT but it is recommended it takes about 10 mins to update the SSDT with a custom DROM.

 

[CaseySJ]

CaseySJ,

It's not clear to me what TB-related patches for flashed firmware we're to be using. I have some of what's shown in the Spoiler below included, but now don't know if this is useful. Can you clarify?

Also, what new PINI method should we include in the SSDT?

Thanks.

Spoiler: TB-related patches

View attachment 467512

My comment regarding PINI was only meant for @dgsga and @faithie999 -- in particular, for the TbtOnPCH SSDT they're working on.

 

[CaseySJ]

Hi CaseySJ,
I am using Opencore 0.5.8 and noticed this in the file
View attachment 467520
Should both these entries be in the patch file as they seem to just be a duplicate ?.

Yours Terry.

If you look at TableSignature you'll see that the difference lies there! One points to DSDT, the other to SSDT. That's because SAT0 appears in both places. Technically, however, it's not necessary to change SAT0 to SATA.

 

[terry1958]

If you look at TableSignature you'll see that the difference lies there! One points to DSDT, the other to SSDT. That's because SAT0 appears in both places. Technically, however, it's not necessary to change SAT0 to SATA.

Thanks.
yours Terry.