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[SUCCESS] Gigabyte Designare Z390 (Thunderbolt 3) + i7-9700K + AMD RX 580

Please copy both of the attached SSDTs to CLOVER/ACPI/patched. Reboot and check IORegistry again.
Same... I had a DTPG with Device (RMDT) [for test purpose]. I tried original DTPG instead of.
I can't load thunderbolt properties with aml for BR3B.
BR3B.png

PCI.png
 

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  • SSDT-TBOLT3-X299_J.aml
    2.2 KB · Views: 72
Okay, I'm adding some files.....

As noted earlier, it's not really working for me. I've added my adjusted config.plist, before and after ioreg files, and my BIOS TB settings.....(these work in macOS, but only Windows style....and no tree as noted before....)
Aaah, I see you're using TitanRidge, not Alpine Ridge. Also, in your "Not_so_good" IOReg the SSDT hasn't loaded as the Thunderbolt devices aren't named correctly (NHI0, DSB0 etc. etc.). There's also some other injection going on as you've got entries like these that shouldn't be there:
Screenshot 2020-05-03 at 16.55.46.png

I would recommend removing these additional entries from your config.plist. When you see entries like this they are making life more difficult. They have no impact on function and just make things look good in the PCI section of System Profiler. I'd recommend removing all the extra injection and keep things to the bare minimum whilst testing. The only device property for thunderbolt that I'm injecting is the ThunderboltDROM with a unique UID
 
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@mm2margaret Your SSDT looks fine. I'm sorry it hasn't worked out for you. It's starting to look like this approach only works with built-in Alpine Ridge, not Add In Cards. :(
Okay, thanks for trying.....:)
SSDT approach can be adapted for add-in-cards. As long as we can determine the addresses of root port and UPSB, then most often the remaining addresses (of DSB0, NHI0, DSB1, DSB2, DSB4) can be determined using the first two.

I'll take a look at the SSDT later -- no promises, but maybe I can provide some hints.
 
Same... I had a DTPG with Device (RMDT) [for test purpose]. I tried original DTPG instead of.
I can't load thunderbolt properties with aml for BR3B.View attachment 466854
View attachment 466857
Please post the original system DSDT like this:
  • At Clover Boot Menu, press F4. Wait few seconds. Nothing will happen on screen, but files will be quietly written to disk.
  • Then boot into macOS and Mount EFI partition.
  • DSDT.aml will be in CLOVER/ACPI/origin folder.
 
SSDT approach can be adapted for add-in-cards. As long as we can determine the addresses of root port and UPSB, then most often the remaining addresses (of DSB0, NHI0, DSB1, DSB2, DSB4) can be determined using the first two.

I'll take a look at the SSDT later -- no promises, but maybe I can provide some hints.

Okay, very unexpected, but a nice surprise....thanks! And, there's no rush....I still have ICM style, for now.....
 
Okay the UberNoob returns.. sorry to be a pain.
The flashing job was painful - once I'm finalised on this I'll give you a post on what I think I may/could have done to save the stress to hopefully help others..

So home run hopefully - but I still am having trouble in what to put in the SSDT
I've gone to the CRC Calculator but in the CRC Input data window - it's already pre-filled with the same 9 bytes even before entering the given configuration from the guide.
I've generated a checksum from the given bytes but just double checking I'm doing this right..??

Screenshot 2020-05-03 at 16.44.13.png
 
Okay the UberNoob returns.. sorry to be a pain.
The flashing job was painful - once I'm finalised on this I'll give you a post on what I think I may/could have done to save the stress to hopefully help others..

So home run hopefully - but I still am having trouble in what to put in the SSDT
I've gone to the CRC Calculator but in the CRC Input data window - it's already pre-filled with the same 9 bytes even before entering the given configuration from the guide.
I've generated a checksum from the given bytes but just double checking I'm doing this right..??

View attachment 466861
Are you specifying new random numbers for the 5 green bytes in the DROM micro-guide? We need to generate a unique ID by specifying any 5 hex numbers between 0x00 and 0xFF. Then we generate a new CRC-8 checksum that goes into byte #1.
 
Are you specifying new random numbers for the 5 green bytes in the DROM micro-guide? We need to generate a unique ID by specifying any 5 hex numbers between 0x00 and 0xFF. Then we generate a new CRC-8 checksum that goes into byte #1.
Well, this is just it. There's already numbers in the box every time I visit the CRC page.
Am I to delete these and stick my own 'lottery numbers' in instead?
 
Well, this is just it. There's already numbers in the box every time I visit the CRC page.
Am I to delete these and stick my own 'lottery numbers' in instead?
Yes of course. Most of the fields on the website are populated with default values to give users some examples of how to enter values. We just delete the appropriate default values and replace them with our own.

Update: I've updated all six Thunderbolt DROM micro-guides to make this more clear (I hope). The original wording was misleading.

Screen Shot 2020-05-03 at 9.49.36 AM.png
 
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@NorthAmTransAm: you are owner of ASUS-THUNDERBOLT-EX-3. Can you provide me please a exact location of Winbond chip to flash on this card? Thank you.
81Q3jNKl4uL._AC_SX466_.jpg
 
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