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[SUCCESS] Gigabyte Designare Z390 (Thunderbolt 3) + i7-9700K + AMD RX 580

Hi all,

I remember seeing a post with detailed photos etc on how to perform the flash using CH341a. I think this post has been replaced/deleted however I have soldering experience and can apply the 3v3 rework needed for correct voltage levels on CH341a.

Rework:

Jumper set to 3v3 mode.

Would it be possible to post this again ? While I feel confident at looking at the pin outs for the programmer / device, I think it would also be helpful to have images that confirm what I am doing as correct.

Most importantly I am looking for photos that show:
Wiring Setup : Clip connection to device - Back on TR AIC, to the headers, and on the programmer

flash rom is installed and ready to use. What commands did you use to perform reads / writes.

Thanks!!

As always I assume all risk!!
Thanks,
 
The magic is: Patched NVM23 & proper ThunderboltConfig (It is specific for device path) (It took 3 days to adapt it for my devices)

Some tips:
Remember to reopen System Information windows to update Thunderbolt tree.
After update SSDT, hang...F11 from clover for clean.

[/CODE]

Could you maybe describe the process in more details, how to do to find the correct one for my board/slot? (Thunderbolt config)
 
Last edited:
Hi all,

I remember seeing a post with detailed photos etc on how to perform the flash using CH341a. I think this post has been replaced/deleted however I have soldering experience and can apply the 3v3 rework needed for correct voltage levels on CH341a.

Rework:

Jumper set to 3v3 mode.

Would it be possible to post this again ? While I feel confident at looking at the pin outs for the programmer / device, I think it would also be helpful to have images that confirm what I am doing as correct.

Most importantly I am looking for photos that show:
Wiring Setup : Clip connection to device - Back on TR AIC, to the headers, and on the programmer

flash rom is installed and ready to use. What commands did you use to perform reads / writes.

Thanks!!

As always I assume all risk!!
Thanks,
Hello @amdfun84,

Here's a link to the newly updated Mini-Guide for using CH341A. And yes, you do bear all risk and responsibility! :)

 
** New Table of Contents Added to Post #1 **

To make them easier to find, the two Mini-Guides for flashing SPI ROM chips are referenced in Post #1 in the spoiler labeled Mini-Guides for Flashing SPI ROM Chips:

Screen Shot 2020-03-05 at 8.37.33 AM.png
 
To make them easier to find, the two Mini-Guides for flashing SPI ROM chips are referenced in Post #1 in the spoiler labeled Mini-Guides for Flashing SPI ROM Chips:

Hi Casey,

I have been following the thread closely. Thank you again. Question, and maybe I missed it, but has anybody tested a flashed GB Titan Ridge add in card in the Designare Z390? I am hoping for the outcome to be 4 total usable TB3 ports.
 
So it looks like it flashed properly it shows up in the device tree, it shows up in PCI, the drives show up, but no hot swap. Also the card only shows up if something is plugged into it at boot, not even in the bios but it has always been that way.

I have no SSDT file for the thunderbolt.

As for the Alpine Ridge I could not actually find modified firmware. DSB said OSY method works for PCI alpine ridge but I am not sure I follow that method. However, if you gave me stupid simple instructions like you have been I could easily follow them.

The card is located in the bottom slot of my board its the only one that it works in and it is RP21.

Edit:

I found an old file that I was able to get Hot sawp to work with with my alpine ridge card in the past but it would crash on sleep before. It never worked with the Titian Ridge it is however, working currently sleep quickly wakes but does not crash.

View attachment 453105View attachment 453106View attachment 453107View attachment 453108

Hotswap - Works
Plugged in at boot - Works
Plugging after boot - Works
Both Ports:

BUG: if you plug something in after boot it does not populate the IOReg tree past USP0 even those the device is operational. I also noticed the Linkspeed is not 40GB maybe that is my SSDT.

Thanks for all your help so far!
Nice to see the Thunderbolt Bus! Link speed depends on LinkDetails property in the SSDT.

Screen Shot 2020-03-05 at 9.20.49 AM.png
 
** New Table of Contents Added to Post #1 **

To make them easier to find, the two Mini-Guides for flashing SPI ROM chips are referenced in Post #1 in the spoiler labeled Mini-Guides for Flashing SPI ROM Chips:

Not to be a nitpicker but in your RP guide you tied 7 & 3 together but 7 & 8 seem like a better grouping since they are next to each other but 3 is on the other side of the clip. I mean it is really 6 of 1 half dozen but if we are going for "easier" 7/8 :)

And really thank you for all the help you provided me yesterday I might have got where I am today but with a lot bigger headache! I think the RP is the way to go with the flashing mostly because it does everything standalone. It also gives you a device you can use for alternate things when you are done. A programer is just a programer when you done doing the programing.
 
Hello i have same system but after a fresh catalina install after boot it goes to black screen is there something i can do? thank you , i also attached my EFI folder to see if i did something wrong.
Hello @makspaints,

Please do not quote the entire build guide. It says so right here:
Screen Shot 2020-03-05 at 9.22.07 AM.png


Your CLOVER configuration is from a Mojave installation. If you performed a fresh installation of Catalina, did you follow the Catalina Mini-Guide located here:
 
Nice to see the Thunderbolt Bus! Link speed depends on LinkDetails property in the SSDT.

View attachment 453164

This is what I got:

Screen Shot 2020-03-05 at 9.29.21 AM.png


This is the file I am using it had another name but I changed it because it was easier to add to open core that way.
 

Attachments

  • SSDT-TBOLT3.aml
    6.2 KB · Views: 95
Hi Casey,

I have been following the thread closely. Thank you again. Question, and maybe I missed it, but has anybody tested a flashed GB Titan Ridge add in card in the Designare Z390? I am hoping for the outcome to be 4 total usable TB3 ports.
Yes this is the current hot topic -- I'm facing some issues as described in an ongoing post here:
Will continue working on this -- seems to be related mostly to SSDT configuration.
 
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