iMac Pro X299 - Live the Future now with macOS 10.14 Mojave [Successful Build/Extended Guide]

[kgp]

@kgp Is there anything that should be updated in the main document regarding X299 WS 10G support? I'm trying to get everything ready before components arrive, like drivers, etc. Also which BIOS version are you using?

There is no need to modify the main guide concerning the Sage. View necessary deviations will be briefly outlined at some adequate place.

 

[djlild7hina]

There is no need to modify the main guide concerning the Sage. View necessary deviations will be briefly outlined at some adequate place.

Yep, everything is already outlined in the guide and I already uploaded the necessary SSDT path adjustments in post 2399 as well as mentioning the fakepciid approach to enable the 10G ports. Latest bios 0905 works with above 4g encoding

 

[vincek8s]

Perfect!

 

[kgp]

Yep, everything is already outlined in the guide and I already uploaded the necessary SSDT path adjustments in post 2399 as well as mentioning the fakepciid approach to enable the 10G ports. Latest bios 0905 works with above 4g encoding

My SSDTs and your SSDTs are valid for our slot and device populations only, and need to be adapted in any case for different slot and device population, following the general guidelines. The only deviations from the guide are the two LAN kexts basically, which are not required either if one applies the Ubuntu EEPROM modding detailed in Section E.8.2.2 for the Intel X540-T1.

Thus there are no major deviations from the guidelines anyway, despite the fact that any TB adapter must be in Slot-2.

 

[djlild7hina]

My SSDTs and your SSDTs are valid for our slot and device populations only, and need to be adapted in any case for different slot and device population, following the general guidelines. The only deviations from the guide are the two LAN kexts basically, which are not required either if one applies the Ubuntu EEPROM modding detailed in Section E.8.2.2 for the Intel X540-T1.

Thus there are no major deviations from the guidelines anyway, despite the fact that any TB adapter must be in Slot-2.

Apologies I forgot I left the br1, br2, and the thunderbolt ssdts in the zip. Those are indeed slot population specific but the rest are adapted to the sage

I’ll eventually get around to the Ubuntu EEPROM modding so I can get rid of the fakepciid kexts

 

[kgp]

Apologies I forgot I left the br1, br2, and the thunderbolt ssdts in the zip. Those are indeed slot population specific but the rest are adapted to the sage

I’ll eventually get around to the Ubuntu EEPROM modding so I can get rid of the fakepciid kexts

Also the SSDTs I created and distributed for the Sage 10G quite a while ago do have onboard (fix) and slot/device specific SSDTs (variable), which is correct anyway. You should not remove your slot/device specific SSDTs from your zip either. Other users with different slot/device configurations have to adapt/create their SSDTs anyway following the respective guidelines. As most users have different slot/device configurations there is no global set of SSDTs possible for any motherboard or system anyway.

Would be also boring, wouldn't it?

 

[djlild7hina]

Also the SSDTs I created and distributed for the Sage 10G quite a while ago do have onboard (fix) and slot/device specific SSDTs (variable), which is correct anyway. You should not remove your slot/device specific SSDTs from your zip either. Other users with different slot/device configurations have to adapt/create their SSDTs anyway following the respective guidelines. As most users have different slot/device configurations there is no global set of SSDTs possible for any motherboard or system anyway.

Would be also boring, wouldn't it?

Hah! If that was the case I wouldn’t have had so much trouble adapting it with all the pci bridges last year Great learning experience though and understanding of adapting the SSDTs

 

[kgp]

Hah! If that was the case I wouldn’t have had so much trouble adapting it with all the pci bridges last year Great learning experience though and understanding of adapting the SSDTs

Yea.. who is able to manage SSDTs for the Sage is able to manage any SSDTs for any motherboard...

The X299 Sage and GA X299-WU8 have by far the most complex ACPI tables of all motherboards .. But for those controlling the underlying basics, they are just two other motherboards.

And I guess we two love crazy bridges. Much fun and at least something a little bit more intellectually demanding once...

 

[vincek8s]

@djlild7hina OK, I've read through the first post and I'm having a little trouble to map the slots to PCIEx BRxx paths. I don't have the ability to run IOREG yet, given that I don't have the hardware, can you explain how it works at a high level?

I've noticed your PC01 BR1A also has Airport Extreme definition and I assume PC02 BR2 is the disabled NVIDIA card? Which I'd need as well.

I'm gonna use the RX560 aml file and modify as needed, just need to wrap my head around the mapping between each slot and ACPI paths. Thanks!

 

[djlild7hina]

@djlild7hina OK, I've read through the first post and I'm having a little trouble to map the slots to PCIEx BRxx paths. I don't have the ability to run IOREG yet, given that I don't have the hardware, can you explain how it works at a high level?

I've noticed your PC01 BR1A also has Airport Extreme definition and I assume PC02 BR2 is the disabled NVIDIA card? Which I'd need as well.

I'm gonna use the RX560 aml file and modify as needed, just need to wrap my head around the mapping between each slot and ACPI paths. Thanks!

@kgp feel free to correct me anywhere but PC02-BR2A is typically slot-1 which is where the gpu usually is placed in most systems. The issue that makes the Sage boards more complex is that it uses a pair of plx chips which results in all of these pci-bridges. Was very difficult for me to adapt to when I was first learning but all I was missing was a couple of lines to differentiate which device was under what pci-bridge. Like @kgp said, it's definitely more demanding than other boards but is a lot easier once you get the hang of it

I believe PC02-BR2A covers slots 1,3 and PC01-BR1A covers slots 5,7 though I'm not 100% on that. I have no idea where slots 2,4,6 show up under since I haven't tried putting something in there yet. My guess is another pci-bridge will populate and it will shuffle the locations around. Thunderbolt under slot-2 actually shows up under the PCH.

Here are some examples:
Slot-1: PC02-BR2A-Pci Bridge 10
Slot-3: PC02-BR2A Pci Bridge 8
Slot-7: PC01-BR1 Pci Bridge 8

It definitely will make a lot more sense once you have ioreg and are able to look at it besides the SSDT code. Good luck!