iMac Pro X99 - Live the Future now with macOS 10.14 Mojave [Successful Build/Extended Guide]
- Thread starter kgp
- Start date
- Status
- Joined
- Mar 6, 2011
- Messages
- 52
- Motherboard
- Asus Rog Maximus XII Formula Z490
- CPU
- i9-10900K
- Graphics
- RX 6900 XT SE
- Classic Mac
- Mobile Phone
kgp
Retired
- Joined
- May 30, 2014
- Messages
- 6,743
- Motherboard
- ASUS WS X299 Sage 10G
- CPU
- i9-7980XE
- Graphics
- Vega 64
- Mac
- Mobile Phone
Upcoming iStatMenus v.6.20
Note the release of iStatMenus 6.20 Beta for testing purposes: files.bjango.com/istatmenus6/is…
Many former bugs have been apparently removed.
If you still witness remaining issues, report back to @bjango on twitter.
Enjoy and have fun,
Note the release of iStatMenus 6.20 Beta for testing purposes: files.bjango.com/istatmenus6/is…
Many former bugs have been apparently removed.
If you still witness remaining issues, report back to @bjango on twitter.
Enjoy and have fun,
Last edited:
kgp
Retired
- Joined
- May 30, 2014
- Messages
- 6,743
- Motherboard
- ASUS WS X299 Sage 10G
- CPU
- i9-7980XE
- Graphics
- Vega 64
- Mac
- Mobile Phone
Bye, Bye Nvidia...
Mojave Public Betas will certainly be my last Nvidia Web Driver disaster.
Implementing Gigabyte Radeon RX Vega 64 Gaming OC 8GB.
Revised Sections A.)- Hardware Summary, E9.2) - SSDT-ASUS-X99-A-II.aml and PCI Device Implementation, E.9.2.1) HDEF - onboard Audio Controller PCI Implementation and E.9.2.2) - GPU and HDMI/DP Audio PCI Implementation. Adding first Gigabyte Radeon RX Vega 64 Gaming OC 8GB OpenGL and Metal Benchmarks in Section F.2). Implementation of new SSDT-X99-10.14-iMacPro.aml (Default: Gigabyte Radeon RX Vega 64 Gaming OC 8GB PCI implementation. Optional: Nvidia GTX 1080 Ti implementation moved to guide text)
Enjoy and have fun,
Mojave Public Betas will certainly be my last Nvidia Web Driver disaster.
Implementing Gigabyte Radeon RX Vega 64 Gaming OC 8GB.
Revised Sections A.)- Hardware Summary, E9.2) - SSDT-ASUS-X99-A-II.aml and PCI Device Implementation, E.9.2.1) HDEF - onboard Audio Controller PCI Implementation and E.9.2.2) - GPU and HDMI/DP Audio PCI Implementation. Adding first Gigabyte Radeon RX Vega 64 Gaming OC 8GB OpenGL and Metal Benchmarks in Section F.2). Implementation of new SSDT-X99-10.14-iMacPro.aml (Default: Gigabyte Radeon RX Vega 64 Gaming OC 8GB PCI implementation. Optional: Nvidia GTX 1080 Ti implementation moved to guide text)
Enjoy and have fun,
Last edited:
- Joined
- Oct 11, 2010
- Messages
- 733
- Motherboard
- GIGABYTE Z790 Gaming X
- CPU
- i9-13900K
- Graphics
- Vega 64
- Mac
Hi KGP
I add this entry very smooth to worked THB card.
If you have this data in your SSDT please remove under UPSB,DSB0,DSB1,DSB2,DSB3,DSB4
X99 and X299-Remove
Add this data under the devices UPSB,DSB0,DSB1,DSB2,DSB3,DSB4
This data get from X99-BR1A
X99 -Add
Add this data under the devices UPSB,DSB0,DSB1,DSB2,DSB3,DSB4
This data hack from X299-BR1A
Add X299-SSDT
You have to remove same code X99 and X299
I add this entry very smooth to worked THB card.
If you have this data in your SSDT please remove under UPSB,DSB0,DSB1,DSB2,DSB3,DSB4
X99 and X299-Remove
Code:
OperationRegion (A1E1, PCI_Config, 0xC0, 0x40)
Field (A1E1, ByteAcc, NoLock, Preserve)
{
Offset (0x01),
Offset (0x02),
Offset (0x04),
Offset (0x08),
Offset (0x0A),
, 5,
TPEN, 1,
Offset (0x0C),
SSPD, 4,
, 16,
LACR, 1,
Offset (0x10),
, 4,
LDIS, 1,
LRTN, 1,
Offset (0x12),
CSPD, 4,
CWDT, 6,
, 1,
LTRN, 1,
, 1,
LACT, 1,
Offset (0x14),
Offset (0x30),
TSPD, 4
}This data get from X99-BR1A
X99 -Add
Code:
OperationRegion (MCTL, SystemMemory, 0xE0000188, 0x04)
Field (MCTL, ByteAcc, NoLock, Preserve)
{
, 3,
HGPE, 1,
, 7,
, 8,
, 8
}
Method (_INI, 0, NotSerialized) // _INI: Initialize
{
Store (0x01, HGPE)
}
Name (_HPP, Package (0x04) // _HPP: Hot Plug Parameters
{
0x08,
0x40,
0x01,
0x00
})
Name (SHPC, 0x40)
Name (SPDS, 0x40)
Name (MRLS, 0x00)
Name (CCOM, 0x10)
Name (SPDC, 0x08)
Name (MRLC, 0x04)
Name (SPFD, 0x02)
Name (SABP, 0x01)
Name (SPOF, 0x10)
Name (SPON, 0x0F)
Name (ALMK, 0x1C)
Name (ALON, 0x01)
Name (ALBL, 0x02)
Name (ALOF, 0x03)
Name (PLMK, 0x13)
Name (PLON, 0x04)
Name (PLBL, 0x08)
Name (PLOF, 0x0C)
Name (HPEV, 0x0F)
OperationRegion (PPA4, PCI_Config, 0x00, 0x0100)
Field (PPA4, ByteAcc, NoLock, Preserve)
{
Offset (0xA0),
, 4,
LDIS, 1,
Offset (0xA2),
Offset (0xA4),
ATBP, 1,
, 1,
MRSP, 1,
ATIP, 1,
PWIP, 1,
HPSR, 1,
HPCP, 1,
, 12,
PSNM, 13,
ABIE, 1,
PFIE, 1,
MSIE, 1,
PDIE, 1,
CCIE, 1,
HPIE, 1,
SCTL, 5,
Offset (0xAA),
SSTS, 7,
Offset (0xAB),
Offset (0xB0),
Offset (0xB2),
PMES, 1,
PMEP, 1,
Offset (0xB4)
}
Method (ATID, 0, NotSerialized)
{
Return (And (SCTL, 0x03))
}
Method (PWID, 0, NotSerialized)
{
Return (ShiftRight (And (SCTL, 0x0C), 0x02))
}
Method (PWCC, 0, NotSerialized)
{
Return (ShiftRight (And (SCTL, 0x10), 0x04))
}
Method (ABPS, 1, NotSerialized)
{
If (LEqual (Arg0, 0x01))
{
Or (SSTS, 0x01, SSTS)
}
Return (And (SSTS, 0x01))
}
Method (PFDS, 1, NotSerialized)
{
If (LEqual (Arg0, 0x01))
{
Or (SSTS, 0x02, SSTS)
}
Return (ShiftRight (And (SSTS, 0x02), 0x01))
}
Method (MSCS, 1, NotSerialized)
{
If (LEqual (Arg0, 0x01))
{
Or (SSTS, 0x04, SSTS)
}
Return (ShiftRight (And (SSTS, 0x04), 0x02))
}
Method (PDCS, 1, NotSerialized)
{
If (LEqual (Arg0, 0x01))
{
Or (SSTS, 0x08, SSTS)
}
Return (ShiftRight (And (SSTS, 0x08), 0x03))
}
Method (CMCS, 1, NotSerialized)
{
If (LEqual (Arg0, 0x01))
{
Or (SSTS, 0x10, SSTS)
}
Return (ShiftRight (And (SSTS, 0x10), 0x04))
}
Method (MSSC, 1, NotSerialized)
{
If (LEqual (Arg0, 0x01))
{
Or (SSTS, 0x20, SSTS)
}
Return (ShiftRight (And (SSTS, 0x20), 0x05))
}
Method (PRDS, 1, NotSerialized)
{
If (LEqual (Arg0, 0x01))
{
Or (SSTS, 0x40, SSTS)
}
Return (ShiftRight (And (SSTS, 0x40), 0x06))
}
Method (HPCC, 1, NotSerialized)
{
Store (SCTL, Local0)
Store (0x00, Local1)
If (LNotEqual (Arg0, Local0))
{
Store (Arg0, SCTL)
While (LAnd (LNot (CMCS (0x00)), LNotEqual (0x64, Local1)))
{
Store (0xFB, IO80)
Sleep (0x02)
Add (Local1, 0x02, Local1)
}
CMCS (0x01)
}
}
Method (ATCM, 1, NotSerialized)
{
Store (SCTL, Local0)
And (Local0, ALMK, Local0)
If (LEqual (Arg0, 0x01))
{
Or (Local0, ALON, Local0)
}
If (LEqual (Arg0, 0x02))
{
Or (Local0, ALBL, Local0)
}
If (LEqual (Arg0, 0x03))
{
Or (Local0, ALOF, Local0)
}
HPCC (Local0)
}
Method (PWCM, 1, NotSerialized)
{
Store (SCTL, Local0)
And (Local0, PLMK, Local0)
If (LEqual (Arg0, 0x01))
{
Or (Local0, PLON, Local0)
}
If (LEqual (Arg0, 0x02))
{
Or (Local0, PLBL, Local0)
}
If (LEqual (Arg0, 0x03))
{
Or (Local0, PLOF, Local0)
}
HPCC (Local0)
}
Method (PWSL, 1, NotSerialized)
{
Store (SCTL, Local0)
If (Arg0)
{
And (Local0, SPON, Local0)
}
Else
{
Or (Local0, SPOF, Local0)
}
HPCC (Local0)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
Switch (And (Arg0, 0xFF))
{
Case (0x03)
{
Switch (ToInteger (Arg1))
{
Case (Package (0x04)
{
0x80,
0x81,
0x82,
0x83
}
)
{
If (LNot (PWCC ()))
{
PWCM (0x01)
Store (0x01, ABIE)
}
}
}
}
}
}
Method (EJ0L, 1, NotSerialized)
{
Store (0xFF, IO80)
Store (SCTL, Local0)
If (LNotEqual (ATID (), 0x01))
{
And (Local0, ALMK, Local0)
Or (Local0, ALBL, Local0)
}
HPCC (Local0)
Store (SCTL, Local0)
Or (Local0, SPOF, Local0)
HPCC (Local0)
Store (SCTL, Local0)
Or (Local0, PLOF, Local0)
HPCC (Local0)
Store (SCTL, Local0)
Or (Local0, ALOF, Local0)
HPCC (Local0)
}
Method (PMEH, 1, NotSerialized)
{
If (And (HPEV, SSTS))
{
If (ABPS (0x00))
{
ABPS (0x01)
Sleep (0xC8)
}
}
Return (0xFF)
}
Method (HPEH, 1, NotSerialized)
{
If (LNot (HPCP))
{
Return (0xFF)
}
Store (0xFE, IO80)
Sleep (0x64)
Store (0x00, CCIE)
If (And (HPEV, SSTS))
{
Store (0xFD, IO80)
Sleep (0x0A)
Store (PPXH (0x00), Local0)
Return (Local0)
}
Else
{
Return (0xFF)
}
Store (0xFC, IO80)
Sleep (0x0A)
}
Method (PPXH, 1, NotSerialized)
{
Sleep (0xC8)
If (ABPS (0x00))
{
If (LNot (PRDS (0x00)))
{
Store (0x01, LDIS)
PWSL (0x00)
PWCM (0x03)
If (LEqual (MSSC (0x00), MRLS))
{
ATCM (0x02)
}
Else
{
ATCM (0x03)
}
ABPS (0x01)
Sleep (0xC8)
Return (0xFF)
}
Store (0x00, ABIE)
ABPS (0x01)
Sleep (0xC8)
If (PWCC ())
{
ATCM (0x02)
Sleep (0x0258)
Store (0x0258, Local0)
ABPS (0x01)
While (LNot (ABPS (0x00)))
{
Sleep (0xC8)
Add (Local0, 0xC8, Local0)
If (LEqual (0x1388, Local0))
{
Store (0x01, ABIE)
ATCM (0x03)
PWCM (0x02)
Sleep (0x0258)
Store (0x00, LDIS)
PWSL (0x01)
Sleep (0x01F4)
If (LNot (PFDS (0x00)))
{
PWCM (0x01)
Store (0x00, Local1)
Store (0x01, ABIE)
}
Else
{
PWSL (0x00)
PWCM (0x03)
ATCM (0x01)
Store (0x01, LDIS)
Store (0x03, Local1)
Store (0x01, ABIE)
}
ABPS (0x01)
Sleep (0xC8)
Return (Local1)
}
}
Return (0xFF)
}
Else
{
ATCM (0x02)
Sleep (0x0258)
Store (0x0258, Local0)
ABPS (0x01)
Sleep (0xC8)
While (LNot (ABPS (0x00)))
{
Sleep (0xC8)
Add (Local0, 0xC8, Local0)
If (LEqual (0x1388, Local0))
{
ABPS (0x01)
ATCM (0x03)
PWCM (0x02)
Sleep (0xC8)
Store (0x01, ABIE)
Store (0x01, LDIS)
PWCM (0x03)
Return (0x03)
}
}
PWCM (0x01)
ABPS (0x01)
Sleep (0xC8)
Store (0x01, ABIE)
Return (0xFF)
}
}
If (PFDS (0x00))
{
PFDS (0x01)
PWSL (0x00)
PWCM (0x03)
ATCM (0x01)
Store (0x01, LDIS)
Return (0x03)
}
If (PDCS (0x00))
{
PDCS (0x01)
If (LNot (PRDS (0x00)))
{
PWSL (0x00)
PWCM (0x03)
If (LEqual (MSSC (0x00), MRLS))
{
ATCM (0x02)
}
Else
{
ATCM (0x03)
}
Store (0x01, LDIS)
Return (0xFF)
}
Else
{
Store (0x00, LDIS)
ABPS (0x01)
Sleep (0xC8)
Store (0x01, ABIE)
Sleep (0xC8)
Return (Local1)
}
}
Return (0xFF)
}
Method (SNUM, 0, Serialized)
{
Store (PSNM, Local0)
Return (Local0)
}This data hack from X299-BR1A
Add X299-SSDT
Code:
OperationRegion (MCTL, SystemMemory, 0x60000188, 0x04)
Field (MCTL, ByteAcc, NoLock, Preserve)
{
, 3,
HGPE, 1,
, 7,
, 8,
, 8
}
Method (_INI, 0, NotSerialized) // _INI: Initialize
{
Store (0x01, HGPE)
}
Name (_HPP, Package (0x04) // _HPP: Hot Plug Parameters
{
0x08,
0x40,
0x01,
0x00
})
Name (SHPC, 0x40)
Name (SPDS, 0x40)
Name (MRLS, 0x00)
Name (CCOM, 0x10)
Name (SPDC, 0x08)
Name (MRLC, 0x04)
Name (SPFD, 0x02)
Name (SABP, 0x01)
Name (SPOF, 0x10)
Name (SPON, 0x0F)
Name (ALMK, 0x1C)
Name (ALON, 0x01)
Name (ALBL, 0x02)
Name (ALOF, 0x03)
Name (PLMK, 0x13)
Name (PLON, 0x04)
Name (PLBL, 0x08)
Name (PLOF, 0x0C)
Name (HPEV, 0x0F)
OperationRegion (PPA4, PCI_Config, 0x00, 0x0100)
Field (PPA4, ByteAcc, NoLock, Preserve)
{
Offset (0xA0),
, 4,
LDIS, 1,
Offset (0xA2),
Offset (0xA4),
ATBP, 1,
, 1,
MRSP, 1,
ATIP, 1,
PWIP, 1,
, 14,
PSNM, 13,
ABIE, 1,
PFIE, 1,
MSIE, 1,
PDIE, 1,
CCIE, 1,
HPIE, 1,
SCTL, 5,
Offset (0xAA),
SSTS, 7,
Offset (0xAB),
Offset (0xB0),
Offset (0xB2),
PMES, 1,
PMEP, 1,
Offset (0xB4)
}
Method (ATID, 0, NotSerialized)
{
Return (And (SCTL, 0x03))
}
Method (PWID, 0, NotSerialized)
{
Return (ShiftRight (And (SCTL, 0x0C), 0x02))
}
Method (PWCC, 0, NotSerialized)
{
Return (ShiftRight (And (SCTL, 0x10), 0x04))
}
Method (ABPS, 1, NotSerialized)
{
If (LEqual (Arg0, 0x01))
{
Or (SSTS, 0x01, SSTS)
}
Return (And (SSTS, 0x01))
}
Method (PFDS, 1, NotSerialized)
{
If (LEqual (Arg0, 0x01))
{
Or (SSTS, 0x02, SSTS)
}
Return (ShiftRight (And (SSTS, 0x02), 0x01))
}
Method (MSCS, 1, NotSerialized)
{
If (LEqual (Arg0, 0x01))
{
Or (SSTS, 0x04, SSTS)
}
Return (ShiftRight (And (SSTS, 0x04), 0x02))
}
Method (PDCS, 1, NotSerialized)
{
If (LEqual (Arg0, 0x01))
{
Or (SSTS, 0x08, SSTS)
}
Return (ShiftRight (And (SSTS, 0x08), 0x03))
}
Method (CMCS, 1, NotSerialized)
{
If (LEqual (Arg0, 0x01))
{
Or (SSTS, 0x10, SSTS)
}
Return (ShiftRight (And (SSTS, 0x10), 0x04))
}
Method (MSSC, 1, NotSerialized)
{
If (LEqual (Arg0, 0x01))
{
Or (SSTS, 0x20, SSTS)
}
Return (ShiftRight (And (SSTS, 0x20), 0x05))
}
Method (PRDS, 1, NotSerialized)
{
If (LEqual (Arg0, 0x01))
{
Or (SSTS, 0x40, SSTS)
}
Return (ShiftRight (And (SSTS, 0x40), 0x06))
}
Method (HPCC, 1, NotSerialized)
{
Store (SCTL, Local0)
Store (0x00, Local1)
If (LNotEqual (Arg0, Local0))
{
Store (Arg0, SCTL)
While (LAnd (LNot (CMCS (0x00)), LNotEqual (0x64, Local1)))
{
Store (0xFB, IO80)
Sleep (0x02)
Add (Local1, 0x02, Local1)
}
CMCS (0x01)
}
}
Method (ATCM, 1, NotSerialized)
{
Store (SCTL, Local0)
And (Local0, ALMK, Local0)
If (LEqual (Arg0, 0x01))
{
Or (Local0, ALON, Local0)
}
If (LEqual (Arg0, 0x02))
{
Or (Local0, ALBL, Local0)
}
If (LEqual (Arg0, 0x03))
{
Or (Local0, ALOF, Local0)
}
HPCC (Local0)
}
Method (PWCM, 1, NotSerialized)
{
Store (SCTL, Local0)
And (Local0, PLMK, Local0)
If (LEqual (Arg0, 0x01))
{
Or (Local0, PLON, Local0)
}
If (LEqual (Arg0, 0x02))
{
Or (Local0, PLBL, Local0)
}
If (LEqual (Arg0, 0x03))
{
Or (Local0, PLOF, Local0)
}
HPCC (Local0)
}
Method (PWSL, 1, NotSerialized)
{
Store (SCTL, Local0)
If (Arg0)
{
And (Local0, SPON, Local0)
}
Else
{
Or (Local0, SPOF, Local0)
}
HPCC (Local0)
}
Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
{
Switch (And (Arg0, 0xFF))
{
Case (0x03)
{
Switch (ToInteger (Arg1))
{
Case (Package (0x04)
{
0x80,
0x81,
0x82,
0x83
}
)
{
If (LNot (PWCC ()))
{
PWCM (0x01)
Store (0x01, ABIE)
}
}
}
}
}
}
Method (EJ0L, 0, NotSerialized)
{
Store (0xFF, IO80)
Store (SCTL, Local0)
If (LNotEqual (ATID (), 0x01))
{
And (Local0, ALMK, Local0)
Or (Local0, ALBL, Local0)
}
HPCC (Local0)
Store (SCTL, Local0)
Or (Local0, SPOF, Local0)
HPCC (Local0)
Store (SCTL, Local0)
Or (Local0, PLOF, Local0)
HPCC (Local0)
Store (SCTL, Local0)
Or (Local0, ALOF, Local0)
HPCC (Local0)
}
Method (PMEH, 1, NotSerialized)
{
If (And (HPEV, SSTS))
{
If (ABPS (0x00))
{
Store (Arg0, IO80)
ABPS (0x01)
Sleep (0xC8)
}
}
Return (0xFF)
}
Method (HPEH, 1, NotSerialized)
{
Store (0xFE, IO80)
Sleep (0x64)
Store (0x00, CCIE)
If (And (HPEV, SSTS))
{
Store (0xFD, IO80)
Sleep (0x0A)
Store (Arg0, IO80)
Sleep (0x0A)
Store (PPXH (), Local0)
Return (Local0)
}
Else
{
Return (0xFF)
}
Store (0xFC, IO80)
Sleep (0x0A)
}
Method (PPXH, 0, NotSerialized)
{
Sleep (0xC8)
If (ABPS (0x00))
{
If (LNot (PRDS (0x00)))
{
Store (0x01, LDIS)
PWSL (0x00)
PWCM (0x03)
If (LEqual (MSSC (0x00), MRLS))
{
ATCM (0x02)
}
Else
{
ATCM (0x03)
}
Store (0x00, ABIE)
ABPS (0x01)
Sleep (0xC8)
Return (0xFF)
}
Store (0x00, ABIE)
ABPS (0x01)
Sleep (0xC8)
If (PWCC ())
{
PWCM (0x03)
ATCM (0x02)
Return (0xFF)
}
Else
{
PWCM (0x02)
Sleep (0x0258)
Store (0x0258, Local0)
ABPS (0x01)
Sleep (0xC8)
While (LNot (ABPS (0x00)))
{
Sleep (0xC8)
Add (Local0, 0xC8, Local0)
If (LEqual (0x1388, Local0))
{
ABPS (0x01)
Sleep (0xC8)
Return (0x03)
}
}
PWCM (0x01)
ABPS (0x01)
Sleep (0xC8)
Store (0x01, ABIE)
Return (0xFF)
}
}
If (PFDS (0x00))
{
PFDS (0x01)
PWSL (0x00)
PWCM (0x03)
ATCM (0x01)
Store (0x01, LDIS)
Return (0x03)
}
If (MSCS (0x00))
{
MSCS (0x01)
If (LEqual (MSSC (0x00), MRLS))
{
If (PRDS (0x00))
{
ATCM (0x03)
PWCM (0x02)
Sleep (0x0258)
Store (0x0258, Local0)
ABPS (0x01)
While (LNot (ABPS (0x00)))
{
Sleep (0xC8)
Add (Local0, 0xC8, Local0)
If (LEqual (0x1388, Local0))
{
Store (0x01, ABIE)
ATCM (0x03)
Store (0x00, LDIS)
PWSL (0x01)
Sleep (0x01F4)
If (LNot (PFDS (0x00)))
{
PWCM (0x01)
Store (0x00, Local1)
Store (0x01, ABIE)
}
Else
{
PWSL (0x00)
PWCM (0x03)
ATCM (0x01)
Store (0x01, LDIS)
Store (0x03, Local1)
}
ABPS (0x01)
Sleep (0xC8)
Return (Local1)
}
}
ABPS (0x01)
Sleep (0xC8)
PWSL (0x00)
PWCM (0x03)
ATCM (0x02)
Store (0x01, LDIS)
Return (0xFF)
}
PWSL (0x00)
PWCM (0x03)
ATCM (0x02)
Store (0x01, LDIS)
Return (0xFF)
}
Else
{
If (PRDS (0x00))
{
ATCM (0x02)
If (LNot (PWCC ()))
{
PWSL (0x00)
PWCM (0x03)
Store (0x01, LDIS)
Return (0x03)
}
Else
{
Return (0xFF)
}
}
ATCM (0x03)
Return (0xFF)
}
}
If (PDCS (0x00))
{
PDCS (0x01)
If (LNot (PRDS (0x00)))
{
PWSL (0x00)
PWCM (0x03)
If (LEqual (MSSC (0x00), MRLS))
{
ATCM (0x02)
}
Else
{
ATCM (0x03)
}
Store (0x01, LDIS)
Return (0xFF)
}
Else
{
Store (0x00, LDIS)
PWSL (0x01)
Sleep (0x01F4)
If (LNot (PFDS (0x00)))
{
PWCM (0x01)
Store (0x00, Local1)
Store (0x01, ABIE)
ATCM (0x03)
}
Else
{
PWSL (0x00)
PWCM (0x03)
ATCM (0x01)
Store (0x01, LDIS)
Store (0x03, Local1)
}
ABPS (0x01)
Sleep (0xC8)
Return (Local1)
}
}
Return (0xFF)
}
Method (SNUM, 0, Serialized)
{
Store (PSNM, Local0)
Return (Local0)
}
Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
{
Return (Package (0x02)
{
0x69,
0x04
})
}
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
{
If (PICM)
{
Return (AG0F)
}
Return (PG0F)
}
Last edited:
kgp
Retired
- Joined
- May 30, 2014
- Messages
- 6,743
- Motherboard
- ASUS WS X299 Sage 10G
- CPU
- i9-7980XE
- Graphics
- Vega 64
- Mac
- Mobile Phone
Hi, @nmano, my friend!
I am back from holidays, finally.. just arrived to Berlin..
Please check x99 and x299 Asus Combo files attached below..
Everything implemented as desired?
Seems there is no change in TB performance and functionality though...
Cheers,
KGP
Last edited:
- Joined
- Oct 11, 2010
- Messages
- 733
- Motherboard
- GIGABYTE Z790 Gaming X
- CPU
- i9-13900K
- Graphics
- Vega 64
- Mac
Hi KGPHi, @nmano, my friend!
I am back from holidays, finally.. just arrived to Berlin..
Please check x99 and x299 Asus Combo files attached below..
Everything implemented as desired?
Seems there is no change in TB performance and functionality though...
Cheers,
KGP
How is your holidays?
I thing this Combo is fine
Please check X299 kernel log
If you have more errors change to Method name _L69 to _L70
kgp
Retired
- Joined
- May 30, 2014
- Messages
- 6,743
- Motherboard
- ASUS WS X299 Sage 10G
- CPU
- i9-7980XE
- Graphics
- Vega 64
- Mac
- Mobile Phone
See the following ACPI errors during boot on X299 under 10.14 PB3:
Sorry for the bad image quality..
- Status